Abstract: A method for testing a reliability of a solid-state storage medium is provided, wherein the solid-state storage medium has a plurality of blocks. First, a lifetime of each of the blocks of the solid-state storage medium is obtained. Then, an erase count of each of the blocks is obtained, and whether the erase count is greater than a predetermined erase count is determined. After that, those blocks having their erase counts greater than the predetermined erase count are accumulated to generate a problematic block number, and a test report is output.

Abstract: A method for testing a storage apparatus, which includes: (a) writing a specific pattern to a storage unit of a storage apparatus; (b) reading the specific pattern written to the storage apparatus; (c) determining an error bit number of the specific pattern read in the step (b); and (d) determining that the storage unit has defect when the error bit number is larger than a error bit threshold value, wherein the error bit threshold value is smaller than a correctable bit number for a error correction code corresponding to the specific pattern.

Abstract: A semiconductor memory device comprises a plate voltage generating circuit that generates a plate voltage supplied to a memory cell array and a plate voltage supply terminal that supplies a plate voltage from the outside. A first switching circuit is provided to switch the supply of the plate voltage between the supply from the plate voltage generating circuit and the supply from the outside through the plate voltage supply terminal.

Abstract: A processor operation inspection system includes a processor and an operation inspection circuit that inspects an operation of the processor. When a program under execution changes from one predefined state to another state, the processor outputs a state switching signal indicating a transition of its state, a state signal indicating a current state to the inspection circuit. The inspection circuit includes a state register that stores the state of the processor, a combinational logic circuit that calculates, according to the stored state of the processor and the state switching signal, a new state to be taken by the processor, and a comparison circuit that inspects the operation of the processor by comparing the calculated new state to the state of the processor inputted as the state signal.

Abstract: Various embodiments include apparatus and methods to store data in a first semiconductor memory unit and to store error correction information in a second semiconductor memory unit to recover the data. The error correction information has a value equal to at least the value of the data store in the first memory unit.

Abstract: An apparatus and method for testing a digital device or software installed in the digital device are provided. According to one aspect, the apparatus for testing the digital device or software installed in the digital device includes a test agent for providing a test execution environment, and the test agent performs a test for each test case in response to a command from a test director. The test agent may report an execution state of the test to the test director, and the test director may generate a test result report based on the report or resumes the test upon generation of error.

Abstract: A computer apparatus includes a first processor, a second processor, and a main memory. The computer apparatus further includes a memory-diagnostic unit, a diagnostic-program loading unit, and a defective-function identifying unit. The memory-diagnostic unit causes the second processor to execute a memory-diagnostic program to diagnose the main memory, and identifies a defective area in the main memory. The diagnostic-program loading unit loads a processor-diagnostic program for diagnosing a plurality of functions of the first processor into an area of the main memory other than the defective area identified by the memory-diagnostic unit. The defective-function identifying unit causes the second processor to execute the processor-diagnostic program loaded by the diagnostic-program loading unit, and identifies a defective function that is disabled from the functions of the first processor.

Abstract: An apparatus for testing setup/hold time includes a plurality of data input units, each configured to calibrate setup/hold time of input data in response to selection signals and setup/hold calibration signals, and an off-chip driver calibration unit configured to generate the selection signals and the setup/hold calibration signals by using the input data input of one of the plurality of data input units.

Abstract: A bad block identification method for a memory is provided. The memory includes at least one memory block for storing data. A data decoding function is performed to the data, and it is determined whether the data decoding function was performed successfully. If the data decoding function was not performed successfully, at least one predetermined location in the memory block is checked. It is determined whether the predetermined location is marked by predetermined information. If the predetermined location is not marked by the predetermined information, the memory block is identified as a bad block.

Abstract: Methods, apparatus and systems pertain to performing READ, WRITE functions in a memory which is coupled to a repair controller. One such repair controller could receive a row address and a column address associated with the memory and store a first plurality of tag fields indicating a type of row/column repair to be performed for at least a portion of a row/column of memory cells, and a second plurality of tag fields to indicate a location of memory cells used to perform the row/column repair.

Abstract: A system that provides large instruction sets for testing memory yet reduces area overhead is disclosed. The system for testing a memory of an integrated circuit comprises a set of registers providing element based programmability for a plurality of tests, wherein each test includes a plurality of test elements; a finite state machine for receiving a plurality of test instructions from the set of registers, wherein the finite state machine dispatches signals instructing a test pattern generator to generate a test pattern; a memory control module for applying the generated test pattern to the memory; and a comparator module for comparing a response received from the memory to a stored, known response.

Abstract: Disclosed are a method, system and computer program product for determining hardware diagnostics during initial program loading (IPL). A space is allocated for a diagnostics hardware table storing hardware identifications corresponding to hardware to be tested. A hardware monitor function detects new and/or defective hardware. Hardware can be manually selected. A runtime diagnostics detects defective hardware. The hardware identifications corresponding to the new, failing, and/or selected hardware are added to the diagnostics hardware table. The hardware identification to be tested is acquired during the building of a system Hardware Objects Model (HOM). A diagnostics flag is set within HOM according to the diagnostics hardware table. Diagnostics are performed per HOM diagnostics flag indication. The diagnostics table is cleared, and the operating system is run. At system runtime, diagnostics code monitors for runtime error.

Abstract: A test system includes a memory device having a data I/O circuit connected to a data write-in path and a data read-out path. During test mode, the data I/O circuit retains a copy of test pattern data received in the I/O circuit via the data write-in path as output test data before the test pattern data is stored in a memory cell array as write data. The test system also includes a test device generating the test pattern data, receiving the output test data from the memory device, comparing the output test data with the test pattern data, and generating an error detection signal on the basis of the comparison. The error detection signal indicates the presence or absence of a defect in the data write-in or read-out path.

Abstract: Embodiments herein provide data recovery techniques and configurations for solid state memory devices. For example, a method includes identifying a hard error associated with a cell of a solid state memory device, providing a location of the cell having the identified hard error to a decoder to recover data originally programmed to the cell, and recovering the data originally programmed to the cell using the decoder. Other embodiments may be described and/or claimed.

Abstract: To provide a memory system which determines a memory state such as an exhaustion level and allows a memory to be efficiently used. The memory system includes a NAND type flash memory 1 in which data can be electrically written/erased, a nonvolatile memory 2 which counts the number of erase operations of the NAND type flash memory 1 and retains the number of erase operations and a maximum number of erase operations, and a controller 3 which has a connection interface 31 to be given a self-diagnosis command from a computer 4, and retrieves the number of erase operations and the maximum number of erase operations from the nonvolatile memory 2 based on the self-diagnosis command and outputs the number of erase operations and the maximum number of erase operations to the computer 4 through the connection interface 31.

Abstract: Techniques to manage various errors in memory such as, e.g., NAND memory in electronic devices are disclosed. In some embodiments, erase, read, and program error handling errors are managed.

Abstract: A method of automatic recovery from a boot device failure and an initial program load (IPL) failure of an operating system (OS) comprises: receiving and complying with a user selected option of an action upon an event of a boot device failure and an IPL failure. The user selected option may consist of taking the action of attempting an auto reboot of the server with the selected boot device and continuing the reboot attempts using the reduced priority boot devices from the bootlist until detection of a boot success, or taking no action allowing for manual user intervention.

Abstract: A basic input output system (BIOS) test system includes a protocol conversion module and a computer. The protocol conversion module is connected to a tested device. The computer is connected to the protocol conversion module. The computer controls the protocol conversion module to simulate a keyboard to send keyboard commands to the device. The computer storing correct setting lists and comments of the setting lists of the BIOS. The tested device selects setting lists and comments thereof according to the keyboard selection commands sent by the protocol conversion module. The tested device is connected to the computer to deliver selected setting lists and comments thereof to the computer. The computer compares the selected setting lists and comments thereof with the correct setting lists.

Abstract: A memory test device, including a universal register to conduct an operation by a predetermined universal command language; an extension register having a larger capacity than the universal register and to conduct an operation by a predetermined extension command language; and a controller to write a predetermined test pattern in an external memory using the extension command language, to read the test pattern written in the memory, to determine the identity of the written test pattern and the read test pattern, and to determine a presence of an error in the memory using the universal command language.

Abstract: A method of a method of replacing bad sectors in a Hard Disk Drive comprises detecting bad sectors on the Hard Disk Drive; remapping the bad sectors to an auxiliary data storage device comprising an Magnetoresistive Random Access Memory connected to the Hard Disk Drive; and storing data on the auxiliary storage device.

Abstract: Provided are a field mounting-type test apparatus and method, which can enhance competitiveness of a product by simulating various test conditions including a mounting environment so as to improve quality reliability of a memory device and by minimizing overall loss due to change in a mounting environment so as to reduce testing time and cost. In accordance with example embodiments, the field mounting-type test apparatus may include a mass storage device configured to store logic data simulating a mounting environment of a device under test (DUT) and a tester main frame configured to test the DUT by using the logic data.

Abstract: A test apparatus includes an up counter, a down counter, a selector that selects either an up counter output from the up counter or a down counter output from the down counter, an inversion circuit that inverts either the counter output selected by the selector or the counter output nonselected by the selector, and a comparison circuit that compares the counter output inverted by the inversion circuit and the other counter output.

Abstract: There is disclosed a test circuit for testing an integrated circuit containing at least one write-only register and providing at least one output signal through at least one output pin. The test circuit may include a test mode decoder circuit to enable a test mode and a data selector circuit to select at least a portion of data stored in the at least one write-only register as test data. The test data may be output from the integrated circuit through the at least one output pin.

Abstract: An apparatus, system, and method are disclosed for bad block remapping. A bad block identifier module identifies one or more data blocks on a solid-state storage element as bad blocks. A log update module writes at least a location of each bad block identified by the bad block identifier module into each of two or more redundant bad block logs. A bad block mapping module accesses at least one bad block log during a start-up operation to create in memory a bad block map. The bad block map includes a mapping between the bad block locations in the bad block log and a corresponding location of a replacement block for each bad block location. Data is stored in each replacement block instead of the corresponding bad block. The bad block mapping module creates the bad block map using one of a replacement block location and a bad block mapping algorithm.

Abstract: A semiconductor integrated circuit device related to an embodiment of the present invention includes an address register which includes an internal selection circuit connected with a control circuit, a signal generation instruction circuit which instructs the control circuit so that a predetermined internal control signal is generated, a latch circuit, a plurality of which are arranged corresponding to a number of bits of test parameter data, the latch circuit latching test result data which is provided from the data program/read circuit and outputting the test result data to the selection circuit and externally, the control circuit generating an internal control signal which activates the selection circuit at a timing at which a fixed value data of the test parameter data is changed, and the selection circuit controlling a test so that a fixed value data of the test parameter data is changed.

Abstract: Parallel bit test circuits for use in a semiconductor memory devices are provided which include a first bus that has N bus lines that are configured to transfer a first group of N bits of test result data and a second bus that has N bus lines that are configured to transfer a second group of N bits of test result data. These parallel bit test circuits further include a switching unit that has a plurality of unit switches, where each switch is configured to connect a bus line of the first bus and a respective bus line of the second bus in response to a switching control signal that is applied after the second group of N bits of test result data are output from the second bus, to transfer the first group of N bits of test result data from the first bus to the second bus so as to output a total of 2N bits of test result data through the second bus.

Abstract: A semiconductor memory device comprises a RAM (Random Access Memory), an ODT (On-Die Termination) circuits and a JTAG (Joint Test Action Group) circuit. The RAM is connected to a data input-output port. The ODT circuit is provided between the data input-output port and a termination port. The JTAG circuit controls the ODT circuit in response to an instruction such that the data input-output port and the termination port are electrically connected with each other.

Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.

Abstract: Provided is a semiconductor memory apparatus that may use an efficient protocol between an NAND flash memory device and a controller to reduce bus traffic. The flash memory device may include a memory cell array and an error correction encoder. The memory cell array may include a plurality of pages. The error correction encoder may generate first parity data based on normal data to be written to the memory cell array, compare the first parity data and second parity data encoded with the normal data stored in the memory cell array, and check an error. The error position detector may detect an error position in response to the error signal transmitted from the error correction encoder. Thus, since the semiconductor memory apparatus may transmit and receives parity data or a syndrome between an NAND flash memory device and the controller by detecting and correcting an error in the same memory chip, bus traffic may be reduced.

Abstract: A method of controlling a memory device connectable to a host for sending out a command to the memory device, having a medium including a plurality of sectors, a head for writing data into and reading data from the medium, and a buffer memory for storing information, the method has receiving information indicating an error of data read out from a sector by the memory device and storing identification information of the sector where the error has been detected in the buffer memory and receiving information indicating an error of data read out from a sector by the host and storing in the buffer memory identification information of the sector where the error has been detected such that in the absence of vacant area in the buffer memory, the identification information is written over into an address where information of sector error detected by the memory device has been stored.

Abstract: The data detecting apparatus may provide a voltage comparison unit that compares a reference voltage, associated with a specific data bit from among a plurality of data bits stored in a memory cell, with a threshold voltage in the memory cell, a detection unit that detects a value of the specific data bit based on a result of the voltage comparison unit, and a decision unit that decides whether the specific data bit is successfully detected based on whether an error occurs in the detected data. The detection unit may re-detect a value of the specific data bit based on detection information with respect to at least one of an upper data bit and a lower data bit in relation to the specific data bit, in response to a result of the decision unit.

Abstract: A method includes providing an integrated circuit having a plurality of debug resources. The debug resources are usable exclusively for debug operations. The debug operations include operations directed by debug software executed by the integrated circuit and operations directed by external debug hardware which is external to the integrated circuit. The method further includes enabling availability of a first portion of the debug resources for use by the debug software, where a second portion of the debug resources are committed for exclusive use by the external debug hardware. The first portion is exclusive of the second portion. The method includes performing operations directed by the debug software using at least one debug resource of the first portion of the debug resources and operations directed by the external debug hardware using at least one debug resource of the second portion of the debug resources.

Abstract: In the method for operating a memory device which has a number of blocks, blocks are marked as intact, suspect, or defective. Blocks marked as suspect are monitored. A device for operating a memory device and a memory device.

Abstract: A method of an apparatus for diagnosing a memory including a storing module for storing diagnosis information relating to memory errors in a memory to be diagnosed, the apparatus capable of detecting memory errors, the method includes: testing the memory and detecting a memory error for each of a plurality of areas of the memory; dividing at least one of the areas into a plurality of sub-areas upon detection of a memory error in the at least one of the areas; testing the sub-areas and detecting a memory error for each of the plurality of the sub-areas; counting the number of sub-areas where a memory error is detected; and storing information of the number of the sub-areas where a memory error is detected together with information of the at least one of the areas containing the sub-areas into the storing module.

Abstract: A semiconductor memory test device and method thereof are provided. The example semiconductor memory test device may include a fail memory configured to store at least one test result of a memory under test, a mode selecting unit configured to output a selection signal for selecting a memory address protocol of the fail memory based upon which one of a plurality of test modes is active in the memory under test and an address arranging unit configured to arrange address signals to conform with the selected memory address protocol in response to the selection signal received from the mode selecting unit.

Abstract: A storage medium managing device is provided which can employ a set of management information containing suitable information from a plural sets of management information contained in the storage medium. An optical disc apparatus (1) manages an optical disc (2) having a plurality of management areas for containing management information with which data is managed and which is recorded in the management areas in a predetermined sequence. The apparatus includes a management information retrieving section (52) for reading the management information in the same sequence as the predetermined recording sequence to retrieve primary management information which is management information that is first retrieved normally.

Abstract: A diagnostic interface architecture for a memory device supports in one aspect one or more dynamically reconfigurable functional interconnects normally utilized in connection with reading data from the memory device and/or writing data to the memory device. The dynamically reconfigurable functional interconnects are capable of being configured to operate in either functional or diagnostic modes, whereby in the diagnostic mode, such interconnects may be used to communicate diagnostic information to support one or more diagnostic operations. The diagnostic interface architecture may also support multiple diagnostic interfaces in a given memory device, with at least one such diagnostic interface being capable of being selectively enabled in response to a failure in another diagnostic interface.

Abstract: A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.

Abstract: A semiconductor memory device includes an alignment unit configured to align data received from the outside, a plurality of data input/output lines corresponding to the aligned data, respectively and a realignment unit configured to change correspondence between the data and the data input/output lines in response to one or more change signals in a test mode. A method for testing the semiconductor memory device includes inputting data in series using a testing apparatus, aligning the serial data in parallel, and realigning the parallel data in response to one or more change signals.

Abstract: A partial voltage level read is made on memory cells of a solid state memory device during a voltage settling time after the memory cells are charged (e.g., by a pulse from a charge pump). Digital values representing partial voltage levels are checked for errors (e.g., by an error correction code (ECC) engine). If the values can be corrected, then the values are released for host access. If the values cannot be corrected, then a full voltage read is performed on the memory cells after the voltage levels have substantially settled. Digital values corresponding to the full voltage reads can be released for host access. The use of partial voltage reads results in faster read of solid state memory devices.

Abstract: Disclosed is an arrangement for testing an embedded circuit as part of a whole circuit located on a semiconductor wafer. Disclosed is an integrated semiconductor arrangement comprising a whole circuit (8) with inputs and outputs (7), an embedded circuit (1) that is part of the whole circuit (8) and is equipped with embedded inputs and outputs which are not directly connected to the inputs and outputs (7) of the whole circuit (8); a test circuit (2, 5, 6) that is connected to the embedded inputs and outputs in order to feed and read out signals during a test phase. A separate supply voltage connection (3) is provided which is used for separately supplying the embedded circuit (1) and the test circuit (2, 5, 6) independently of a supply voltage of the whole circuit (8) such that the inputs of the whole circuit do not have to be connected for testing the embedded circuit while only the inputs and outputs that are absolutely indispensable for testing the embedded circuit need to be connected to a test system.

Abstract: The apparatus includes a first variable delay circuit that delays a data signal from a device under test (DUT) to output a delay data signal; a second variable delay circuit that delays a clock signal to output a first delay clock signal; a first FF that acquires the delay data signal based on a reference clock; a second FF that acquires the first delay clock signal based on the clock; a first delay adjusting section that adjusts a delay amount of at least one of the first and second variable delay circuits so that the first and second FFs acquire the delay data signal and the first delay clock signal when the signals are changed; a third variable delay circuit that delays the clock signal to output a second delay clock signal; a second delay adjusting section that adjusts a delay amount of the third variable delay circuit based on the acquired first delay clock signal of which a phase is adjusted by the first delay adjusting section when the second delay clock is changed, in order to adjust a phase differenc

Abstract: According to one embodiment a computer system is disclosed. The computer system includes memory. The memory includes two or more rows, where each row has a plurality of memory devices. The computer system also includes a chipset. The chipset includes a detection/correction circuit to detect single and double symbol errors and correct single symbol errors for each memory row, and markers to maintain a log of errors within each memory row.

Abstract: An operation method of a MRAM of the present invention stores in memory arrays, error correction codes, each of which comprises of symbols, each of which comprises bits, and to which an error correction is possible in units of symbols. In the operation method, the symbols are read by using the reference cells different from each other. Moreover, when a correctable error is detected in a read data of the error correction code from data cells corresponding to an input address, (A) a data in the data cell corresponding to an error bit is corrected, for a first error symbol as an error pattern of one bit, and (B) a data in the reference cell that is used to read a second error symbol is corrected for a second error symbol as en error pattern of the bits.

Abstract: A semiconductor memory device includes: a parity generating circuit for generating parity data corresponding to input data; a normal data latching section for latching the input data or data read out from the normal memory cell array; an input selection circuit for selectively outputting the input data or the parity data; a parity data latching section for latching and outputting the output from the input selection circuit or data read out from the parity memory cell array; and an error correction circuit for performing an error detection on the data latched by the normal data latching section by using the data latched by the parity data latching section, and performing an error correction if an error is detected, to output the obtained result. The parity data latching section outputs the data latched by itself externally of the semiconductor memory device.

Abstract: A semiconductor memory device includes a memory cell array from which all bits of a data signal having a first number of the bits composed of a main data signal and an error detection/correction code data signal are simultaneously read, a sense amplifier for amplifying the read data signal, a selection unit for selecting a data signal having a second number of bits forming a part of the data signal amplified by the sense amplifier, and an error detection/correction unit for performing error detection and correction based on at least a part of the selected data signal having the second number of bits, wherein the selection by the selection unit is performed based on a row address.

Abstract: A computer configured to operate in diagnostic mode during which the operating system is suspended. During the diagnostic mode, tests can be performed on the computer system, including hardware, and the tests do not disrupt the operating system and are not disrupted by the operating system. When diagnostic mode is triggered, execution of the operating system is suspended. When the diagnostic tests are completed, the operating system may resume operation and test data may be made available within the operating system environment. Upon resuming, the state of the computer prior to entering diagnostic mode may be restored, preventing any changes made during diagnostic mode from interfering with operation of the operating system or application components.

Abstract: Test functions are expanded by adopting a test part, and an increase in circuit scale is reduced by adding the test part. A semiconductor integrated circuit comprises a memory that includes plural memory banks and is accessed by specifying a bank address, an X address, and a Y address, and a self-test part that tests the memory in response to commands. The self-test part has an address counter covering plural addressing modes that are different in how to update X addresses, Y addresses, and bank addresses. A variety of addressing modes provided for testing contribute to the expansion of BIST-based test functions. Since the self-test part has plural test sequencers corresponding to plural test modes, the area of the semiconductor integrated circuit can be easily reduced in comparison with program-controlled general-purpose sequencers requiring memory for storing programs.

Abstract: An Error Correcting Code (ECC) control circuit in a memory controller includes an ECC controller configured to receive data from a memory device in response to a request from a host device. The ECC controller transmits the data to a direct memory access (DMA) buffer for transfer to the host device, and to an ECC block for error detection and correction of the data. The ECC controller is configured to interrupt transmission of the data to the DMA buffer and transmit error-corrected data output from the ECC block to the DMA buffer responsive to detection of an error in the data by the ECC block. Related systems and methods are also discussed.

Abstract: A built-in redundancy analyzer and a redundancy analysis method thereof for a chip having a plurality of repairable memories are provided. The method includes the following steps. First, the identification code of a repairable memory containing a fault (“fault memory” for short) is identified and a parameter is provided according to the identification code. The parameter includes the length of row address, the length of column address, the length of word, the number of redundancy rows, and the number of redundancy columns of the fault memory. Since the parameter of every individual repairable memory is different, the fault location is converted into a general format according to the parameter for easier processing. A redundancy analysis is then performed according to the parameter and the converted fault location, and the analysis result is converted from the general format to the format of the fault memory and output to the fault memory.