Abstract: An IC includes an IEEE 1149.1 standard test access port (TAP) interface and an additional Off-Chip TAP interface. The Off-Chip TAP interface connects to the TAP of another IC. The Off Chip TAP interface can be selected by a TAP Linking Module on the IC.

Abstract: A device for using a programmable component carrying out at least one logical function in a radiative environment includes: a mechanism for error detection in a data-storing working memory space actually serving to carry out each logical function of the device through use of data stored in at least one reference memory space storing a data copy implemented by at least one logical function; a mechanism blocking at least one output of at least one logical function of the component for which an error in the data implemented by the logical function is detected by the mechanism for detection; and a mechanism correcting each error detected in the working space.

Abstract: A method for performing robust scan synthesis for soft-error protection on a design for generating a robust scan design in a system. The system is modeled selectively at a register-transfer level (RTL) or a gate level; the design includes at least a sequential element or a scan cell for mapping to a robust scan cell of a select robust scan cell type. The method comprises performing a scan replacement and a scan stitching on the design database based on a given control information file for synthesizing the robust scan cell on the design database; and generating the synthesized robust scan design at a pre-determined RTL or a pre-determined gate level.

Abstract: An apparatus and method for soft-error resilience or correction with the ability to perform a manufacturing test operation, a slow-speed snapshot operation, a slow-speed signature analysis operation, an at-speed signature analysis operation, a defect tolerance operation, or any combination of the above operations. In one embodiment, an apparatus includes a system circuit, a shadow circuit, and an output joining circuit for soft-error resilience. The output joining circuit coupled to the output terminals of the system circuit and the shadow circuit includes at least an S-element for defect tolerance. In another embodiment, an apparatus includes a system circuit, a shadow circuit, a debug circuit, and an output joining circuit for soft-error correction. The output joining circuit coupled to the output terminals of the system circuit, the shadow circuit, and the debug circuit includes at least a V-element for defect tolerance.

Abstract: A method for automatically generating test patterns using a close-to-minimum number of configurations for a Field Programmable Gate Array (FPGA) to reduce test data volume and test application time. The FPGA can be a standalone programmable device or a circuit embedded in an Application Specific Integrated Circuit (ASIC).

Abstract: It is desired to suppress an increase of the TAT or a repetition of processing in inserting a test circuit on designing. A test point insertion method includes: extracting a plurality of logic cones from a net list; generating an order for the plurality of logic cones based on a connection relation of logic cells in each of the plurality of logic cones; and setting a test point in each of the plurality of logic cones in turn in accordance with the order.

Abstract: A test architecture accesses IP core test wrappers within an IC using a Link Instruction Register (LIR). An IEEE P1500 standard is in development for providing test access to these individual cores via a test structure called a wrapper. The wrapper resides at the boundary of the core and provides a way to test the core and the interconnections between cores. The test architecture enables each of the plural wrappers in the IC, including wrappers in cores embedded within other cores, with separate enable signals.

Abstract: An integrated circuit includes a flip-flop circuit having a master latch unit and a slave latch unit. The master latch unit includes a data latch that may receive a data value on a data input, and a scan latch that may receive a scan data value on a scan data input. The data latch may latch and output the data value on an output line in response to a transition of a first clock signal, while the scan latch may latch and output the scan data value on the output line in response to a transition of a second clock signal. The slave latch unit may latch and output either the data value or the scan data value. The flip-flop circuit also includes a clock select circuit that may selectively provide either the first clock signal or the second clock signal dependent upon a scan enable signal.

Abstract: Scan-enabled method and system for testing a system-on-chip (SoC). The method includes electronically determining a slack in a signal at each port of a core of the SoC. The SoC includes multiple cores. Each core includes input ports and output ports. The method also includes selecting flip-flops for each port if the slack does not exceed a slack threshold. Further, the method includes integrating a wrapper cell to each port for which the slack exceeds the slack threshold. Moreover, the method includes coupling integrated wrapper cells and selected flip-flops corresponding to the input ports to form at least one input scan chain for the core, and corresponding to the output ports to form at least one output scan chain for the core. The method also includes testing the SoC using the at least one input scan chain and the at least one output scan chain of each core.

Abstract: An integrated circuit carries an intellectual property core. The intellectual property core includes a test access port 39 with test data input leads 15, test data output leads 13, control leads 17 and an external register present, ERP lead 37. A scan register 25 encompasses the intellectual property core and ERP lead 37 carries a signal indicating the presence of the scan register.

Abstract: The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. The use of the TMS and/or TCK terminal as serial I/O channels, as described, does not effect the standardized operation of the JTAG Tap, since the TMS and/or TCK I/O operations occur while the Tap is placed in a non-active steady state.

Abstract: An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG interface and is thus more applicable than conventional JTAG interfaces on an integrated circuit where the availability of pins is limited. The interface may be used for a variety of serial communication operations such as, but not limited to, serial communication related integrated circuit test, emulation, debug, and/or trace operations.

Abstract: A testable circuit includes a first function logic, an input output cell including an input/output unit and a first control multiplexer; and a first testing block is provided, wherein the input/output unit has at least a connection terminal. The first control multiplexer has an output port coupled to the connection terminal, a first input port coupled to the first functional logic, and a second input port. The first testing block is coupled between the first functional logic and the second input port, wherein when the testable circuit is under a testing mode, the first control multiplexer couples the second input port to the output port; and when the testable circuit is under a normal mode, the first control multiplexer couples the first input port to the output port.

Abstract: The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced pin JTAG devices (506), or a mixture of both full pin and reduced pin JTAG devices. The access is accomplished using a single interface (502) between the substrate (408) and a JTAG controller (404). The access interface may be a wired interface or a wireless interface and may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.

Abstract: A storage circuit, an integrated circuit and a scanning method are provided. The storage circuit includes a first storage element, and a second storage element connected to an output of the first storage element. The storage circuit includes a first setting circuit that is configured to set data of a first logic value to the first storage element when a clear signal is applied, and a second setting circuit that is configured to set data of a second logic value to the second storage element and transmit the second logic value data to a different storage circuit when a second clock signal is in an off state and the clear signal is applied.

Abstract: A method and system to facilitate a scalable scan system in the design of a system-on-chip. In one embodiment of the invention, the system-on-chip includes a controller and one or more clock gating units. The clock gating unit is added to each unique clock domain of each function or logic block in the system-on-chip. By having a controller that connects to each clock gating unit and the scan input and output signals in each logic block of the SOC, this allows a scalable scan system in the design of the SOC and allows frequent block level design changes in the SOC without extensive changes to the scan logic in one embodiment of the invention. In addition, the scalable scan system also allows at-speed scan write-through testing of a memory array that can improves the scan test coverage of the system-on-chip.

Abstract: A high integration integrated circuit may comprise a plurality of processing cores, a graphics processing unit, and an uncore area coupled to an interface structure such as a ring structure. A generic debug external connection (GDXC) logic may be provisioned proximate to the end point of the ring structure. The GDXC logic may receive internal signals occurring in the uncore area, within the ring structure and on the interfaces provisioned between the plurality of cores and the ring structure. The GDXC logic may comprise a qualifier to selectively control the entry of the packets comprising information of the internal signals into the queue. The GDXC logic may then transfer the packets stored in the queues to a port provisioned on the surface of the integrated circuit packaging to provide an external interface to the analysis tools.

Abstract: Memory compiler engineers often focus on the efficient implementation of the largest possible memory configurations for each memory type. The overhead of test and control circuitry within memory implementations is usually amortized across a large number of storage bits. Unfortunately, test structures generally do not scale down with decreasing memory sizes, creating a large area penalty for a design with numerous small memories. One solution is a scannable register file (SRF) architecture using scannable latch bit-cells laid out using a standard cell layout/power template. All sub-cells can be placed in standard cell rows and utilize standard cell power straps. Non-SRF standard cells can be abutted on all sides, placement keep-out regions are not needed. Metal utilization is usually limited to first three metallization layers. The bit-cell is much larger than standard compiled memory bit cells, but has no overhead beyond address decode, word-line drivers, and read-write data latches.

Abstract: In a method of performing a test on a logic circuit in accordance with an exemplary aspect of the present invention, the test is performed by supplying a clock signal from a clock supply circuit to a plurality of clock domains operating by a clock signal of a same frequency. The method includes calculating a number of test patterns of each of the plurality of internal clock domains; classifying the plurality of clock domains into a plurality of groups based on the calculated number of test patterns; and assigning a clock supply circuit independently to each of the groups into which the clock domains are classified.

Abstract: Flip-flops 201 to 206 constitute a scan path shift register. During shift mode operation, a clock signal CLK is supplied to clock terminals of the flip-flops 201, 203, and 205, a signal obtained by having an inverted clock control circuit 303 reverse the phase of the clock signal CLK is supplied to clock terminals of the flip-flops 202 and 206, and a normal/inverted clock control circuit 404 supplies a signal having the same phase as the clock signal CLK to a clock terminal of the flip-flop 204 having no sufficient setup time.

Abstract: The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access technique. The serial access technique may be controlled by a device tester or by a JTAG controller. Further the disclosure provides an approach to access the TCA of a device when the device exists in a daisy-chain arrangement with other devices, such as in a customer's system. Additional embodiments are also provided and described in the disclosure.

Abstract: A fault location estimation device includes: a faulty scan chain identification unit that identifies a faulty scan chain and its fault type based on result of operation verification test; a faulty scan FF narrowing unit that compares test result of the faulty scan chain with simulation result for determining a faulty scan FF range beginning at the location of a scan FF where both results differ; and a path trace narrowing unit that references logic circuit configuration information, signal line expected value, a failure-observed scan FF, and test result of a defective circuit to extract a scan FF on the faulty scan chain, which may be reached from a failure-observed scan FF observed on a normal scan chain by tracing back a failure propagation path while performing implication procedure for an input side, and thereby further narrows the faulty scan FF range determined by the faulty scan FF narrowing unit.

Abstract: The disclosure describes novel methods and apparatuses for controlling a device's TCA circuit when the device exists in a JTAG daisy-chain arrangement with other devices. The methods and apparatuses allow the TCA test pattern set used during device manufacturing to be reused when the device is placed in a JTAG daisy-chain arrangement with other devices, such as in a customers system using the device. Additional embodiments are also provided and described in the disclosure.

Abstract: In a scanning-capable latch circuit, main latch circuits respectively corresponding to data inputs D1 to D4 are connected in series and, except the last-stage main latch circuit, the scanning output from each main latch circuit becomes the scanning input for the subsequent main latch circuit; while the scanning output from the last-stage main latch circuit becomes the scanning input for a slave latch circuit. Hence, in the scanning-capable latch circuit used in an information processing apparatus, the circuit area can be reduced and scanning can be performed with a small-scale circuit.

Abstract: A method comprises performing at least one zero-bit scan across an interface. The at least one zero-bit scan defines a command window. Further, the method implements one of a selectable plurality of control levels in the command window based on the number of the at least one zero-bit scans.

Abstract: Methods and devices for using high-speed serial links for scan testing are disclosed. The methods can work with any scheme of scan data compression or with uncompressed scan testing. The protocol and hardware to support high speed data transfer reside on both the tester and the device under test. Control data may be transferred along with scan data or be partially generated on chip. Clock signals for testing may be generated on chip as well. In various implementations, the SerDes (Serializer/Deserializer) may be shared with other applications. The Aurora Protocol may be used to transport industry standard protocols. To compensate for effects of asynchronous operation of a conventional high-speed serial link, buffers may be used. The high-speed serial interface may use a data conversion block to drive test cores.

Abstract: A device test architecture and interface is provided to enable efficient testing embedded cores within devices. The test architecture interfaces to standard IEEE 1500 core test wrappers and provides high test data bandwidth to the wrappers from an external tester. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester. The test architecture includes a selector circuit for selecting a core for testing. Additional features and embodiments of the device test architectures are also disclosed.

Abstract: Disclosed below are representative embodiments of methods, apparatus, and systems used to generate test patterns for testing integrated circuits. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) environment). Certain embodiments of the disclosed technology can reduce the switching rates, and thus the power dissipation, in scan chains with no hardware modification. Other embodiments use specialized decompression hardware and compression techniques to achieve low power testing.

Abstract: A semiconductor integrated circuit includes: a plurality of scan flip-flops configured to form a scan chain in a scan test; and a plurality of clock gating circuits connected between a clock input and corresponding portions of the plurality of scan flip-flops, respectively. The plurality of clock gating circuits are connected in serial to form a chain and gating setting data is inputted in serial through the chain connection. Each of the plurality of clock gating circuits controls a connection between the clock input and a corresponding portion of the plurality of scan flip-flops based on the gating setting data.

Abstract: Methods, apparatus, and systems for performing fault diagnosis are disclosed herein. In one exemplary embodiment, a failure log is received comprising entries indicative of compressed test responses to chain patterns and compressed test responses to scan patterns. A faulty scan chain in the circuit-under-test is identified based at least in part on one or more of the entries indicative of the compressed test responses to chain patterns. One or more faulty scan cell candidates in the faulty scan chain are identified based at least in part on one or more of the entries indicative of the compressed test responses to scan patterns. The one or more identified scan cell candidates can be reported. Computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods are also provided. Likewise, computer-readable media storing lists of fault candidates identified by any of the disclosed methods are also provided.

Abstract: A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20).

Abstract: A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20).

Abstract: A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20).

Abstract: Techniques are provided for X-masking using at least some masking information provided by on-chip logic, in lieu of masking information provided from off of the integrated circuit being tested. The masking information is provided by a masking information source on the integrated circuit being tested, such as, for example, a read-only memory (ROM) circuit, that feeds the masking information to the X-masking logic. With these implementations of the invention, it is possible to perform X-masking independent from any external data, thus enabling X-masking for a logic built-in self-test without requiring an external testing device.

Abstract: Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuity, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals.

Abstract: A debugging module for connecting an IC to a JTAG debugger device includes a JTAG interface, an earphone circuit, a USB interface, a switching unit, and a reset circuit. The earphone circuit is electrically connected to the JTAG interface via the switching unit. The USB interface and the reset circuit are electrically connected to the JTAG interface. When a JTAG debugger device is connected to the earphone circuit and the USB interface, the earphone circuit and the USB interface, respectively, can establish a connection between the JTAG debugger device and the JTAG interface.

Abstract: An apparatus having a plurality of first circuits, second circuits, third circuits and fourth circuits is disclosed. The first circuits may be configured to generate a plurality of first signals in response to (i) a priority signal and (ii) a request signal. The second circuits may be configured to generate a plurality of second signals in response to the first signals. The third circuits may be configured to generate a plurality of enable signals in response to the second signals. The fourth circuits may be configured to generate collectively an output signal in response to (i) the enable signals and (ii) the request signal. A combination of the first circuits, the second circuits, the third circuits and the fourth circuits generally establishes a programmable priority encoder. The second signals may be generated independent of the enable signals.

Abstract: A virtual In-Circuit Emulation (ICE) capability is provided herein for supporting testing of Joint Test Action Group (JTAG) hardware. A Virtual ICE Driver is configured for enabling any debug software to interface with target hardware in a flexible and scalable manner. The Virtual ICE Driver is configured such that the test instruction set used with the Virtual ICE Driver is not required to compute vectors, as the JTAG operations are expressed as local native instructions on scan segments, thereby enabling ICE resources to be accessed directly. The Virtual ICE Driver is configured such that ICE may be combined with instrument-based JTAG approaches (e.g., the IEEE P1687 standard and other suitable approaches).

Abstract: A semiconductor integrated circuit includes: a plurality of flip-flops connected to a scan chain set as a test path of an integrated circuit; and a data-collection section inputting setting values of the plurality of flip-flops connected to the scan chain through the scan chain or an independent connection path, wherein the data-collection section inputs the setting values of the flip-flops at the time the power has been turned on to the plurality of flip-flops, and performs generation processing of random numbers, or random-number generation data, or fixed data on the basis of the input values.

Abstract: The present invention relates to a parametric scan register and a method of testing a digital circuit with the aid of such a register. The parametric scan register includes a memory cell having at least one data input, able to receive a test datum, and transferring to its output a representative signal indicative of the test datum by use of a synchronization signal. It furthermore includes a parametric test block one input of which is linked to the output (s) of the cell, the output signal of the cell being transferred at the output of the parametric test block through an internal module, this internal module operating according to modes able to modify the output signal of the cell. Embodiments of the invention apply to the testing of integrated circuits with high integration density, for example in the field of nanotechnologies.

Abstract: An apparatus configured for a phase locked loop (PLL) built in self test (BIST) jitter measurement is described. The apparatus includes a phase detector. The phase detector produces a digital signal that describes a comparison between a reference signal and a feedback signal. The apparatus also includes a BIST controller. The BIST controller accumulates the digital signal with successive digital signals. The apparatus also includes a communication pin. The communication pin sends the accumulated signal to automatic test equipment (ATE) that determines whether the PLL is operating correctly based on the accumulated signal.

Abstract: Scan chain diagnosis techniques are disclosed. Faulty scan chains are modeled and scan patterns are masked to filter out loading-caused failures. By simulating the masked scan patterns, failing probabilities are determined for cells on a faulty scan chain. One or more defective cells are identified based upon the failing probability information. A noise filtering system such as the one based upon adaptive feedback may be adopted for the identification process.

Abstract: This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations. In a fifth aspect of the present disclosure, an interface select circuit, FIGS. 41-49, provides for selectively using either the 5 signal interface of FIG. 41 or the 3 signal interface of FIG. 8.

Abstract: A test pattern generating device generates a test pattern with respect to a semiconductor circuit having first and second common circuits and a non-common circuit other than the first and second common circuits, wherein each of the first and second common circuits has a scan chain for checking an operation of the circuit by applying a test pattern from the outside of the circuit. A set of scan chains and a set of assumed faults are created for each of the first and second common circuits. Any of the first and second common circuits is determined as the common circuit of a first test target. After the determined common circuit of the first test target is subjected to ATPG and detection of circuit fault, a test pattern generated in successful ATPG about the common circuit of the first test target is diverted to the common circuit determined as the second test target, and ATPG and detection of a circuit fault of the non-common circuit part is carried out.

Abstract: A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein.

Abstract: A semiconductor integrated circuit includes a scan chain configured to serve as a connection path used for testing the semiconductor integrated circuit and connect a plurality of flip-flops and an interleave circuit provided at an output portion of the scan chain. The interleave circuit includes a plurality of branches including different numbers of stages of storage elements, a selector configured to select one of the plurality of branches serving as an input/output branch that performs input of data from the scan chain and output of data from the interleave circuit, and a selector controller configured to execute a process of switching among the plurality of branches to select the input/output branch at every predetermined timing.

Abstract: Fault tolerant programming of a programmable device advantageously occurs via a host controller that first queries the programmable device through a Boundary scan interface to identify the device. Thereafter, host controller selects a program file in accordance with the device identity for subsequent downloading via the Boundary scan interface to program the device. Thereafter, the host controller verifies that successful programming has occurred.

Abstract: A method for allowing measurement corrections on a chip-by-chip basis. Error correction values are generated responsive to the input value to a circuit of the calibrated integrated circuit chip and to a measured value from the circuit of the calibrated integrated circuit chip. The error correction values are stored within an error correction table within a nonvolatile memory of the integrated circuit chip.

Abstract: An emulator for emulating operations of data processing circuitry normally connected to and cooperable with a peripheral circuit includes serial scanning circuitry connectable to the peripheral circuit. The serial scanning circuitry provides to and receives from the peripheral circuit signals which would normally be provided and received by the data processing circuitry. The serial scanning circuitry is connectable to an emulation controller for transferring serial data between the emulation controller and the emulator. The serial scanning circuitry includes a first state machine having plural states controlling the transfer of serial data. The emulator further includes control circuitry connected to the serial scanning circuitry and connectable to the emulation controller.

Abstract: Today many instances of IEEE 1149.1 Tap domains are included in integrated circuits (ICs). While all TAP domains may be serially connected on a scan path that is accessible external to the IC, it is generally preferred to have selectivity on which Tap domain or Tap domains are accessed. Therefore Tap domain selection circuitry may be included in ICs and placed in the scan path along with the Tap domains. Ideally, the Tap domain selection circuitry should only be present in the scan path when it is necessary to modify which Tap domains are selected in the scan path. The present disclosure describes a novel method and apparatus which allows the Tap domain selection circuitry to be removed from the scan path after it has been used to select Tap domains and to be replaced back into the scan path when it is necessary to select different Tap domains.