Abstract: A client computing system (CCS) receives a download including (i) an image representative of at least one circuit in a vehicle, the at least one circuit including a first circuit configured for carrying a first signal within the vehicle, and (ii) symbol data associated with at least one symbol, the at least one symbol including a first symbol. After receiving the download, the CCS displays the image and the at least one symbol. The CCS then receives a first input corresponding to selection of the first symbol. The CCS then responsively receives, from the vehicle, data representing value(s) of the first signal. The CCS then determines a first display-location at which to display the data representing the value(s) of the first signal. While the image and the at least one symbol are displayed, the CCS then displays, at the first display-location, the data representing the value(s) of the first signal.

Abstract: The present disclosure relates to a method for use with an electronic design. Embodiments may include simulating a processor model and a hardware model, each executed with a corresponding simulator thread on a simulation platform. Embodiments may also include simulating embedded software using the processor model. The simulating may include updating a given register of the processor model that stores a value that changes in response to switching between processes within the embedded software. Embodiments may further include setting a simulator breakpoint and a software breakpoint and enabling debugging of both non-virtual and virtual addresses at the software breakpoint without leaving the software breakpoint.

Abstract: A controller for a plurality of interconnected devices in a system is shown. The controller includes a processing circuit configured to detect that a first device of the plurality of interconnected devices is unavailable and identify a second device of the plurality of interconnected devices schematically dependent upon the first device by conducting a graph theory analysis on schematic relationships indicating connections among the plurality of interconnected devices. The processing circuit is further configured to, in response to identifying the second device schematically dependent upon the first device, generate a reduced subset of the plurality of interconnected devices that excludes the second device. The processing circuit is further configured to operate the reduced subset to transfer one or more resources among the reduced subset via the connections.

Abstract: Vacant areas of a layer of an integrated circuit design are filled with shapes connected to the appropriate nets.

Abstract: A method is provided and includes several operations: arranging multiple channels extending in a first direction; arranging, in accordance with multiple weights of multiple macros, a first portion of the macro closer to a centroid of a core region of an integrated circuit than a second portion of the macros; and arranging the macros on opposite sides of the channels. The macros have multiple pins coupled to the channels interposed between the macros.

Abstract: A method includes reserving a routing track within a cell, wherein the cell comprises signal lines for connection to elements within the cell, the cell further comprises a plurality of routing tracks, the reserved routing track is one of the plurality of routing tracks, and the reserved routing track is free of the signal lines. The method further includes determining whether any power rails overlap with any of the plurality of routing tracks other than the reserved routing track. The method further includes adjusting a position of the cell in response to a determination that at least one power rail overlaps with at least one routing track of the plurality of routing tracks other than the reserved routing track.

Abstract: The present disclosure relates to a chip design layout process. More specifically, the present disclosure is directed to an incremental routing-based pin assignment technique. One example method generally includes: performing routing and pin assignment for a chip design layout, one or more objects of the chip design layout being associated with a routing engine and a pin assignment engine stored in memory; detecting a change associated with the one or more objects of the chip design layout; updating, via one or more processors, at least one of the routing engine or the pin assignment engine stored in the memory in response to the detected change and based on the association between the one or more objects and the routing engine or pin assignment engine; and performing another routing and pin assignment based on the updated at least one of the routing engine or the pin assignment engine.

Abstract: Implementations of a method of designing a module semiconductor product may include receiving a selection of a module type, one or more die, a placement of one or more wires, clips, or pins; and generating, using a processor, a module configuration file. The method may include generating a module bonding diagram using a build diagram system module; selecting one or more SPICE models corresponding with the die; and generating a product SPICE model and a three dimensional model for the module semiconductor product. The method may include generating one or more datasheet characteristics of the module semiconductor product with at least the product SPICE model and the product simulation module, generating a product datasheet for the module semiconductor product using the datasheet formation module, and providing access to at least the module bonding diagram, the product SPICE model, the three dimensional model, and the product datasheet to the user.

Abstract: Various embodiments provide for a cross-section parameterized cell, which can enable a user to visualize and interactively define or modify one or more wire instances and related elements/structure of a circuit design from an elevation view (or a side view).

Abstract: In a radio frequency power amplifier with harmonic suppression, one end of an input matching circuit is connected with a radio frequency input end; and another end is connected with a base of a power amplification transistor having a collector connected with a power supply voltage through a first matching branch, and an emitter connected with a first connection point on a package substrate. The collector of the power amplification transistor is connected with a radio frequency output end through a second matching branch that is connected with the package substrate. A harmonic control circuit has a first end connected with the collector of the power amplification transistor, and a second end connected with a second connection point on the package substrate.

Abstract: An automated analog layout tool creates not just one, but many electrically correct layouts from an input schematic. Designers can explore multiple layout options in a fraction of the time needed to produce just a single layout by hand. Because the tool produces layout results so quickly, parasitics are available for simulation early in the design process, further speeding the entire design cycle. The tool considers place and route concurrently.

Abstract: A method to store the shapes of an electrical circuit design in a hierarchical set of arrays that inverts the layout size order by area includes defining a plurality of storage levels. Each level corresponds to a two-dimensional projection of the three-dimensional volume of the circuit layout. Accordingly, each level subsumes the entire physical space of the circuit layout. Each level may include a respective grid of slots. The slots may be rectangular. Each slot within any single level may be the same size and dimensions as every other slot in this level. Shapes are added to this storage technique based upon size, not based upon physical layer. Each slot can contain shapes from any physical layer as long as that shape fits entirely within the slot.

Abstract: The present disclosure relates to a system and method for use in an electronic circuit design. Embodiments may include receiving, using a processor, one or more DFM rules files from at least one PCB fabricator and importing the one or more DFM rules files to a DFM rule aggregator database. Embodiments may also include grouping one or more rules associated with the one or more DFM rules files using an automated or manual operation. Embodiments may further include performing automatic or manual rule aggregation on the grouped rules based upon, at least in part, rules aggregation information including a DFM template file.

Abstract: A method and an apparatus for verifying an operation state of an application are provided. The method can include setting target verification operation information according to an operation verification item of an application to be verified; setting a verification process instruction for the target verification operation information; encapsulating the verification operation information and the verification process instruction as fault injection data, and sending the fault injection data to a data input port of the application to be verified; matching the process feedback information with the verification process instruction in response to receiving the process feedback information corresponding to the fault injection data, and determining executed target verification operation information.

Abstract: A system and a method are disclosed for placing hardware components on a printed circuit board (“PCB”) in a way that enables all hardware components on the PCB to be passively cooled without using active cooling systems. Components are selected to be placed onto the PCB and heat metrics for each component is obtained (e.g., from a server). The components are ranked based on the amount of heat that each component generates. A corresponding position for each of the hardware components is determined based on the ranking of the components and the orientation of the PCB. The placement is based on the concept that air having higher temperature rises while air having cooler temperature falls. A representation of the PCB according to corresponding positions of the hardware components may be generated for display.

Abstract: In certain embodiments, a selection of a first point and a second point within an infrastructure may be obtained via a user interface. A plurality of pathways, including a plurality of cable trays, between the first point and the second point may be determined. A first set of cable trays, having weights that do not exceed weight thresholds, may be identified. Images of the first set of cable trays may be obtained from a plurality of image sensors within the infrastructure. Fullness levels of the first set of cable trays may be determined based on the images. A second set of cable trays, having fullness levels that do not exceed fullness thresholds, may be identified from the first set of cable trays. One or more recommended pathways between the first point and the second point may be determined based on the identified second set of cable trays.

Abstract: Methods and apparatus for performing profile-guided optimization of integrated circuit hardware are provided. Circuit design tools may receive a source code and compile the source code to generate a hardware description. The hardware description may include profiling blocks configured to measure useful information required for optimization. The hardware description may then be simulated to gather profiling data. The circuit design tools may then analyze the gathered profiling data to identify additional opportunities for hardware optimization. The source code may then be modified based on the analysis of the profiling data to produce a smaller and faster hardware that is better suited to the application.

Abstract: In an approach for balancing mainframe and distributed workloads, a processor receives a request to allocate an application workload to a mainframe platform and a distributed computing platform. The application workload includes a plurality of work units. A processor collects performance and cost data associated with the application workload, the mainframe platform, and the distributed computing platform. A processor determines the mainframe platform and the distributed computing platform for the plurality of work units of the application workload, based on the analysis of the performance and cost data. A processor allocates the plurality of work units of the application workload to run on the mainframe platform and the distributed computing platform respectively to balance performance and cost in real time.

Abstract: A method of fabricating a circuit element, such as a quantum computing circuit element, including obtaining a lithography mask write file that includes mask information characterizing one or more mask features, obtaining a uniformity function that is configured to modify the mask information to compensate for a non-uniform deposition process, applying the uniformity function to the lithography mask write to obtain a modified lithography mask write file, and performing lithography as directed by the modified lithography mask write file.

Abstract: A graph neural network to predict net parasitics and device parameters by transforming circuit schematics into heterogeneous graphs and performing predictions on the graphs. The system may achieve an improved prediction rate and reduce simulation errors.

Abstract: A recording medium includes simulation data input into a computing device executing a simulation of a semiconductor device, wherein the simulation data includes part shape information describing a shape of a part included in a simulation target circuit, model information describing operation and connection information of the simulation target circuit, and symbol information of the part included in the simulation target circuit, and the computing device causes the part shape information, the model information, and the symbol information to correspond to each other to execute the simulation of the semiconductor device.

Abstract: A system for element tracking in documents includes a memory device, a database, and a processor. The memory device is configured to store a mapping in a memory between a linked element within a document and a database object. The database is configured to store the database object. The processor is configured to in response to an update of the database object: a) cause storage in the database of an update event associated with the linked element; and b) provide an update indication that the update associated with the linked element has occurred.

Abstract: Various embodiments provide for a pre-validation of various aspects of an application deployment before any resources are provisioned in a user account. Pre-validation can perform checks on aspects such as connectivity and credential-based access for instances to be provisioned in a user account. These checks can be performed through an application wizard or deployment service that can collect information though a single console, and can ensure that these checks succeed before the requested instances are provisioned in the user account.

Abstract: Approaches for visualizing data buses in a circuit design include determining ones of the data buses that satisfy selection criteria. For each element connected to a data bus of the ones of the data buses, a method and system determine whether the element is of interest or the element is not of interest. A graphical representation of the ones of the data buses and each element of interest is generated, and data buses of the circuit design determined to not satisfy the selection criteria and elements not of interest are excluded from the graphical representation. The graphical representation is displayed on a display device.

Abstract: Data transformation in a distributed system of applications and data repositories is described. The subsystems for the overall framework are distributed, thereby allowing for customization to require only isolated changes to one or more subsystems. In one embodiment, a source code repository is used to receive and store source code. A build subsystem can retrieve source code from the source code repository and build it, using one or more criteria. By building the source code, the build subsystem can generate an artifact, which is executable code, such as a JAR or SQL file. Likewise, by building the source code, the build subsystem can generate one or more job specifications for executing the executable code. In one embodiment, the artifact and job specification may be used to launch an application server in a cluster. The application server can then receive data transformation instructions and execute the data transformation instructions.

Abstract: A device is disclosed. The cell block includes a pin disposed at a Nth metal layer in a cell layout. The first metal interconnect is disposed at a (N+1)th metal layer above the Nth metal layer and stacked over the pin, and electrically coupled to the pin. The second interconnects are disposed at a (N+2)th metal layer and stacked over the first metal interconnect, and parallel to each other. The second metal interconnects are electrically coupled to the first metal interconnect, and forming an equivalent tapping point of the pin of the cell block. The equivalent tapping point and the pin are vertically overlapped with each other, and fabrication of the device is initiated after a DRC or a SEM simulation test is passed. A first via connects the first metal interconnect to the pin, and the at least one first metal interconnect is perpendicular to the pin.

Abstract: A digital engineering (DE) platform configured to support space system development and acquisition. The DE platform includes a modular reference architecture models module configured to capture key modular system elements of interest using model-based system engineering (MBSE) and digital object oriented requirements system (DOORS) tools. The DE platform also includes a connectivity matrix module defining interface or specifications between one or more modular system elements. The DE platform is also configured to digitize the interface using a behavior model. The behavior model capturing required activity and/or sequence for a particular use case.

Abstract: A drawing management apparatus of the present disclosure includes a processor that generates a virtual plant based on various types of drawings of a plant, updates the virtual plant, when a change is made to a drawing among the various types of drawings, based on the change, and notifies a predetermined recipient, via a communication interface, of information related to a change made to the virtual plant by updating.

Abstract: Embodiments include herein are directed towards a method for use in an electronic design environment is provided. Embodiments may include receiving, at a client electronic device, an image of an electronic circuit and storing an electronic circuit design file. Embodiments may further include identifying the electronic circuit design file based upon, at least in part, the image of the electronic circuit. Embodiments may also include displaying a graphical representation of the electronic circuit at a display screen associated with the client electronic device.

Abstract: The present disclosure relates to a method for use with an electronic design. Embodiments may include receiving, at a graphical user interface, an indication of a desired wire creation associated with an electronic design and determining a plurality of routing solutions, based upon, at least in part, the desired wire creation. Embodiments may further include simultaneously displaying the plurality of routing solutions at the graphical user interface, wherein a predicted preferred routing solution is graphically emphasized. Embodiments may also include receiving a selection from a user, at the graphical user interface, of one of the plurality of routing solutions and storing the selection for subsequent use.

Abstract: A computing system can implement a circuit verification tool to perform scaled sampling of parameter values in a foundry model describing parameter variations for a manufacturing process capable of fabricating an integrated circuit described in a circuit design. The computing system can simulate the circuit design with the scaled samples of the parameter values, and build a geometric model to describe a response of the circuit design to the scaled samples of the parameter values during the simulation. The geometric model can include one or more failure regions corresponding to geometric descriptions for failures of the circuit design to meet a specification during simulation with the scaled samples of the parameter values. The computing system can estimate a yield for an output of the integrated circuit described by the circuit design based on the failure regions in the geometric model.

Abstract: A system and a method are disclosed for placing hardware components on a printed circuit board (“PCB”) in a way that enables all hardware components on the PCB to be passively cooled without using active cooling systems. Components are selected to be placed onto the PCB and heat metrics for each component is obtained (e.g., from a server). The components are ranked based on the amount of heat that each component generates. A corresponding position for each of the hardware components is determined based on the ranking of the components and the orientation of the PCB. The placement is based on the concept that air having higher temperature rises while air having cooler temperature falls. A representation of the PCB according to corresponding positions of the hardware components may be generated for display.

Abstract: An automated analog layout tool creates not just one, but many electrically correct layouts from an input schematic. Designers can explore multiple layout options in a fraction of the time needed to produce just a single layout by hand. Because the tool produces layout results so quickly, parasitics are available for simulation early in the design process, further speeding the entire design cycle. The tool considers place and route concurrently.

Abstract: The present disclosure relates to a method for use with an electronic design. Embodiments may include displaying, at a graphical user interface, at least a portion of the electronic design and receiving a selection of a subcircuit at a first position of the graphical user interface. In response to a user input, embodiments may include transitioning the subcircuit from the first position to a second position of the graphical user interface and determining one or more direct and indirect connections resulting from a potential placement at the second position. Embodiments may include determining an influence metric by applying an optimized connectivity rules definition upon the potential placement at the second position and the one or more direct and indirect connections. Embodiments may also include displaying feedback at the graphical user interface based upon, at least in part, the influence metric.

Abstract: In some embodiments, a logging framework reserves space in an in-memory storage for a log entry upon receiving a first function call from an application being executed. Upon receiving a second function call from the application being executed, the framework writes the log entry in the space in the in-memory storage. Upon receiving a third function call from the application being executed, the framework selects a configuration for the application and comparing an indicator that is generated based on the executing of the application to the configuration. When the indicator meets a condition of the configuration, the framework copies the log entry from the space in the in-memory storage to a persistent storage space. The log entry is deleted from the space in the in-memory storage at a time after performing the comparing.

Abstract: Seamless transitions between routing modes are provided via providing a cursor in association with a design layout; in response to receiving a follow-the-cursor (FTC) command at a first position in the design layout, create a first trace in the design layout where the cursor is displayed; in response to receiving a start command for point-to-point routing at a second position in the design layout: complete the first trace at the second position; and provide an indicator at the second position; in response to receiving an end command for point-to-point routing at a third position in the design layout: create a second trace in the design layout where the cursor is displayed; and create a third trace in the design layout, wherein the third trace is routed from the first trace to the second trace.

Abstract: A medical imaging system (100) includes a user interface (110) and a magnifying view engine (130). The user interface displays a view of a medical image on a display device (114) and to provide a moveable indicator (116) identifying a moveable point positioned in the displayed medical image. The magnifying view engine (130) generates a localized enlargement of a region of interest within the displayed medical image in response to selection of an existing end point or an existing contour in the displayed medical image according to a first input by one or more input devices and indicated by a current position of the moveable indicator.

Abstract: An apparatus including semiconductor dies in a stack. The semiconductor dies are configured to power-up in a staggered manner. Methods for powering up an electronic device include detecting a power-up event with the semiconductor dies in the stack, and responsive to the power-up event, powering up a first semiconductor die in the stack at a first time, and powering up a second semiconductor die in the stack at a second time that is different from the first time.

Abstract: A method includes reserving a routing track within a cell, the cell includes signal lines for connection to elements within the cell, the cell further includes a plurality of routing tracks, the reserved routing track is one of the plurality of routing tracks, and the reserved routing track is free of the signal lines. The method includes placing the cell in a chip-level layout, wherein the chip-level layout includes a plurality of power rails. The method includes determining whether any of the plurality of power rails overlaps with any of the plurality of routing tracks other than the reserved routing track. The method includes adjusting a position of the cell in the chip-level layout in response to a determination that at least one power rail of the plurality of power rails overlaps with at least one routing track of the plurality of routing tracks other than the reserved routing track.

Abstract: A layout modification method for fabricating a semiconductor device is provided. Uniformity of critical dimensions of a first portion and a second portion in a patterned layer are calculated by using a layout for an exposure manufacturing process to produce the semiconductor device. A width of the second portion equals a penumbra size of the exposure manufacturing process, and the penumbra size is utilized to indicate which area of the patterned layer is affected by light leakage exposure from another exposure manufacturing process. Non-uniformity between the first and second portions of the patterned layer is compensated according to the uniformity of critical dimensions to generate a modified layout. The patterned layer includes a plurality of absorbers, and a first width of the absorbers is the first portion is less than a second width of the absorbers in the second portion the second portion.

Abstract: Various embodiments provide for modeling a power and ground (PG) mesh for a circuit design placement process. For some embodiments, a reference PG mesh can be used to generate a PG mesh model for a circuit design. A PG mesh model can be generated for a circuit design by calculating how much routing resource is occupied by the reference PG mesh of the circuit design, and the resulting PG mesh model can be applied to the circuit design by removing a similar amount of routing resource from the circuit design during a placement circuit design flow. Additionally (or alternatively), a PG mesh model can be generated to comprise a set of metal obstructions that correspond to each macro of the circuit design, and the PG mesh model can be applied to the circuit design by adding the metal obstructions to one or more metal layers of the circuit design.

Abstract: An integrated circuit that includes a first row having a first height, with a first cell in the first row that has the first height. The integrated circuit further includes a second row having a second height, where the first height is not an integer multiple of the second height. A second cell is in the second row that has the second height.

Abstract: Electronic system level (ESL) design and verification of the present disclosure is utilized to provide an electronic simulation of various loads on one or more batteries of an electronic device resulting from the electronic device performing one or more functional behaviors. Before this electronic simulation occurs, the electronic device is modeled using the high-level software language or the high-level software format. For example, a battery discharge model, a regulator efficiency model, a power delivery network (PDN) model, or a component power model are used to model behaviors of the one or more batteries, regulator circuitry, power delivery network (PDN) circuitry, and other electronic circuits, respectively, of the electronic device.

Abstract: Systems and techniques are described for transparent hierarchical routing in an integrated circuit (IC) design. A logical netlist can be analyzed in the IC design to identify endpoints of a physical route that crosses at least one physical hierarchy boundary. Next, a set of routing shapes can be created to electrically connect the endpoints of the physical route. The set of routing shapes can then be transformed to corresponding routing shapes in each physical hierarchy context along the physical route.

Abstract: Embodiments include herein are directed towards a method for electronic circuit design. Embodiments may include displaying, at a graphical user interface, an electronic circuit design topology environment and allowing a user to select, create, or modify an entirely single pin topology, an entirely multi-pin topology, or a combination of a single pin topology and a multi-pin topology for one or more portions of the electronic circuit design topology environment. Embodiments may also include receiving a selection of a designated portion of the electronic circuit design topology environment and generating, at the graphical user interface, a first, pin-adjustable symbol in accordance with the selected topology at the designated portion.

Abstract: The present embodiments relate generally to integrated circuit design, and more particularly to techniques for providing enhanced visual information about a shape of interest in a hierarchical design. For example, embodiments relate to automatically and dynamically creating or adjust a highlight set in a graphical user interface for providing hierarchical information about shapes in a hierarchical design in a more productive manner, and possibly concurrently with other textual information about shapes that is being displayed. In these and other embodiments, these automatic and/or dynamic highlight sets can be based on the relationship between a current cursor position and shapes of a hierarchical design that is currently being edited using a GUI of a layout editor tool that is adapted with the functionality of the present disclosure.

Abstract: A layout modification method is performed by at least one processor. The layout modification method includes: analyzing, by the at least one processor, allocation of a plurality of specific layout segments of a circuit cell layout to determine a first specific layout segment and a second specific layout segment from the plurality of specific layout segments; determining, by the at least one processor, if the first specific layout segment and the second specific layout segment are coupled to a first signal level; and merging, by the at least one processor, the first specific layout segment and the second specific layout segment into a first merged layout segment when the first specific layout segment and the second specific layout segment are coupled to the first signal level.

Abstract: Disclosed are methods and systems for characterizing and analyzing an electronic system design including a parallel interface. Some methods and systems identify an electronic design including a parallel interface, determine a single circuit representation including the parallel interface from the electronic design, and analyze the parallel interface to determine waveform responses of the parallel interface by using channel analysis techniques without performing circuit simulations.

Abstract: Electronic design automation to simulate the behavior of structures and materials at multiple simulation scales with different simulators.

Abstract: The present disclosure relates to a system and method for determining an effective electrical resistance in an electronic circuit design. Embodiments may include receiving, at one or more computing devices, an electronic circuit design and identifying one or more features associated with the electronic circuit design. Embodiments may also include performing a resistance only extraction of a circuit net associated with the electronic circuit design and identifying at least two node locations from the electronic circuit as one or more port nodes. Embodiments may further include reducing the resistance only extraction to an equivalent circuit including only the port nodes and attaching a high-resistance ground voltage source to at least one of the port nodes of the reduced equivalent circuit. Embodiments may also include generating a conductance matrix, based upon, at least in part, the reduced equivalent circuit.