Abstract: A system generates a mask for a circuit design while enforcing symmetry and consistency across random areas of the mask. The system builds a mask solutions database mapping circuit patterns to mask patterns. The system uses the mask solutions database to replace circuit patterns of the circuit design with mask patterns. The system identifies properties in circuit patterns of the circuit design and enforces the same property in the corresponding mask patterns. Examples of properties enforced include symmetry within circuit patterns and similarity across circuit patterns. The system combines mask patterns in different regions of the circuit and resolves conflicts that occur when there are multiple masks within a region.

Abstract: An operating method of an extreme ultraviolet (EUV) lithography device includes defining a target image to render an illumination system, assigning priorities to respective positions of facets of a pupil facet mirror corresponding to the target image, assigning a mirror according to the assigned priorities using linear programming, generating the illumination system by selecting one of the facets of the pupil facet mirror based on a symmetry criterion, and converting mirror assignment information and source map information corresponding to the selected facet into a form recognizable by an EUV scanner.

Abstract: Embodiments disclosed herein include a semiconductor manufacturing tool with a hybrid model and methods of using the hybrid model for processing wafers and/or developing process recipes. In an embodiment, a method for developing a semiconductor manufacturing process recipe comprises selecting one or more device outcomes, and querying a hybrid model to obtain a process recipe recommendation suitable for obtaining the device outcomes. In an embodiment, the hybrid process model comprises a statistical model and a physical model. In an embodiment, the method may further comprise executing a design of experiment (DoE) on a set of wafers to validate the process recipe recommended by the hybrid process model.

Abstract: A method including obtaining (i) measurements of a parameter of the feature, (ii) data related to a process variable of a patterning process, (iii) a functional behavior of the parameter defined as a function of the process variable based on the measurements of the parameter and the data related to the process variable, (iv) measurements of a failure rate of the feature, and (v) a probability density function of the process variable for a setting of the process variable, converting the probability density function of the process variable to a probability density function of the parameter based on a conversion function, where the conversion function is determined based on the function of the process variable, and determining a parameter limit of the parameter based on the probability density function of the parameter and the measurements of the failure rate.

Abstract: A method for generating a mask pattern to be employed in a patterning process. The method including obtaining (i) a first feature patch including a first polygon portion of an initial mask pattern, and (ii) a second feature patch including a second polygon portion of the initial mask pattern; adjusting the second polygon portion at a patch boundary between the first feature patch and the second feature patch such that a difference between the first polygon portion and the second polygon portion at the patch boundary is reduced; and combining the first polygon portion and the adjusted second polygon portion at the patch boundary to form the mask pattern.

Abstract: Various integrated circuit (IC) design methods are disclosed herein. An exemplary method includes receiving an IC design layout having an IC feature to be formed on a wafer using a lithography process and inserting a spacing in the IC feature, thereby generating a modified IC design layout that divides the IC feature into a first main feature and a second main feature separated by the spacing. The spacing has a sub-resolution dimension, such that the IC feature does not include the spacing when formed on the wafer by the lithography process using the modified IC design layout. A mask can be fabricated based on the modified IC design layout, wherein the mask includes the first main feature and the second main feature separated by the spacing. A lithography process can be performed using the mask to form the IC feature (without the spacing) on a wafer.

Abstract: A method for determining a probabilistic model configured to predict a characteristic (e.g., defects, CD, etc.) of a pattern of a substrate subjected to a patterning process. The method includes obtaining a spatial map of a distribution of a residue corresponding to a characteristic of the pattern on the substrate, determining a zone of the spatial map based on a variation of the distribution of the residue within the spatial map, and determining the probabilistic model based on the zone and the distribution of the residue values or the values of the characteristic of the pattern on the substrate within the zone.

Abstract: A method to determine a curvilinear pattern of a patterning device that includes obtaining (i) an initial image of the patterning device corresponding to a target pattern to be printed on a substrate subjected to a patterning process, and (ii) a process model configured to predict a pattern on the substrate from the initial image, generating, by a hardware computer system, an enhanced image from the initial image, generating, by the hardware computer system, a level set image using the enhanced image, and iteratively determining, by the hardware computer system, a curvilinear pattern for the patterning device based on the level set image, the process model, and a cost function, where the cost function (e.g., EPE) determines a difference between a predicted pattern and the target pattern, where the difference is iteratively reduced.

Abstract: Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that that includes a periphery IP tile. The periphery IP tile may be disaggregated from the programmable fabric die and may be communicatively coupled to the first die via a modular interface.

Abstract: A method of generating an integrated circuit includes providing a placing layout of the integrated circuit; generating a routed layout of the integrated circuit, the routed layout includes a layout region with a systematic design rule check (DRC) violation; generating an adjusted routing layout of the integrated circuit by adjusting the layout region with the systematic DRC violation according to a target placement recipe in a plurality of placement recipes; extracting features of the placing layout to obtain an extracted data; extracting features of the layout region with the systematic DRC violation to obtain an extracted routing data; performing a training process upon the extracted data and the extracted routing data to generate a plurality of aggregated-cluster models; and selecting a target aggregated-cluster model from the plurality of aggregated-cluster models by comparing the extracted data to the plurality of aggregated-cluster models.

Abstract: This application discloses a computing system to identify structures of an integrated circuit capable of being fabricated utilizing a lithographic mask described by mask layout data and to generate process windows for the identified structures based, at least in part, on the mask layout data and a failure definition for the identified structures. The computing system utilizes process windows for the identified structures to determine failure rates for the identified structures based on a distribution of the manufacturing parameters. The computing system determines frequency of occurrences for the identified structures from the mask layout data and generates a die yield metric for the integrated circuit by aggregating the failure rates for the identified structures based on the frequency of occurrences for the identified structures in the integrated circuit. These increases in yield of the integrated circuit allow manufacturers to produce more units per fixed processing cost of the wafer.

Abstract: A method of generating a plurality of photomasks includes generating a circuit graph. The circuit graph comprises a plurality of vertices and a plurality of edges. Each of the plurality of vertices is representative of one of a plurality of conductive lines. The plurality of edges are representative of a spacing between the conductive lines less than an acceptable minimum distance. Kn+1 graph comprising a first set of vertices selected from the plurality of vertices connected in series by a first set of edges selected from the plurality of edges and having at least one non-series edge connection between a first vertex and a second vertex selected from the first set of vertices is reduced by merging a third vertex into a fourth vertex selected from the first set of the plurality of vertices. An n-pattern conflict check is performed and the photomasks generated based on the result.

Abstract: An integrated circuit (IC) device includes a substrate having opposite first and second sides, an active region over the first side of the substrate, a first conductive pattern over the active region, and a second conductive pattern under the second side of the substrate. The active region includes a first portion and a second portion. The first conductive pattern is electrically coupled to the first portion and the second portion of the active region. The second conductive pattern is electrically coupled to the first portion and the second portion of the active region.

Abstract: A method for forming a photomask is provided. The method includes: receiving an initial layout, the initial layout comprising a first pattern and a second pattern; decomposing the initial layout into a first layout including the first pattern and a second layout including the second pattern; inserting a third pattern into the first layout; overlapping the first layout including the first pattern and the third pattern to the second layout including the second pattern; increasing a width of the third pattern in the first layout overlapping the second pattern in the second layout to form a fourth pattern in the first layout; and outputting the first layout comprising the first pattern, the third pattern and the fourth pattern into a first photomask.

Abstract: A lithography method using a multiscale simulation includes estimating a shape of a virtual resist pattern for a selected resist based on a multiscale simulation; forming a test resist pattern by performing an exposure process on a layer formed of the selected resist; determining whether an error range between the test resist pattern and the virtual resist pattern is in an allowable range; and forming a resist pattern on a patterning object using the selected resist when the error range is in the allowable range. The multiscale simulation may use molecular scale simulation, quantum scale simulation, and a continuum scale simulation, and may model a unit lattice cell of the resist by mixing polymer chains, a photo-acid generator (PAG), and a quencher.

Abstract: Embodiments of the present application relate to the technical field of semiconductor, and disclose a design method of a wafer layout and an exposure system of a lithography machine. The design method of a wafer layout includes: providing a yield distribution map of a wafer under an initial wafer layout; determining a yield edge position of the wafer according to the yield distribution map; and calculating a new wafer layout according to a die size and the yield edge position.

Abstract: A learning device for performing a machine learning based on a learning model using data input to an input layer, includes: a calculation part configured to calculate a predetermined number of features, in which simulation data as a result of simulating semiconductor manufacturing processes by setting environmental information inside a process vessel in which the semiconductor manufacturing processes are performed and using a predetermined component provided in the process vessel as a variable, and XY coordinates parallel to a plane of a wafer are associated with each other; and an input part configured to input the calculated predetermined number of features to the input layer.

Abstract: A system and a method of optimizing an optical proximity correction (OPC) model for a mask pattern of a photo mask is disclosed. A machine learning (ML) based model builder includes an OPC model, measurement data and a random term generator. Random terms are generated in a M-dimensional space by the random term generator. The ML based model builder classifies the random terms to clusters by applying a classifying rule. A representative subset of the random terms is determined among the classified clusters, and the representative subset is added to the OPC model.

Abstract: A method of designing and manufacturing a replica composite object based on an original object. The method identifies the structure and physical properties of an original object. Base materials, bodies, and structural templates, each of which includes associated physical properties, are utilized to generate a 3-dimensional model. The 3-dimensional model is discretized and tested to determine if the selected combination of base materials and bodies have physical properties that substantially equal the physical properties of the original object. If the physical properties do not equate, the 3-dimensional model is optimized by adjusting the combination of base materials, bodies, and structural templates. When the difference between the measured physical properties of the 3-dimensional model and the identified physical properties of the original object is less than a tolerance value, the method instructs an additive manufacturing system to generate a replica composite object based on the original object.

Abstract: A semiconductor device including: first, second and third active regions a first gate structure over the first active region and a first part of the second active region; a second gate structure over the third active region and a second part of the second active region; a first cell region including the first gate structure, the first active region and the first part of the second active region; a second cell region including the second gate structure, the third active region and the second part of the second active region; a first border region representing an overlap of the first and second cell regions which is substantially aligned with an approximate midline of the second active region; the second gate structure overlapping the first border region; and there being a first gap which is between the first gate structure and the first border region.

Abstract: The independent claims of this patent signify a concise description of embodiments. An automatic process for determining and/or predicting the original root-cause(s) of a violation is proposed using two major enhancements on top of the current VC-Static solution. First, an information repository is created by mining various Static checker components' analysis information, and second, an analysis framework is created which systematically prunes the above-mentioned information repository to find the actual root cause(s) of the violation. This Abstract is not intended to limit the scope of the claims.

Abstract: There are provided a lithography method capable of selecting best resist and a semiconductor device manufacturing method and exposure equipment based on the lithography method. The lithography method includes estimating a shape of a virtual resist pattern based on a multi-scale simulation for resist, forming a test resist pattern by performing exposure on selected resist based on the simulation result, comparing the test resist pattern with the virtual resist pattern, and forming a resist pattern on an object to be patterned by using the resist when an error between the test resist pattern and the virtual resist pattern is in an allowable range.

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated circuit. The method includes forming a hard mask over a dielectric layer of a substrate. A blocking layer is formed on the hard mask and spacers are formed over the blocking layer. The spacers laterally straddle opposing edges of the blocking layer. The hard mask is etched according to the spacers and the blocking layer. The dielectric layer is etched according to the hard mask.

Abstract: Embodiments of techniques for inverse design of physical devices are described herein, in the context of generating designs for photonic integrated circuits (including a multi-channel photonic demultiplexer). In some embodiments, an initial design of the physical device is received, and a plurality of sets of operating conditions for fabrication of the physical device are determined. In some embodiments, the performance of the physical device as fabricated under the sets of operating conditions is simulated, and a total performance loss value is backpropagated to determine a gradient to be used to update the initial design. In some embodiments, instead of simulating fabrication of the physical device under the sets of operating conditions, a robustness loss is determined and combined with the performance loss to determine the gradient.

Abstract: A method of determining candidate patterns from a set of patterns of a patterning process. The method includes obtaining (i) a set of patterns of a patterning process, (ii) a search pattern having a first feature and a second feature, and (iii) a search condition comprising a relative position between the first feature and the second feature of the search pattern; and determining a set of candidate patterns from the set of patterns that satisfies the search condition associated with the first feature and the second feature of the search pattern.

Abstract: The present invention relates generally to the technical field of integrated circuit mask design, and more particularly to a method, an apparatus and an electronic device for Hessian-Free photolithography mask optimization. The method includes steps: S1, inputting a design layout of a mask to be optimized; S2, positioning error monitoring points on the design layout of the mask to be optimized; S3, obtaining an optimization variable x of the mask to be optimized; S4, forming an objective function cost on the optimization variable x; and S5, optimizing the objective junction cost by a Hessian-Free-based conjugate gradient method, to obtain an optimization result of the mask to be optimized. Optimizing the objective function cost based on a Hessian-Free conjugate gradient method to obtain an optimization result of the mask to be optimized, which can greatly reduce the computation resources in the optimization process, make the optimization process simpler, feasible, and improve the optimization efficiency.

Abstract: A method for representing a layout of an integrated circuit (IC) includes, in part, determining multiple regions of the IC layout based on one or more parameters, determining multiple areas associated with the multiple regions where each area has a characteristic of a region of the multiple regions, assigning a first set of values to locations of the IC layout outside the multiple areas, assigning a second set of values to locations of the IC layout within the multiple areas, and, in response to a determination that a location of the IC layout is in two or more overlapping areas of the multiple areas, determining a value to assign to the location in accordance with the values of the two or more overlapping areas. The method further includes generating data representative of the IC layout design in accordance with the first and second set of values, and the assigned value.

Abstract: A semiconductor circuit design method, system and computer program product for placing a unit pin on a boundary of a unit of a semiconductor circuit to be designed may be provided. Pin position data is received, wherein the pin position data comprises a chip pin position of a chip pin within the chip area and outside of the unit of a semiconductor circuit, to which the unit pin is to be electrically connected. The coordinates of a center point of the unit are determined, as well as a line crossing the center point and the chip pin position. The unit pin is placed on an intersection of the boundary of the unit and the line crossing the center point.

Abstract: A method for inspection of a patterning device. The method includes obtaining (i) patterning device apparatus data of a patterning device making process, (ii) a patterning device substrate map based on the patterning device apparatus data, and (iii) predicted process window limiting pattern locations corresponding to the patterning device based on the patterning device substrate map, and based on the process window limiting pattern locations, guiding a patterning device inspection apparatus to the process window limiting pattern locations for defect inspection.

Abstract: The present invention relates generally to the technical field of integrated circuit mask design, and more particularly to a method, an apparatus and an electronic device for photolithographic mask optimization of joint optimization of pattern and image. The method includes steps: inputting the main pattern; dividing edges of each main pattern into short edges, and regarding the short edges as a first variable for optimizing the main pattern; generating same or similar assistant feature sample points around same or similar main patterns, and regarding the assistant feature sample points as a second variable for optimizing the main pattern; and forming an objective function with the first variable and the second variable as optimization variables. The rules for generating assistant feature sample points around each main pattern are consistent, which are not limited to specific locations of the main pattern and ensures the consistency of final results for optimizing each main pattern.

Abstract: A method of determining a sampling control scheme and/or a processing control scheme for substrates processed by a device. The method uses a fingerprint model and an evolution model to generate the control scheme. The fingerprint model is based on fingerprint data for a processing parameter of at least one substrate processed by a device, and the evolution model represents variation of the fingerprint data over time. The fingerprint model and the evolution model are analyzed and a sampling and/or processing control scheme is generated using the analysis. The sampling control scheme provides an indication for where and when to take measurements on substrates processed by the device. The processing control scheme provides an indication for how to control the processing of the substrate. Also, there is provided a method of determining which of multiple devices contributed to a fingerprint of a processing parameter.

Abstract: Systems and methods for calculating a printed area metric indicative of stochastic variations of the lithographic process are disclosed. Lithography is a process that uses light to transfer a geometric pattern from a photomask, based on a layout design, to a resist on a substrate. The lithographic process is subject to random stochastic phenomena, with the resulting stochastic randomness potentially becoming a major challenge. To characterize the stochastic phenomena, a printed area metric may be generated analytically (rather than via simulations) and comprise one or more defined moments for a printed area distribution associated with the printed area that are indicative of one or more aspects associated with printing. For example, the printed area metric may be indicative of the likelihood of printing within the printed area or the variance of printing within the printed area due to stochastic randomness in one or both of exposure or resist process.

Abstract: A method to determine a curvilinear pattern of a patterning device that includes obtaining (i) an initial image of the patterning device corresponding to a target pattern to be printed on a substrate subjected to a patterning process, and (ii) a process model configured to predict a pattern on the substrate from the initial image, generating, by a hardware computer system, an enhanced image from the initial image, generating, by the hardware computer system, a level set image using the enhanced image, and iteratively determining, by the hardware computer system, a curvilinear pattern for the patterning device based on the level set image, the process model, and a cost function, where the cost function (e.g., EPE) determines a difference between a predicted pattern and the target pattern, where the difference is iteratively reduced.

Abstract: A method to improve a lithographic process of imaging a portion of a design layout onto a substrate using a lithographic apparatus, the method including computing a multi-variable cost function. The multi-variable cost function represents an interlayer characteristic, the interlayer characteristic being a function of a plurality of design variables that represent one or more characteristics of the lithographic process. The method further includes reconfiguring one or more of the characteristics of the lithographic process by adjusting one or more of the design variables and computing the multi-variable cost function with the adjusted one or more design variables, until a certain termination condition is satisfied.

Abstract: The independent claims of this patent signify a concise description of embodiments. Roughly described, a design team prioritizes polygons of a circuit design layout. This information is then encoded into a layout database that is passed to the manufacturing team for correction further processing toward tape-out. The priorities may be used by an engineer to disposition errors found in the layout. For example, a failure may be waived. In another embodiment, the priorities are used during hotspot fixing, a process where failed features are corrected. In hotspot fixing, the priority can be used to make correction tradeoffs in favor of the highest priority features. Priorities are set during the correction to favor fidelity of the higher priority features over the lower priority features. Each embodiment reduces cost, and in some cases, improve final device performance. This Abstract is not intended to limit the scope of the claims.

Abstract: Methods and devices that identify a silkscreen data file associated with a physical printed circuit board and use an image of the physical printed circuit board to display a virtual silkscreen over the image of the physical printed circuit board.

Abstract: Aspects described herein relate to obtaining a mask pattern using a cost function gradient (CFG) generated from a Jacobian matrix generated from a perturbation look-up table (PLT). In an example method, a PLT is populated (108). Each table entry of the PLT is based on a respective perturbed intensity signal. The respective perturbed intensity signal is based on a simulated signal received at an image surface using a mask pattern having a perturbed element of the mask pattern. The mask pattern is for a design of an integrated circuit. A matrix is populated (110) using the PLT and a target intensity signal. The target intensity signal is based on a signal received at the image surface to form target features at the image surface. A CFG is defined (112) based on the matrix. An analysis is performed (114) on the mask pattern based on the CFG.

Abstract: Provided is a method for fabricating a semiconductor device including generating an ideal image using measured contour data and fitted conventional model terms. The method further includes using the fitted conventional model terms and a mask layout to provide a conventional model aerial image. In some embodiments, the method further includes generating a plurality of mask raster images using the mask layout, where the plurality of mask raster images is generated for each measurement site of the measured contour data. In various embodiments, the method also include training a neural network to mimic the ideal image, where the generated ideal image provides a target output of the neural network, and where the conventional model aerial image and the plurality of mask raster images provide inputs to the neural network.

Abstract: Several methods of reducing one or more pattern displacement errors, contrast loss, best focus shift, tilt of a Bossung curve of a portion of a design layout used in a patterning process for imaging that portion onto a substrate using a lithographic apparatus. The methods include determining or adjusting one or more characteristics of one or more assist features using the one or more rules based on one or more parameters selected from a group consisting of: one or more characteristics of one or more design features in the portion, one or more characteristics of the patterning process, one or more characteristics of the lithographic apparatus, and/or a combination selected from the foregoing.

Abstract: Various embodiments provide for routing a network of a circuit design based on at least one of a placement blockage or a layer-assigned network of a circuit design. For instance, some embodiments route a network of a circuit design (e.g., clock net, date net) by generating a congestion map based on modeling layer-assigned networks, considering (e.g., accounting for) routing congestion based on a placement blockage of the circuit design, or some combination of both.

Abstract: A device includes a plurality of active areas, a plurality of gates, and a plurality of conductors. The active areas are elongated in a first direction. The gates are elongated in a second direction. The conductors are disposed between the active areas and elongated in the second direction. Each one of the conductors has an overlap with at least one corresponding gate of the gates to form at least one capacitor.

Abstract: Examples of synchronized parallel tile computation techniques for large area lithography simulation are disclosed herein for solving tile boundary issues. An exemplary method for integrated circuit (IC) fabrication comprises receiving an IC design layout, partitioning the IC design layout into a plurality of tiles, performing a simulated imaging process on the plurality of tiles, generating a modified IC design layout by combining final synchronized image values from the plurality of tiles, and providing the modified IC design layout for fabricating a mask. Performing the simulated imaging process comprises executing a plurality of imaging steps on each of the plurality of tiles. Executing each of the plurality of imaging steps comprises synchronizing image values from the plurality of tiles via data exchange between neighboring tiles.

Abstract: Examples described herein provide a method for designing an integrated circuit (IC) for meeting different sets of criteria. In an example, different sets of criteria are identified for an IC design. The IC design is designed to meet the different sets of criteria based on expected manufacturing variation. The IC design is caused to be manufactured as IC products. At least some of the IC products are caused to be tested. The IC products are characterized as meeting respective ones of the different sets of criteria based on testing the at least some of the IC products.

Abstract: Verifying a product is disclosed. An image of a self-assembly (SA) pattern on a substrate from a scanner is received. The SA pattern has been initially created using a block copolymer (BCP) which has been annealed on the substrate. Data from the SA pattern is stored in a computer system. The SA pattern data is associated with the product. The SA pattern is an information carrying security mark having a set of features with corresponding locations within the information carrying security mark which uniquely identify the product.

Abstract: A method and system is provided that simplifies the key management by allowing personalization data protected for one chip model to be used to provision device with another chip model with different global hardware root keys. The solution minimizes the changes needed to be performed on the device during provisioning and remains secure.

Abstract: A method of determining dimensional changes of features in a mask involves calculating a spacing to be used between adjacent unit cells, correcting a unit cell surrounded by replicas of the same unit cell at the calculated spacing for optical proximity effects, arraying the proximity corrected unit cell at the calculated spacing, and dividing the array of unit cells into templates. Each template frames a portion of the array of unit cells, and locations of the unit cells in each framed template are shifted relative to locations of the unit cells in other framed templates. Critical dimensions for features in the unit cell are determined within each template, and the critical dimensions determined across the template are used to obtain shift variances of each feature. A dimensional change is determined for a feature based on the shift variance for that feature.

Abstract: A method including: obtaining a resist process dose sensitivity value for a patterning process; applying the resist process dose sensitivity value to a stochastic model providing values of a stochastic variable as a function of resist process dose sensitivity to obtain a value of the stochastic variable; and designing or modifying a parameter of the patterning process based on the stochastic variable value.

Abstract: A focus metrology target includes one or more periodic arrays of features. A measurement of focus performance of a lithographic apparatus is based at least in part on diffraction signals obtained from the focus metrology target. Each periodic array of features includes a repeating arrangement of first zones interleaved with second zones, a feature density being different in the first zones and the second zones. Each first zone includes a repeating arrangement of first features. A minimum dimension of each first feature is close to but not less than a resolution limit of the printing by the lithographic apparatus, so as to comply with a design rule in a given a process environment. A region of high feature density may further include a repeating arrangement of larger features.

Abstract: A method including computing a multi-variable cost function, the multi-variable cost function representing a metric characterizing a degree of matching between a result when measuring a metrology target structure using a substrate measurement recipe and a behavior of a pattern of a functional device, the metric being a function of a plurality of design variables including a parameter of the metrology target structure, and adjusting the design variables and computing the cost function with the adjusted design variables, until a certain termination condition is satisfied.

Abstract: A method includes obtaining a sub-layout having an area that is a performance limiting spot, adjusting colors of patterns in the area, and determining whether the area is still a performance limiting spot. Another method includes decomposing patterns in a design layout into multiple sub-layouts; determining for at least one area in one of the sub-layouts, the likelihood of that a figure of merit is beyond its allowed range; and if the likelihood is above a threshold, that one sub-layout has a performance limiting spot. Another method includes: obtaining a design layout having a first group of patterns and a second group of patterns, wherein colors of the first group of patterns are not allowed to change and colors of the second group of patterns are allowed to change; and co-optimizing at least the first group of patterns, the second group of patterns and an illumination of a lithographic apparatus.