Abstract: An illumination source is optimized by changing the intensity and shape of the illumination source to form an image in the image plane that maximizes the minimum ILS at user selected fragmentation points while forcing the intensity at the fragmentation points to be within a small intensity range. An optimum mask may be determined by changing the magnitude and phase of the diffraction orders to form an image in the image plane that maximizes the minimum ILS at user selected fragmentation points while forcing the intensity at the fragmentation points to be within a small intensity range. Primitive rectangles having a size set to a minimum feature size of a mask maker are assigned to the located minimum and maximum transmission areas ad centered at a desired location. The edges of the primitive rectangle are varied to match optimal diffraction orders O(m,n). The optimal CPL mask OCPL(x,y) is then formed.

Abstract: Methods and apparatuses for estimation of at least one parameter of interest of a feature fabricated on a substrate, the feature having a plurality of structure parameters, the structure parameters including the at least one parameter of interest and one or more nuisance parameters. A receiver receives radiation scattered from one or more measured features on the substrate. A pupil generator generates an unprocessed pupil representation of the received radiation. A matrix multiplier multiplies a transformation matrix with intensities of each of a plurality of pixels of the unprocessed pupil representation to determine a post-processed pupil representation in which effects of the one or more nuisance parameters are mitigated or removed. A parameter estimator estimates the at least one parameter of interest based on the post-processed pupil representation.

Abstract: A method of designing and manufacturing a replica composite object based on an original object. The method identifies the structure and physical properties of an original object. Base materials, bodies, and structural templates, each of which includes associated physical properties, are utilized to generate a 3-dimensional model. The 3-dimensional model is discretized and tested to determine if the selected combination of base materials and bodies have physical properties that substantially equal the physical properties of the original object. If the physical properties do not equate, the 3-dimensional model is optimized by adjusting the combination of base materials, bodies, and structural templates. When the difference between the measured physical properties of the 3-dimensional model and the identified physical properties of the original object is less than a tolerance value, the method instructs an additive manufacturing system to generate a replica composite object based on the original object.

Abstract: A method of manufacturing an integrated circuit (IC) including instances of standard cells includes arranging a first instance and arranging a second instance adjacent to the first instance. The second instance has a front-end layer pattern corresponding to a context group of the first instance. The context group includes information about front-end layer patterns of instances, the front-end layer patterns causing a same local layout effect (LLE) on the first instance and arranged adjacent to the first instance.

Abstract: Systems and methods for tuning photolithographic processes are described. A model of a target scanner is maintained defining sensitivity of the target scanner with reference to a set of tunable parameters. A differential model represents deviations of the target scanner from the reference. The target scanner may be tuned based on the settings of the reference scanner and the differential model. Performance of a family of related scanners may be characterized relative to the performance of a reference scanner. Differential models may include information such as parametric offsets and other differences that may be used to simulate the difference in imaging behavior.

Abstract: Verifying a semiconductor product is disclosed. An image of a self-assembly (SA) pattern on a substrate from a scanner is received. The SA pattern has been initially created using a block copolymer (BCP) which has been annealed on the substrate. Data from the SA pattern is stored in a computer system. The SA pattern data is associated with the semiconductor product. The SA pattern is an information carrying security mark having a set of features with corresponding locations within the information carrying security mark which uniquely identify the semiconductor product.

Abstract: A method for mask process correction or forming a pattern on a reticle using charged particle beam lithography is disclosed, where the reticle is to be used in an optical lithographic process to form a pattern on a wafer, where sensitivity of the wafer pattern is calculated with respect to changes in dimension of the reticle pattern, and where pattern exposure information is modified to increase edge slope of the reticle pattern where sensitivity of the wafer pattern is high. A method for fracturing or mask data preparation is also disclosed, where pattern exposure information is determined that can form a pattern on a reticle using charged particle beam lithography, where the reticle is to be used in an optical lithographic process to form a pattern on a wafer, and where sensitivity of the wafer pattern is calculated with respect to changes in dimension of the reticle pattern.

Abstract: A method includes receiving a first target pattern of an integrated circuit (IC) that includes two first target features and two second target features. The method further includes deriving a second target pattern based on the first target pattern and a directed self-assembly (DSA) process, wherein the first target pattern is to be produced by a process that includes performing the DSA process with a guide pattern derived from the second target pattern. The second target pattern includes a third feature and a fourth feature. The third feature is designed for producing the two first target features with the DSA process, and the fourth feature is designed for producing the two second target features with the DSA process. The method further includes inserting one or more sub-DSA-resolution assistant features (SDRAF) into the second target pattern, the one or more SDRAF connecting the third and fourth features.

Abstract: A technique and method for determining a process dose for a beam lithography process includes accessing a data set that enables associating (i) a plurality of measured dimensions of features exposed by beam lithography with (ii) a plurality of different exposure doses, wherein the features were exposed with the different exposure doses, and with (iii) at least one of a plurality of different densities of the exposed features and a plurality of different nominal dimensions of the exposed features. The method also includes providing a model that is parameterized in at least the following parameters (i) measured feature dimension; (ii) exposure dose; (iii) at least one of feature density and nominal feature dimension; (iv) process dose; and (v) at least one process bias. In a further step, the method includes fitting the model with the data set to determine the process dose and the process bias.

Abstract: A computer implemented method for decomposing a layout of a portion of an integrated circuit is presented. The layout includes a first multitude of polygons. The method includes constructing, using the computer, a first matrix representative of a first multitude of constraints. Each of the first multitude of constraints is between a different pair of the first multitude of polygons. The method includes solving, using the computer, the first matrix to thereby assign one of a multitude of masks to each different one of the first multitude of polygons, when the computer is invoked to decompose the layout.

Abstract: A computer-implemented method for quickly analyzing the effect of process, voltage, temperature, and other variations when the variation analysis or circuit structure can be hierarchically composed into nested loops. The method has two main steps: first, it hierarchically generates a set of points and inserts them into a flat list of tuples, where each tuple contains a point from each level in the looping hierarchy. Second, it efficiently identifies and simulates failing tuples with the assistance of modeling to order the tuples to simulate. By using the present method, a designer does not have to simulate the full ECD at each and every statistical process point or PVT corner, which can same considerable time or compute effort.

Abstract: Embodiments of the disclosure provide a method including: identifying a target feature in an integrated circuit (IC) layout not represented in a library, the library including a plurality of sub-resolution assist feature (SRAF) usefulness maps corresponding to a plurality of features and SRAFs in the IC layout; generating a usefulness map for the target feature with an artificial neural network (ANN), the generating being based on the target feature and the plurality of SRAF usefulness maps in the library; adding the target feature and the generated usefulness map to the library; selecting an SRAF insertion site for the target feature based on the generated usefulness map; and inserting an SRAF for the target feature into the IC layout at the selected SRAF insertion site.

Abstract: A method to easily determine parameters of a second process for manufacturing from parameters of a first process is provided. Metrics representative of differences between the first process and the second process are computed from a number of values of the parameters, which can be measured for the first process and the second process on a calibration layout, or which can be determined from pre-existing values for layouts or reference data for the first process and the second process by an interpolation/extrapolation procedure. A set of metrics are selected so that their combination gives a precise representation of the differences between the first process and the second process in all areas of a target design. Advantageously, the metrics are calculated as a product of convolution of the target design and a compound of a kernel function and a deformation function.

Abstract: The present invention provides a number of innovations in the area of computational process control (CPC). CPC offers unique diagnostic capability during chip manufacturing cycle by analyzing temporal drift of a lithography apparatus/ process, and provides a solution towards achieving performance stability of the lithography apparatus/process. Embodiments of the present invention enable optimized process windows and higher yields by keeping performance of a lithography apparatus and/or parameters of a lithography process substantially close to a pre-defined baseline condition. This is done by comparing the measured temporal drift to a baseline performance using a lithography process simulation model. Once in manufacturing, CPC optimizes a scanner for specific patterns or reticles by leveraging wafer metrology techniques and feedback loop, and monitors and controls, among other things, overlay and/or CD uniformity (CDU) performance over time to continuously maintain the system close to the baseline condition.

Abstract: Disclosed are an optical member, a display device including the optical member and a method of fabricating the optical member. The display device includes a light source; a wavelength conversion member into which light generated from the light source is incident; and a display panel into which light is incident from the wavelength conversion member. The wavelength conversion member includes a receiving part having a pipe shape; a matrix in the receiving part; and a plurality of wavelength conversion particles disposed in the matrix to convert a wavelength of the light generated from the light source.

Abstract: A semiconductor structure includes a substrate having a plurality of semiconductor devices disposed therein. A dielectric layer is disposed over the substrate. A plurality of substantially parallel metal lines are disposed in the dielectric layer. The metal lines include active lines for routing signals to and from the devices, and dummy lines which do not route signals to and from the devices. Signal cuts are disposed in the active lines. The signal cuts define tips of the active lines. Assist cuts are disposed exclusively in the dummy lines and do not define tips of the active lines. The assist cuts are located proximate the signal cuts such that a first density of assist cuts and signal cuts in an area surrounding the signal cuts is substantially greater than a second density of signal cuts alone in the same area.

Abstract: A method of generating a layout usable for fabricating an integrated circuit is disclosed. The method includes generating a block layout layer usable in conjunction with a first conductive layout layer. The first conductive layout layer includes a fuse layout pattern, and the block layout layer includes a block layout pattern overlapping a portion of a fuse line portion of the fuse layout pattern. A second conductive layout layer is generated to replace the first conductive layout layer. The generating the second conductive layout layer includes performing an optical proximity correction (OPC) process on the first conductive layout layer except the portion of the fuse line portion of the fuse layout pattern corresponding to the block layout pattern.

Abstract: A system, method, and computer program product for reducing the number of Monte Carlo simulation samples required to determine if a design meets design specifications. The worst sample for each specification acts as a design corner to substitute for a full design verification. Embodiments determine the maximum number of samples needed, perform an initial performance modeling using an initial set of samples, and estimate the failure probability of each of the remaining samples based on the performance model. Embodiments then simulate remaining samples with a computer-operated Monte Carlo circuit simulation tool in decreasing design specification model accuracy order, wherein the sample predicted most likely to fail each specification is simulated first. Re-use of simulation results progressively improves models. Probability based stop criteria end the simulation early when the worst samples have been confidently found. A potential ten-fold reduction in overall specification verification time may result.

Abstract: A system, method, and computer program product for efficiently finding the best Monte Carlo simulation samples for use as design corners for all design specifications to substitute for a full circuit design verification. Embodiments calculate a corner target value matching an input variation level by modeling the circuit performance with verified accuracy, estimate the corner based on a response surface model such that the corner has the highest probability density (or extrapolation from the worst sample if the model is inaccurate), and verify and/or adjust the corner by performing a small number of additional simulations. Embodiments also estimate the probability that a design already meets the design specifications at a specified variation level. Composite multimodal and non-Gaussian probability distribution functions enhance model accuracy. The extracted design corners may be of particular utility during circuit design iterations.

Abstract: The present invention provides an exposure apparatus including a projection optical system configured to project light from a reticle onto a substrate, a processor configured to estimate a variation in imaging characteristic of the projection optical system, based on a model determined in advance, and an adjusting device configured to adjust the imaging characteristic of the projection optical system based on the variation estimated by the processor, wherein the processor is configured, if an error of the imaging characteristic of the projection optical system adjusted by the adjusting device based on the variation which is estimated based on a first number of models, for estimating the variation, determined in advance without the reticle, does not fall within a tolerance, to generate a second number of models for estimating the variation, the second number being larger than the first number.

Abstract: A technique relates to a method of optimizing self-aligned double patterning. Predefined locations for required metal cuts are provided in order to form metal wires from metal fills that have been cut. Extended locations for extended metal cuts are provided in order to cut adjacent metal fills. The adjacent metal fills are the metal fills that are adjacent to the predefined locations for the required metal cuts, and the extended metal cuts extend beyond the required metal cuts. The required metal cuts into the metal fills are performed and the extended metal cuts into the adjacent metal fills are performed.

Abstract: A method includes receiving a layout of an integrated circuit that includes a plurality of layers, one of the layers is selected and one or more tile number values are provided. A die area of the integrated circuit is partitioned into a plurality of tiles on the basis of the tile number values. It is determined, on the basis of the layout, if a portion of the selected one of the layers in the tile has an available space for inclusion of a test cell or a dummy cell, and a label indicative of a result is assigned to the tile. It is determined, on the basis of the labels assigned, if one or more space availability criteria are fulfilled and, if fulfilled, the labels are used for placing at least one of one or more test cells and one or more dummy cells in the layout.

Abstract: A method of making a semiconductor device includes determining, by a processor, a first pattern density of a first region, determining a second pattern density of a second region, determining a pattern density gradient from the first region to the second region, determining whether the pattern density gradient exceeds a pattern density gradient threshold and performing a placement or a routing of the semiconductor device if the pattern density gradient is less than or equal to the pattern density gradient threshold.

Abstract: Provided herein is a method of improving a transference of a mask pattern into a material layer on a semiconductor wafer. The method includes steps of receiving a semiconductor mask made from a desired design layout and of patterning the material layer present on a plurality of semiconductor wafers with the mask having the mask pattern and an illumination pattern. The method further includes steps of identifying defects and/or defect patterns in the transference of the mask pattern on the plurality of semiconductor wafers, determining an illumination modification, and applying the illumination modification to the illumination pattern to create a modified illumination pattern. Additional methods and associated systems are also provided.

Abstract: Techniques are disclosed for optimizing the pattern density in the circuit layout design of a circuit layer. A layer in circuit design is analyzed to define empty regions that can be filled with fill polygons (referred to hereafter as “fill” regions). Next, a pattern of fill polygons is generated. After the fill polygons have been defined, the layout design for the layer is divided into separate areas or “windows,” and a target density for each window is determined. Once this target density for the window has been determined, the fill polygons required to most closely approach this target density are generated and added to the circuit layout design. This process may be repeated with progressively different (e.g., smaller) fill polygons, until each window meets or exceeds both the specified minimum density and complies with the specified maximum density gradient.

Abstract: The present disclosure provides a method of fabricating a semiconductor device. A first layout design for a semiconductor device is received. The first layout design includes a plurality of gate lines and an active region that overlaps with the gate lines. The active region includes at least one angular corner that is disposed adjacent to at least one of the gate lines. The first layout design for the semiconductor device is revised via an optical proximity correction (OPC) process, thereby generating a second layout design that includes a revised active region with a revised corner that protrudes outward. Thereafter, the semiconductor device is fabricated based on the second layout design.

Abstract: A method and apparatus of a novel full chip edge-based mask three-dimensional (3D) model for performing photolithography simulation with consideration for edge coupling effect is described. The method receives a mask design layout in order to perform mask topography effect modeling. The method generates scaling parameters for edge coupling effects. Each scaling parameter has an associated combination of feature width and space. The sum of feature width and space associated with at least one scaling parameter is less than a minimum pitch. The method applies a thick mask model that includes several edge-based kernels to the mask design layout to create a mask 3D residual. To apply the thick mask model to the mask design layout, the method updates the edge-based kernels with the scaling parameters.

Abstract: A method, system or computer usable program product for preventing odd cycles caused by design modifications to a double patterning layout including utilizing a processor to identify a set of double patterning cycles in the layout for storage in a memory; receiving a set of design modifications to the layout; utilizing the processor to identify from the set of double patterning cycles a subset of double patterning cycles affected by the set of design modifications; utilizing the processor to identify from the set of design modifications a subset of design modifications which may cause odd cycles in the subset of double patterning cycles; and providing a notification of the subset of design modifications.

Abstract: A method includes performing a place and route operation using an electronic design automation tool to generate a preliminary layout for a photomask to be used to form a circuit pattern of a semiconductor device. The place and route operation is constrained by a plurality of single patterning spacer technique (SPST) routing rules. Dummy conductive fill patterns are emulated within the EDA tool using an RC extraction tool to predict locations and sizes of dummy conductive fill patterns to be added to the preliminary layout of the photomask. An RC timing analysis of the circuit pattern is performed within the EDA tool, based on the preliminary layout and the emulated dummy conductive fill patterns.

Abstract: A transistor and method of fabrication thereof includes a screening layer formed at least in part in the semiconductor substrate beneath a channel layer and a gate stack, the gate stack including spacer structures on either side of the gate stack. The transistor includes a shallow lightly doped drain region in the channel layer and a deeply lightly doped drain region at the depth relative to the bottom of the screening layer for reducing junction leakage current. A compensation layer may also be included to prevent loss of back gate control.

Abstract: The present invention relates to lithographic apparatuses and processes, and more particularly to tools for co-optimizing illumination sources and masks for use in lithographic apparatuses and processes. According to certain aspects, the present invention enables full chip pattern coverage while lowering the computation cost by intelligently selecting a small set of critical design patterns from the full set of clips to be used in source and mask optimization. Optimization is performed only on these selected patterns to obtain an optimized source. The optimized source is then used to optimize the mask (e.g. using OPC and manufacturability verification) for the full chip, and the process window performance results are compared. If the results are comparable to conventional full-chip SMO, the process ends, otherwise various methods are provided for iteratively converging on the successful result.

Abstract: The present disclosure relates to lithographic apparatuses and processes, and more particularly to tools for optimizing illumination sources and masks for use in lithographic apparatuses and processes. According to certain aspects, the present disclosure significantly speeds up the convergence of the optimization by allowing direct computation of gradient of the cost function. According to other aspects, the present disclosure allows for simultaneous optimization of both source and mask, thereby significantly speeding the overall convergence. According to still further aspects, the present disclosure allows for free-form optimization, without the constraints required by conventional optimization techniques.

Abstract: System and methods for design-for-manufacturing and design-enabled-manufacturing (DFM-DEM) proactive integrated manufacturing flow are presented. A method includes receiving design data related to layout of an integrated circuit (IC); extracting information from the design data; and performing analysis on the extracted information. The method also enables DFM-DEM aware manufacturing applications using information stored in a knowledge database. The method further updates the knowledge database with new information learned from at least the extracted information and the analysis.

Abstract: A simulation method includes acquiring processing conditions for performing an etching process using plasma on a surface of a wafer covered by a mask having a predetermined mask thickness and aperture ratio, calculating, based on the conditions, a flux amount of a reaction product that enters the surface, calculating, based on mask information including the thickness and the aperture ratio and the flux amount, an etching rate of the wafer, calculating, based on the conditions and the etching rate, a dissociation fraction of the product, calculating, based on the information and the etching rate, a solid angle at a predetermined evaluation point set on the surface, the solid angle corresponding to a view area in which plasma space can be seen from the evaluation point, and calculating, based on the etching rate, the dissociation fraction, the solid angle, and the aperture ratio, a control index for evaluating a surface shape.

Abstract: A method of determining focal planes during a photolithographic exposure of a wafer surface is provided. The method may include receiving data corresponding to a surface topography of the wafer surface and determining, based on the received data corresponding to the surface topography, a plurality of regions having substantially different topographies. Reticle design data is received for exposure on the wafer surface, whereby, from the received reticle design data, reticle design data subsets that are each allocated to a corresponding one of the determined plurality of regions are generated. A best fit focal plane is then generated for each of the determined plurality of regions.

Abstract: A method for mask data preparation or mask process correction is disclosed in which a set of charged particle beam shots is determined which is capable of forming a pattern on a surface, wherein critical dimension uniformity (CDU) of the pattern is optimized. In some embodiments the CDU is optimized by varying at least two factors. In other embodiments, model-based techniques are used. In yet other embodiments, the surface is a reticle to be used in an optical lithographic process to form a pattern on a wafer, and CDU on the wafer is optimized.

Abstract: Methods are provided to facilitate automated creation and management of design rule checking or DRC waiver descriptions. Embodiments include receiving a plurality of first checksums corresponding to respective first geometric element violations waived in association with a block of an integrated circuit design, the first checksums being based on a first version of at least one design verification rule and/or of the block, receiving a second checksum corresponding to a second geometric element violation associated with the block, the second checksum being based on a second version of the design verification rule and/or of the block, determining whether the second checksum corresponds to at least one of the first checksums, and, if the second checksum does not correspond to at least one first checksum, generating a waiver request for the second geometric element error.

Abstract: A method of patterning a plurality of layers of a work piece in a series of writing cycles in one or a plurality of write machines, the workpiece being deviced to have a number of N layers and layers of the workpiece having one or a plurality of boundary condition(s) for pattern position, the method comprising the steps of: determining the boundary conditions of layers 1 to N, calculating deviations due to the boundary conditions and calculating a compensation for the deviation of the first transformation added with the assigned part of the deviation due to the boundary conditions.

Abstract: A layout decomposition method and a method for manufacturing a semiconductor device applying the same are provided. According to the layout decomposition method, a design layout is received by the logic processer of a computing system. A design rule for layout decomposition is then identified by the logic processer, including identifying the loose areas (areas with loosely distributed features) and dense areas (areas with densely distributed features) on a substrate, and identifying first areas with odd-numbered features and second areas with even-numbered features on the substrate. Next, a first mask with a first pattern and a second mask with a second pattern are generated corresponding to results of design rule identification by the computing system.

Abstract: A design or lithographic enhancement process, a method for forming a device based on the lithographic enhancement process and a system for pattern enhancement are presented. The process includes processing a design data file. The design data file includes information of design layers in an integrated circuit (IC). Processing the design data file includes analyzing the design data file and patterns in the design data file are enhanced taken into consideration topography information of design layers corresponding to masks of the IC.

Abstract: The present disclosure relates to a method of integrated chip (IC) design pattern correction that reduces pattern correction cycle time by separately correcting main feature shapes and dummy shapes of the IC design, and an associated apparatus. In some embodiments, the method is performed by forming an IC design having a plurality of main feature shapes. A plurality of dummy shapes are added to the IC design to improve a process window of the IC design. The plurality of main feature shapes are corrected using a first pattern correction process. One or more of the plurality of dummy shapes are subsequently corrected using a second pattern correction process separate from the first pattern correction process. By separately correcting dummy shapes and main feature shapes, the dummy shapes can be subjected to a different pattern correction process having lower time/resource demands, thereby reducing the pattern correction cycle time.

Abstract: Some embodiments of the present disclosure relate to a method to simulate patterning of a layout. The method comprises simulating formation of a layout pattern under a first lithography condition. The first lithography condition comprises a set of parameters, wherein a value of each parameter is defined by a corresponding process model. The method further comprises randomly varying the value of each parameter of the first lithography condition within a range of values defined by the corresponding process model of the parameter, to create a second lithography condition. Formation of a layout pattern is then re-simulated under the second lithography condition. Random variation of the value of each parameter is repeated to create additional lithography conditions. And, each lithography condition is re-simulated until the value of each parameter has been substantially varied across a range of its respective process model.

Abstract: An embodiment of a feed-forward method of determining a photomask pattern is provided. The method includes providing design data associated with an integrated circuit device. A thickness of a coating layer to be used in fabricating the integrated circuit device is predicted based on the design data. This prediction is used to generate a gradating pattern. A photomask is formed having the gradating pattern.

Abstract: A semiconductor integrated circuit designing method capable of minimizing a parasitic capacitance generated by an overhead in conductive lines, especially a gate line, a semiconductor integrated circuit according to the designing method, and a fabricating method thereof are provided. A method of designing a semiconductor integrated circuit having a FinFET architecture, includes: performing a pre-simulation of the semiconductor integrated circuit to be designed; designing a layout of components of the semiconductor integrated circuit based on a result of the pre-simulation, the components comprising first and second device areas and a first conductive line extending across the first and second device areas; modifying a first cutting area, that is arranged between the first and second device areas and electrically cuts the first conductive line, according to at least one design rule to minimize an overhead of the first conductive line created by the first cutting area.

Abstract: A method comprises (a) providing an integrated circuit (IC) layout comprising data representing a plurality of circuit patterns to be formed on or in a single layer of an IC by multi-patterning; (b) dividing the plurality of circuit patterns into two or more groups; (c) assigning the circuit patterns within each group to a respective mask to provide mask assignment data, for forming each group of circuit patterns on or in the single layer of the IC; (d) compressing the mask assignment data; and (e) storing the compressed mask assignment data to a non-transitory machine readable storage medium for use by an electronic design automation tool configured for reconstructing the mask assignment data from the compressed data.

Abstract: An integrated circuit includes a first conductive structure of a device configured to have a first voltage potential, a second conductive structure of the device configured to have a second voltage potential that is different than the first voltage potential, and a peacekeeper structure disposed between and separating the first conductive structure and the second conductive structure. The peacekeeper structure is separated from at least one of the first conductive structure and the second conductive structure by a fixed spacing distance for conductive lines for a self-aligned double patterning (“SADP”) process from the integrated circuit was formed.

Abstract: A multiple-patterned semiconductor device is provided. The semiconductor device includes one or more layers with signal tracks defined by masks and a structure for transferring a signal between signal tracks and repowering the signal.

Abstract: A plurality of gate electrode patterns to be laid out in parallel are alternately set as first patterns to be formed in a first exposure step of double patterning and as second patterns to be formed in a second exposure step. Subsequently, a circuit that includes transistor pairs each formed by connecting one of the first patterns and one of the second patterns in parallel is laid out. This reduces the risk of variations in characteristics of transistors caused by double patterning.

Abstract: A method of correcting assist features includes the following steps. At first, a first layout pattern is received by a computer system, and the first layout pattern is split into a plurality of first regions. Subsequently, a plurality of assist features are added into the first layout pattern to form a second layout pattern, wherein at least one of the assist features neighboring any one of the edges of the first regions is defined as a selected pattern. Then, the second layout pattern is split into a plurality of second regions. Afterwards, a check step is performed on the second region including the selected pattern, and the second layout pattern is corrected to form a corrected second layout pattern.

Abstract: One or more techniques or systems for incorporating a common template into a system on chip (SOC) design are provided herein. For example, a common template mask set is generated based on a first set of polygon positions from a first vendor and a second set of polygon positions from a second vendor. A third party creates a third party SOC design using a set of design rules generated based on the common template mask set. The common template is fabricated based on the third party SOC design using the common template mask set. Because the common template is formed using the common template mask set and because the common template mask set is based on polygon positions from both the first vendor and the second vendor, a part can be connected to the SOC regardless of whether the part is sourced from the first vendor or the second vendor.