Abstract: A rules definition language the authoring rules for concurrent processing. The RDL includes statements that facilitate efficient use of computer resources by allowing a rule to be broken down into one or more instructions, and processing these instructions asynchronously to provide more efficient use of the computer resources. Once processed into the instructions, results thereof can be passed among the instructions to facilitate process completion of the rule.

Abstract: A method and an apparatus that execute a parallel computing program in a programming language for a parallel computing architecture are described. The parallel computing program is stored in memory in a system with parallel processors. The system includes a host processor, a graphics processing unit (GPU) coupled to the host processor and a memory coupled to at least one of the host processor and the GPU. The parallel computing program is stored in the memory to allocate threads between the host processor and the GPU. The programming language includes an API to allow an application to make calls using the API to allocate execution of the threads between the host processor and the GPU. The programming language includes host function data tokens for host functions performed in the host processor and kernel function data tokens for compute kernel functions performed in one or more compute processors, e.g. GPUs or CPUs, separate from the host processor.

Abstract: A runtime system implemented in accordance with the present invention provides an application platform for parallel-processing computer systems. Such a runtime system enables users to leverage the computational power of parallel-processing computer systems to accelerate/optimize numeric and array-intensive computations in their application programs. This enables greatly increased performance of high-performance computing (HPC) applications.

Abstract: A runtime system implemented in accordance with the present invention provides an application platform for parallel-processing computer systems. Such a runtime system enables users to leverage the computational power of parallel-processing computer systems to accelerate/optimize numeric and array-intensive computations in their application programs. This enables greatly increased performance of high-performance computing (HPC) applications.

Abstract: In a multi-thread executing method of dividing a single program into a plurality of threads and executing the program by a plurality of processors in parallel, at a time of every fork instruction of the executing thread, when there already exists a child thread generated form the above thread, the program cancels the child thread or makes invalid all the fork instructions other than the first fork instruction having succeeded in forking the child thread, hence to select one fork instruction for creating an effective child thread from a plurality of fork instructions existing within a parent thread, during the execution of the parent thread. Therefore, it can assure the Fork-Once limitation at a time of the program execution.

Abstract: A parallel or computing system and method make use of a plurality of adapters each affording a specific type of processing algorithm. At each point in an application, an adapter is identified, to parallelize that portion of the application. The process involves associating an appropriate adapter with the application portion, parsing the application portion to define tasks that may be distributed over the available computers. Combined with the parallelized program is a software server that is designed to cooperate with the adapters to control and supervise distributed processing functions. Such functions include mapping, load balancing, and error detection and correction. Also included are functions that cause the results of the computing to be coordinated in real-time and returned appropriately, according to the application.

Abstract: Processing circuits that are associated with the operation of threads in an SMT processor can be configured to operate at different performance levels based on a number of threads currently operated by the SMT processor. For example, in some embodiments according to the invention, processing circuits, such as a floating point unit or a data cache, that are associated with the operation of a thread in the SMT processor can operate in one of a high power mode or a low power mode based on the number of threads currently operated by the SMT processor. Furthermore, as the number of threads operated by the SMT operator increases, the performance levels of the processing circuits can be decreased, thereby providing the architectural benefits of the SMT processor while allowing a reduction in the amount of power consumed by the processing circuits associated with the threads. Related computer program products and methods are also disclosed.

Abstract: According to an embodiment, a computer system displays, on a display, a GUI dialog box that prompts an operator to set the identification name and thread type of a source file that describes source code of a thread. When the identification name and thread type of the source file are set via the GUI dialog box, the computer system acquires a source code template corresponding to that thread type, and reflects the identification name set via the GUI dialog box in that source code template. The computer system generates a source file with the identification name set via the GUI dialog box in the basis of the source code template. The computer system stores the identification name and thread type set via the GUI dialog box in a definition file as thread definition information of the source file set with the identification name.

Abstract: A data access method in an information system including a plurality of data utilization systems connected to a network N1, and a plurality of data provision systems connected to a network, wherein a data utilization system transmits a request for utilizing data in a data provision system to another data utilization system P2 through the network N1, the data utilization system, upon receipt of the data utilization request, transmits a processing execution request corresponding to the data utilization request to the data provision system through the network N2, the data provision system, upon receipt of the execution request, executes processing corresponding to this execution request and transmits necessary data to the data provision system through the network, and the data provision system receives the data and stores the same.

Abstract: A parallel loop transformation method for race detection during an execution of parallel programs that includes generating a data structure of a condition statement branch determinant string Cstr required for loop transformation by taking an original parallel loop as an input and extracting execution path information, transforming the original parallel loop into a full race covering loop using the data structure of the condition statement branch determinant string Cstr required for loop transformation and the execution path information as an input statement, instrumenting the race detection function in order to activate the race detection function for the transformed parallel loop which are previously generated, and executing the race detection while running the parallel programs according to instrumented detection functions.

Abstract: A method to perform the insertion, deletion and updating of data in table-format data quickly and appropriately. A CPU 12 accepts a record number as a subscript, generates a subscript conversion array for giving an offset value corresponding to the range of the subscript in question, identifies the insertion position which indicates the position of the field value to be inserted, and, in the subscript conversion array, gives an offset value that defines the range of the corresponding subscript and also identifies the end of the array, and in the subscript conversion array, gives an offset value that increments the corresponding range of subscripts and also decrements the accepted subscript, and places the field value to be inserted at the stipulated end position, such that an offset value according to the range of subscripts within the subscript conversion array is given as the subscript.

Abstract: A process modeling tool for graphically representing a process which includes transactions and events, and for generating computer code representing the process. A graphical tool creates a graphical representation of the transactions and events with graphical symbols, where one or more of such transactions and events may be of an asynchronous nature. A code generator generates computer code in response to information contained in the graphical representation. The computer code is executable on a computer system to cause the computer system to perform one or more operations which emulate the process shown in the graphical representation.

Abstract: A modified JAVA(™) execution environment is described. The modified environment supports multiple JAVA(™) applications on a single JAVA(™) virtual machine (JVM). This modified environment provides significant memory and performance improvements when running multiple applications on a single computer system. Notably, no changes are needed to the source code of an application to take advantage of the modified environment. Further, embodiments of the invention may support shared access to base classes through the use of overlays. Additionally, system resource permissions can be enforced based upon the user permissions associated with a running application. Notably, embodiments of the invention allow multiple applications to share the abstract window toolkit (AWT) on a per display basis. Since only a single garbage collection routine is necessary, applications see improved performance relative to running in different JVMs. Further, the shared base classes eliminate significant memory overhead.

Abstract: Embodiments of the present invention relate generally to the manner in which processors execute multiple loop instructions. That is, embodiments of the invention relate to the organization of multiple loop constructs, such as, for example, nested loops, to achieve improved performance during loop execution. One embodiment contemplates a single instruction that provides for execution of other instructions of a set of instructions in accordance with multiple looping constructs. Another embodiment contemplates a single-loop instruction suitable for terminating on multiple termination conditions.

Abstract: A method and mechanism for implementing a general purpose scripting language that supports parallel execution is described. In one approach, parallel execution is provided in a seamless and high-level approach rather than requiring or expecting a user to have low-level programming expertise with parallel processing languages/functions. Also described is a system and method for performing circuit simulation. The present approach provides methods and systems that create reusable and independent measurements for use with circuit simulators. Also disclosed are parallelizable measurements having looping constructs that can be run without interference between parallel iterations. Reusability is enhanced by having parameterized measurements. Revisions and history of the operating parameters of circuit designs subject to simulation are tracked.

Abstract: The first model described in a software description language is converted into the second model described in a hardware description language without considering whether a plurality of parallel procedures for writing with respect to the same shared variable are contained in the first model. It is detected whether a plurality of parallel processes corresponding to the plurality of parallel procedures for writing with respect to the same shared variable exist in the second model obtained in this manner. A value solving process is generated, in which a pair of a data signal and an assignment timing signal are input from each process of all or some of the detected parallel processes, and a signal of the data signals which corresponds to a process in which the assignment timing signal has changed is output to a signal holding the value of the shared variable.

Abstract: The latencies associated with retrieving instruction information for a main thread are decreased through the use of a simultaneous helper thread. The helper thread is a speculative prefetch thread to perform instruction prefetch and/or trace pre-build for the main thread.

Abstract: The latencies associated with retrieving instruction information for a main thread are decreased through the use of a simultaneous helper thread. The helper thread is permitted to execute Store instructions. Store blocker logic operates to prevent data associated with a Store instruction in a helper thread from being committed to memory. Dependence blocker logic operates to prevent data associated with a Store instruction in a speculative helper thread from being bypassed to a Load instruction in a non-speculative thread.

Abstract: A method for generating instructions to facilitate control-quasi-independent-point multithreading is provided. A spawn point and control-quasi-independent-point are determined. An instruction stream is generated to partition a program so that portions of the program are parallelized by speculative threads. A method of performing control-quasi-independent-point guided speculative multithreading includes spawning a speculative thread when the spawn point is encountered. An embodiment of the method further includes performing speculative precomputation to determine a live-in value for the speculative thread.

Abstract: A software-implemented method and implementation is disclosed for commissioning an automated system. The implementation analyzes the configuration of one or more operational components in the automated system and generates one or more operator communication and monitoring masks for each of the operational components. An interface is provided with the at least one mask to parametize the at least one operational component.

Abstract: Index association based dependence analysis accurately determines lack of dependence for complex memory subscript references to allow greater use of loop transformation and automatic parallelization at compile of an application. Index association functions that map an original i index space to a dependence analysis j index space are analyzed at compile to determine one-to-one mapping or many-to-one mapping. For dependence analysis of two references with a one-to-one mapping determination, lack of dependence in the dependence analysis index space confirms lack of dependence in the original index space. For many-to-one mapping, both a lack of dependence in the dependence analysis index space and a check that no two iterations in the original index space could map to the two references in the dependence analysis index space confirms no dependence for the two references.

Abstract: The method, system and tangible medium storing computer readable software of the present invention, provide for program constructs, such as commands, declarations, variables, and statements, which have been developed to describe computations for an adaptive computing architecture, rather than provide instructions to a sequential microprocessor or DSP architecture. The invention includes program constructs that permit a programmer to define data flow graphs in software, to provide for operations to be executed in parallel, and to reference variable states and historical values in a straightforward manner. The preferred method, system, and software also includes mechanisms for efficiently referencing array variables, and enables the programmer to succinctly describe the direct data flow among matrices, nodes, and other configurations of computational elements and computational units forming the adaptive computing architecture.

Abstract: An optimizing system, method and computer readable recording medium to increase the speed of parallel processing by allowing a mixture of automatic creation of parallel processes and OpenMP API processing and to prevent reduction in performance during parallel processing by controlling the generation of wasted threads when automatic parallel processing and OpenMP API call each other. The optimizing system, method and recording medium create object code that creates parallel processes from a source program coded in a specific programming language, wherein the program is performed using a plurality of threads. The optimizing system generates object code for a source program which is executed in parallel by generating a plurality of threads.

Abstract: Multiple instructions, specifying equivalent operations but designating different execution units, are stored beforehand on an instruction exchange table. First, a primary compiler compiles a source program into a set of machine-readable instructions. From the set of instructions, an instruction parallelizer generates a set of long instruction words. Specifically, an instruction identifier identifies one of the instructions in the set with one of the instructions stored on the instruction exchange table. Then, an instruction replacer replaces the instruction in question with another one of the instructions that is also stored on the instruction exchange table, specifies an equivalent operation but designates a different execution unit as a target. In this manner, the number of parallelly executable instructions can be increased, while the number of no-operation instructions can be reduced, thus generating a parallelized instruction set at a higher level of parallelism.

Abstract: A computer system or peripheral device includes an arithmetic-logic circuit that provides, for example, in binary parallel format a maximum code from a set of input codes, each input code in binary parallel format. The circuit has minimal propagation delay owing to its expandable architecture which includes: an array of product term generators, a summary term generator, and a selection circuit. Each product term generator primarily includes one AND gate per product term having inputs that combine bits of an input code, the product terms being organized in sets. The summary term generator includes one OR gate for each summary term. The selection circuit includes a multiplexer for each set having data inputs responsive to summary term signals and control inputs responsive to summary term signals of higher significance than the highest summary term on a data input of the multiplexer. In illustrated embodiments, a printer includes an integrated circuit processor of the present invention.

Abstract: A system for adding functionality to a graphical user interface of a non-Java based, or native, application, using the Java programming language is provided. A Java window, or dialog, is configured to be accessible by a native application. While the native application is executed in a first thread, a Java dialog is launched in a second thread. Execution of the native application in the first thread is then continued. The Java dialog next calls the native application and registers itself with the native application. Also, the native code can control the Java dialog like other dialogs supported by the native code. A command for a Java dialog from a native application is routed to an invisible dialog. The invisible dialog passes that command to the Java dialog through a native interface connection. A very seamless integration between the Java and native code thus occurs. The graphical user interface operates and visually appears as if controlled from a single source of code.

Abstract: According to an embodiment, a computer system displays, on a display, a GUI dialog box that prompts an operator to set the identification name and thread type of a source file that describes source code of a thread. When the identification name and thread type of the source file are set via the GUI dialog box, the computer system acquires a source code template corresponding to that thread type, and reflects the identification name set via the GUI dialog box in that source code template. The computer system generates a source file with the identification name set via the GUI dialog box in the basis of the source code template. The computer system stores the identification name and thread type set via the GUI dialog box in a definition file as thread definition information of the source file set with the identification name.

Abstract: When converting a sequential execution source program into a parallel program to be executed by respective processors (nodes) of a distributed shared memory parallel computer, a compiler computer transforms the source program to increase a processing speed of the parallel program. First, a kernel loop having a longest sequential execution time is detected in the source program. Next, a data access pattern equal to that of the kernel loop is reproduced to generate a control code to control first touch data distribution. The first touch control code generated is inserted in the parallel program.

Abstract: The present invention relates to parallel loop transformation methods for race detection during an execution of parallel programs which is one of the debugging methods for parallel loop programs. Using the information obtained from a static analysis of parallel loop bodies, the monitoring time for race detection is improved by transforming the loop bodies in order for only the necessary iterations for race detection can be dynamically selected during the execution. Specifically, in comparison to the conventional monitoring methods which typically consumes a long time since they monitor the full iterations for each parallel loop in parallel loop programs, by monitoring two times of the execution paths irrespective of the parallelism of each parallel loop, the present invention can significantly reduce the execution time. As a result, the present invention allows a convenient race detection of parallel loop programs therefore making the race detection more practical.

Abstract: A method and apparatus for a atomic operation is described. A method comprises receiving a first program unit in a parallel computing environment, the first program unit including a memory update operation to be performed atomically, the memory update operation having an operand, the operand being of a data-type and of a data size, and translating the first program unit into a second program unit, the second program unit to associate the memory update operation with a set of one or more low-level instructions upon determining that the data size of the operand is supported by the set of low-level instructions, the set of low-level instructions to ensure atomicity of the memory update operation.

Abstract: A method of, apparatus for and computer-readable medium for obtaining a program for a distributed memory-type parallel computer by dividing data for a program written for a serial processing computer. The method comprises changing a declaration of an array to be subjected to indirect or irregular division which is designated by the mapping array in the program into a declaration of an allocation array; inserting statements to declare the allocation array for converting subscripts and to calculate the size of the divided array during processing, and inserting a statement to preserve or to release an area for divided arrays corresponding to the calculated length of arrays to be divided and subscript conversion arrays during processing.