Abstract: A method for detecting computational errors in a digital processor executing a program. Initially, the program is divided into computation segments, and source code for at least one of the segments is compiled to generate two redundant code sections. Comparison code is generated for comparing results produced by execution of the two code sections. Each of the code sections is then executed in a different computational domain to generate respective results. The results of the computation are executed to alter further flow of the program only if the respective results are identical.

Abstract: A method of tracing activity of a data processor generates a trace data stream during a normal background mode and a foreground mode while servicing a real time interrupt during an emulation halt. An Interrupt During Suspend bit is set in foreground modes and transmitted in the trace data stream to distinguish the trace data streams between background mode and foreground mode.

Abstract: Described herein is a technology facilitating the operation of non-native program modules within a native computing platform. This invention further generally relates to a technology facilitating the interoperability of native and non-native program modules within a native computing platform. More specifically, this technology involves an emulation of the kernel of the non-native operating system. Instead of interacting with the native kernel of the native computing platform, the non-native program modules interact with a non-native kernel emulator. This abstract itself is not intended to limit the scope of this patent. The scope of the present invention is pointed out in the appending claims.

Abstract: The present invention is directed to an extensible console emulator for Hyperion Performance Suite interaction. An emulator system in accordance with an embodiment of the present invention includes: a Hyperion Performance Suite (HPS) console emulator for receiving commands from a source and for performing actions based on the commands; and an HPS Software Development Kit (SDK) for receiving output from the HPS console emulator and for interacting with the HPS; wherein the HPS console emulator provides an interface that allows a user to interact with the HPS via the HPS SDK.

Abstract: A method and system for accessing, from a mirror probe handler, a value to be associated with an argument of a function. The mirror probe handler and the function are defined with identical prototypes and compiled with identical linkage conventions. The mirror probe handler is executed after initiating execution of the function, executing a probe placed in the function, and saving a state of processor registers. While executing the mirror probe handler, a reference to an argument of the mirror probe handler seamlessly accesses the value via automatically employing at least one of the processor registers. The access is facilitated by the identical prototypes and the compilations with identical linkage conventions. After the reference accesses the value, the saved state is restored, which facilitates the execution of the function, which was temporarily replaced by the execution of the probe and mirror probe handler.

Abstract: Provided are a method, system, and article of manufacture for the traversal of empty regions in a searchable data structure such as a table. A plurality of elements are allocated in logical storage, wherein the plurality of elements correspond to entries of the searchable data structure. An indicator is maintained corresponding to contiguously allocated empty elements in the plurality of elements. An operation is performed on the searchable data structure by avoiding the contiguously allocated empty elements.

Abstract: In general, in one aspect, the invention relates to a method for transforming binaries to use different instructions. The method includes identifying an instruction in the binary, where the instruction is an unimplemented instruction of an instruction set of a processor. The method further includes replacing the instruction with emulation code, where execution of the emulation code emulates execution of the instruction, and generating an updated binary including the emulation code.

Abstract: The present invention compensates for the shortcomings in x86 processor architectures by providing a set of “synthetic instructions” that cause a trap and thereby provide an opportunity for the virtual machine (VM) to process the instructions safely. By using instructions that are “illegal” to the x86 architecture, but which are nonetheless understandable by a virtual machine, the method of using these synthetic instructions to perform well-defined actions in the virtual machine that are otherwise problematic when performed by traditional instructions to an x86 processor but provide much-improved processor virtualization for x86 processor systems.

Abstract: A mechanism for incorporating user input modes in a scripting language are provided for. A context allows use of user input modes in a scripting language in a manner that corresponds to their use in a GUI. A programming construct, referred to as a context, specifies at least one user input mode and a state for the user input mode that are applied to a set of instructions. The operations specified by the instructions that are referenced by a context are executed as if the user input modes referred to by the contexts have the state specified by the contexts.

Abstract: A method for prevention of system execution malfunction is provided. First, an IDL (Interface Definition Language) file is compiled using an IDL compiler to generate a compiled IDL file. The compiled IDL file is converted by defining additional operations corresponding to a specific operator in the compiled IDL file. When a program comprising the converted file is executed with the specific operator, the additional operations are performed before original operations thereof.

Abstract: A system, method and a computer program product for emulating a tape-based storage system to provide data storage. The system includes a data storage medium storing a data set which represents the data layout of the emulated tape-based medium, and an interface for providing access to a non-tape-based data storage medium, using tape-based media commands and using the data set. The fist data set includes filemark location data and block number data for mapping between filemark locations and block numbers of the emulated tape-based storage medium and the non-tape-based data storage medium.

Abstract: An emulation system that provides the functionality of an emulated computer on a host computer pre-processes the object code file to be emulated to reduce the run-time overhead due to parsing the object code. The emulator uses preprogrammed functions that model each instruction of the emulated computer. An object code file is pre-parsed to generate a translated file which includes a sequence of function calls corresponding to the sequence of instructions in the code file. The translated file is compiled to generate a corresponding translated object-code file. The translated object-code file is executed in the emulation environment on the host computer. The emulation system also includes a standard mode in which the object code file is emulated by sequentially parsing each instruction in the object code file and invoking an appropriate one of the preprogrammed functions in the emulated environment.

Abstract: A source computer system with one instruction set architecture (ISA) is configured to run on a target hardware system that has its own ISA, which may be the same as the source ISA. In cases where the source instructions cannot be executed directly on the target system, the invention provides binary translation system. During execution from binary translation, however, both synchronous and asynchronous exceptions may arise. Synchronous exceptions may be either transparent (requiring processing action wholly within the target computer system) or non-transparent (requiring processing that alters a visible state of the source system). Asynchronous exceptions may also be either transparent or non-transparent, in which case an action that alters a visible state of the computer system needs to be applied.

Abstract: An embodiment of the invention is a technique for enabling an emulator that emulates an e-mode program to utilize stored data items whose values are stored in native data format in native memory. The emulator fetches an item referenced by the e-mode program. The referenced item comprises a tag field and a data field. The emulator determines whether the tag field of the referenced item indicates that the referenced item is an external reference word (ERW). If the tag field of the referenced item indicates that the referenced item is an ERW, the emulator decodes the ERW to obtain a data type and a pointer. The pointer corresponds to a location of a stored data item in native memory.

Abstract: Protocol conversion is disclosed. A first transaction of a first protocol and a second transaction of a second protocol are accessed. From the accessed transactions, a plurality of protocol conversions are computed. Additional transactions of the first protocol and additional transactions of the second protocol can be accessed, and further protocol conversions applicable between the additional first and the second transactions can be computed. Based on at least some of the applicable protocol conversions, a combined controller that is able to convert between the transactions of the first and second protocols is generated. Instructions that are operable to describe the combined controller are stored in a computer readable medium.

Abstract: Provided are a method, system, and program for allocating call stack frame entries at different memory levels to functions in a program. Functions in a program accessing state information stored in call stack frame entries are processed. Call stack frame entries are allocated to the state information for each function, wherein the call stack frame entries span multiple memory levels, and wherein one function is capable of being allocated stack entries in multiple memory levels.

Abstract: A loader section (102) for converting a program from a class file to a runtime execution format, a runtime saving section (103) for performing a runtime saving process by which a runtime execution format is converted to a temporary runtime execution format, a temporary runtime execution format storing section (302) for storing a temporary runtime execution format, and a post-loader section (105) for performing a post-loader process by which a temporary runtime execution format is converted to a runtime execution format are included, and determination is made whether or not there is a temporary runtime execution format in the temporary runtime execution format storing section when a start-up of a program is instructed, the loader section is requested to perform conversion to a runtime execution format if there is none, and the post-loader section is requested to perform conversion to a runtime execution format if there is any.

Abstract: An emulation system that provides the functionality of an emulated computer on a host computer pre-processes the object code file to be emulated to reduce the run-time overhead due to parsing the object code. The emulator uses pre-programmed functions that model each instruction of the emulated computer. An object code file is pre-parsed to generate a translated file which includes a sequence of function calls corresponding to the sequence of instructions in the code file. The translated file is compiled to generate a corresponding translated object-code file. The translated object-code file is executed in the emulation environment on the host computer. The emulation system also includes a standard mode in which the object code file is emulated by sequentially parsing each instruction in the object code file and invoking an appropriate one of the preprogrammed functions in the emulated environment.

Abstract: A method for adapting a .Net framework compliant reflection mechanism to a Java™ environment, wherein the reflection mechanism allows a user to discover class information and invoke data members solely at runtime. The method includes gathering reflection related metadata from a .Net assembly class of a respective .Net class that comprises the metadata. The method also includes the steps of generating an attributes class comprising at least the reflection related metadata and a plurality of conversion methods and integrating the attributes class in a Java™ class file of the respective .Net class, such that the reflection mechanism is capable of adapting the reflection mechanism as defined in the .Net framework to the Java™ environment. Also disclosed is a plurality of conversion methods. The attributes class is included in a Java™ class file rendered by a compiler capable of compiling a .Net class to a Java™ compliant programming code.

Abstract: A system and method for providing a user interface system to develop an application having a first component with descriptors expressed in a structured definition language and a second component expressed as a series of instructions. The individual components interact for processing messages on a runtime environment of a device that are received from a data source over a network. The component applications comprise data components, presentation components, and message components, which are written in XML code. The component applications further comprise workflow components which are written in a subset of ECMAScript, and are augmented with the XML code. The user interface system comprises a first module, such as a viewer or and editor, for developing the definitions of the first component through interaction with a data model that provides a persistent state of the application.

Abstract: Described herein is a technology facilitating the operation of non-native program modules within a native computing platform. This invention further generally relates to a technology facilitating the interoperability of native and non-native program modules within a native computing platform. More specifically, this technology involves an emulation of the kernel of the non-native operating system. Instead of interacting with the native kernel of the native computing platform, the non-native program modules interact with a non-native kernel emulator. This abstract itself is not intended to limit the scope of this patent. The scope of the present invention is pointed out in the appending claims.

Abstract: A method, system and computer program product for creating a software product in an Integrated Development Environment (IDE). In one embodiment, remote object status data is received by a software development module which may be a source code editor or a program execution emulator. Responsive to the received data, the remote object status is rendered within a display medium of the software development module by decorating or otherwise distinguishing the remote OIDs in the IDE. In one embodiment in which the software development module is a source code editor, the method further includes detecting a remote object identifier in a source code file processed by the source code editor, and in response thereto, displaying the remote object status within the source code editor.

Abstract: An emulation-based event-wait simulator including an application module to configure and command verification processes on a design under test (DUT). An event dispatcher is in communication with the application module to deliver commands to the DUT. A plurality of transactors are in communication with the event dispatcher to forward the commands to the DUT. A channel controller is in communication with the transactors to process and forward the commands to the DUT, wherein the channel controller also receives messages from the DUT, processes the messages, and forwards the messages to the transactors for delivery to the event dispatcher and the application module.

Abstract: An emulation-based event-wait simulator including an application module to configure and command verification processes on a design under test (DUT). An event dispatcher is in communication with the application module to deliver commands to the DUT. A plurality of transactors are in communication with the event dispatcher to forward the commands to the DUT. A channel controller is in communication with the transactors to process and forward the commands to the DUT, wherein the channel controller also receives messages from the DUT, processes the messages, and forwards the messages to the transactors for delivery to the event dispatcher and the application module.

Abstract: A method for emulating a hardware design by time division multiplexing data communicated between an emulator and a runtime assist unit (RTAU), such as a behavior card. Data from the emulator may be received directly at the general purpose registers of the RTAU. A programmable delay may be used in conjunction with a step generator to initiate concurrent cycle processes. Code executed by the RTAU may be coded in assembly, and external interrupts that might otherwise affect the determined processing time of the RTAU task are disabled. The time multiplexing reduces card port, cabling and processing cycle requirements.

Abstract: A method and apparatus for processor emulation using speculative forward translation are disclosed. A potential candidate for forward translation is identified from one or more portions of target system code. A priority for forward translation is assigned to the potential candidate. It is determined whether the potential candidate is a valid candidate for forward translation. If valid, the potential candidate is translated with a host system to produce one or more corresponding blocks of translated code executable by the host system.

Abstract: A method for checking page size dependency including generating an interposing library comprising a first modified interface, wherein the first modified interface is dependent on a native page size, intercepting a call into a kernel by the interposing library, wherein the call is dependent on a non-native page size, modifying the call using the first modified interface to obtain a modified call, and generating a response to the modified call by the kernel using the native page size.

Abstract: Methods and apparatus to support the execution of a managed application that is linked to a native library or application are disclosed. The disclosed methods and apparatus support a virtual machine that is associated with the same ISA as the executing platform, while the ISA of the native library or application is of a different ISA. The disclosed methods and apparatus also support the execution of a managed application that is linked with several native libraries or applications that are associated with several different ISAs respectively.

Abstract: A method of translating instructions from a target instruction set to a host instruction set. In one embodiment, a plurality of first target instructions is translated into a plurality of first host instructions. After the translation, it is determined whether the plurality of first target instructions has changed. A copy of a second plurality of target instructions is stored and compared with the plurality of first target instructions if the determining slows the operation of the computer system. After comparing, the plurality of first host instructions is invalidated if there is a mismatch. According to one embodiment, the storing, the comparing and the invaliding is initiated when the determining indicates that a page contains at least one change to the plurality of first target instructions. In one embodiment, the determining is by examining a bit indicator associated with a memory location of the plurality of first target instructions.

Abstract: A mechanism is disclosed for enabling a set of code intended to be executed on a first platform (intended platform) to be executed on another platform (target platform). In one implementation, this mechanism takes a significantly different approach than that taken by current techniques. Rather than duplicating, augmenting, or changing a platform to accommodate the set of code, this mechanism alters the set of code to accommodate the platform. By altering the set of code, the mechanism causes the set of code to compensate for the difference(s) between the intended platform and the target platform. By compensating for the difference(s) in the two platforms, the set of code, when executed on the target platform, is able to produce the same result or results as it would have produced had it been executed on the intended platform. Thus, the set of code is able to execute properly on the target platform.

Abstract: According to one embodiment a method and apparatus for displaying the path of a computer program error as a sequence of hypertext documents in a computer system having a display is disclosed. The method includes displaying a first function in the control-flow path of the error as text in a first region on the display. Subsequently, a first hypertext link marker located within the first function, and associated with a second function called by the first and also lying on the error's control-flow path is selected. Thereafter, the second function's text associated with the first link marker is displayed in a second region. The second region is positioned in the first region such that the text of the first document is not obscured. The second region includes a first tab area that surrounds the first link maker after it is selected.

Abstract: A system for porting code from a native platform to a non-native platform is provided which utilizes a non-native, platform-specific layer of code and a platform-neutral layer of code. The platform-neutral layer substantially emulates the native platform of ported code and provides a platform-neutral interface to the ported code. Together, the platform-specific layer and the platform-neutral layer provide an execution environment in which the ported code operates as a kernel extension of the non-native platform. The platform-neutral layer of the execution environment is portable to other non-native platforms so that code can be ported to another non-native platform by replacing the platform-specific layer with a customized platform-specific layer, which is adapted to the other non-native platform.

Abstract: A method and system for enforcing version control is provided. An embodiment of the method comprises receiving a command to execute code. Code is retrieved from a code management storage and loaded into a controlled storage. The code may comprise test and program components. The code is executed and the results of the executed code are recorded and logged, and the code is removed from the controlled storage. The system includes an interface for receiving the execute code command and is coupled to the controlled storage. A code loader for loading code into the controlled storage may also be provided.

Abstract: Electronic design automation tool specifies an architecture at a system level and its component (which include intellectual property (IP) cores like embedded processors, arithmetic logic units (ALU), multipliers, dividers, embedded memory element, programmable logic cells, etc.); specifies IP-cores and their interface; and understands IP-cores and functions via their interface. Further, techniques are provided for modeling the timing behavior of a function or functional block without drawing a timing diagram; understanding the interface behavior of a function block which captures the timing waveforms; specifying virtual functions which are built using basic functional units and their timing behavior; parsing and creating an internal graphical form for analyzing a specification for compilation; matching the components in the architecture specification and their instantiation to map the computations in the input graph produced from an application; and mapping the specification onto the target's components.

Abstract: A method of porting code from a native platform to a non-native platform is provided which utilizes a non-native, platform-specific layer of code and a platform-neutral layer of code. The platform-neutral layer substantially emulates the native platform of ported code and provides a platform-neutral interface to the ported code. Together, the platform-specific layer and the platform-neutral layer provide an execution environment in which the ported code operates as a kernel extension of the non-native platform. The platform-neutral layer of the execution environment is portable to other non-native platforms so that code can be ported to another non-native platform by replacing the platform-specific layer with a customized platform-specific layer, which is adapted to the other non-native platform.

Abstract: A method of handling exceptions for use in an emulator (20) performing program code conversion. Registers (X) of a subject machine (11) being emulated (20) are represented by a pair of abstract registers (XA,XB) on the target machine (31), suitably using memory locations of the target machine and/or any available target registers. One of the pair (e.g., Reg XA) holds a definitive value at entry into a section (100) of subject code (10) while the other (e.g., Reg XB) holds a speculative value which is updated during translation and execution of that section of code. Exceptions are handled by recovering the conditions of the virtual subject machine (11) upon entry into the section of subject code (100) using the definitive version of each abstract register (i.e., Reg XA).

Abstract: A computer language translator that translates all or any portion thereof of source code in an original computer language to source code in a target computer language, which may then be translated back to the original language while still maintaining concept, syntax, form of expression, and formatting of the original source code.

Abstract: A real time data exchange on demand system for transferring real time data between a host processor and a target processor is described. The target processor includes a real time target exchange library and API library interface to a target application. The host processor includes a target server, a real time data exchange API interface to a host data exchange application and a real time data exchange dynamic link library. An interconnection data link is coupled between said real time target exchange library on said target processor and said real time data exchange dynamic link library on said host processor. The host processor includes a user interface for programming real time data exchange transfer points for data exchange into the target processor that are passed down to the target processor via the interconnection data link. The target processor has programmable triggers that are programmed by the transfer points that call an appropriate real time data exchange routine to do the data transfer.

Abstract: A method of generating an expected TOS during translation of instructions. The method includes translating a first block of instructions executable in a first processor architecture, into a translated first block of instructions executable in a second processor architecture, wherein the translated first block of instructions operate with a stack of data entry positions. During the translation, an expected Top of Stack (TOS) position in the stack for the first block of code is generated.

Abstract: A method for determining a process to use for converting instructions in a target instruction set to instructions in a host instructions set including the steps of executing code morphing software including an interpreter and a translator to generate host instructions from target instructions, detecting at intervals whether the interpreter or the translator is executing, increasing a count if the interpreter is executing and decreasing the count if the translator is executing, and changing from interpreting to translating a sequence of target instructions when the count reaches a selected maximum.

Abstract: An emulator (30) allows subject code (10) written for a subject processor (12) having subject processor registers (14) and condition code flags (16) to run in a non-compatible computing environment (2). The emulator (30) identifies and records parameters of instructions in the subject code (10) that affect status of the subject condition code flags (16). Then, when an instruction in the subject code (10) is encountered, such as a branch or jump, that uses the flag status to make a decision, the flag status is resolved from the recorded instruction parameters. Advantageously, emulation overhead is substantially reduced.

Abstract: This invention relates to the art of computer system emulation and, more particularly, to a computer system emulator in which the functions normally performed by the hardware in a legacy central processor unit are emulated by a software program. The invention is to enhance the emulated instruction set beyond that of the legacy machine such to include as new single instructions a method for invoking operating system functions, with the machine coding of the operating system functions now being performed by machine code native to the new host machine, rather than as a sequence of emulated legacy instructions.

Abstract: System and method for debugging a program intended for execution on a programmable hardware element (PHE) to perform a function. A first portion of the program is converted into a first hardware configuration program (HCP) deployable on the PHE, where a remaining portion is to be debugged by a user. The PHE is configured with the first HCP, and the program executed, including the PHE executing the first portion of the program, and the computer system executing the remaining portion, which is then analyzed and debugged in response to being executed, and user input received modifying the remaining portion to debug the remaining portion. The method is repeated, where in each iteration the first portion is a successively larger portion of the program. After being debugged, the program is converted into a second HCP deployable on the PHE to perform the function, and the PHE configured with the second HCP.

Abstract: In an emulated computing environment, a method is provided for licensing software of one or more guest computer systems. A license key server is provided in the host computer system for monitoring the initiation of unlicensed software, including operating system software, in the guest computer system. A determination is made by the license key server as to whether additional a license is available for each unlicensed software application. If a license is available, a license is granted and the count of available licenses is decremented. If a license is not available, a license is not granted and the unlicensed software application in the guest computer system is disabled.

Abstract: Disclosed is a technology of converting a first assembly language program implementable on a first processor to a second assembly language program implementable on another processor. The two assembly language programs are described using same instructions. A unique address in the first assembly language program is assigned to a first number of bytes, and a unique address in the second assembly language program is assigned to a second number of byte numbers. The first number is larger than the second number. The first assembly language program is read from a storage. Thereafter, one or more address descriptions of the first assembly language program are translated to another one or more address descriptions using a ratio of the first number to the second number so that the first assembly language program is implementable on the second processor, wherein the ratio is 2 or a positive integer more than 2.

Abstract: Simulate and calibrate a process by generating a modular representation of a process using modules and variables, each module representing a portion of the process, each variable representing an adjustable parameter of the process. One or more variables are set to specific values. Source code is generated to implement the process according to the modular representation, the code being generated without implementing portions of the process that are not executable when the one or more variables are set to the specific values. The source code is compiled into a machine code and executed to implement the process.

Abstract: Emulation systems and method involving invalidating blocks of translated code in emulation of a target system on a host system in are disclosed. One or more blocks of target system code are translated by the host system to produce one or more corresponding blocks of translated code. The host system uses one or more native target system instructions as hints to invalidate or potentially invalidate one or more blocks of translated code. Blocks containing such hints cause the host system to mark some or all of the one or more blocks of translated code as potentially invalid. The potentially invalid blocks may be re-translated immediately. Alternatively, the potentially invalid blocks may be checked to see if the code in these blocks has been modified. If the code has been modified, corresponding blocks of target code may be re-translated.

Abstract: Embodiments of systems, methods, and computer program products may facilitate translation of machine code associated with a first processor for execution on a second processor. Machine code associated with a first processor may be translated into a translated program that includes one or more translation instructions for execution on the second processor. The one or more translation instructions are used exclusively to translate machine code that is associated with a processor other than the second processor. The translated program may be stored in a storage medium where it may be executed using the second processor. Each translation instruction that involves access of the storage medium may be dispatched to one or more translation load-store units that are dedicated exclusively to processing the translation instructions.

Abstract: A system and method for efficiently walking a directed non-cyclic graph of hierarchical data using multiple analysis tools. The graph walking system comprises: a system for binding a plurality of graph observers to a graph, wherein each graph observer is further bound to a set of node patterns and a set of node observers; graph walking logic for systematically walking through nodes within the graph, wherein the graph walking logic can be instructed by a first pruning system not to walk a set of sub-nodes of an encountered node; and a second pruning system that can be instructed by a node observer bound with an associated graph observer to deactivate the associated graph observer until the set of sub-nodes for the encountered node has been walked. The first pruning system will cause the set of sub-nodes not to be walked only if all of the plurality of graph observers have been deactivated.

Abstract: The invention relates to managing registers during a binary translation mode in a virtual computing system. A set of registers is saved to memory before beginning to execute a series of blocks of translated code, and the contents of the set of registers are restored from memory later. A status register is maintained for tracking the status of each register within the set, the status indicating whether the contents are valid and whether the contents are saved in memory. Before the execution of each block, a determination is made as to whether the actions taken within the block relative to the registers are compatible with the current status of the registers. If the actions are not compatible, additional registers are saved to memory or restored from memory, so that the translation block can be executed.