Abstract: A computer binary translator translates at least a segment of a binary representation of a program from a first instruction set architecture to a second instruction set architecture. A sequence of side-effects in the translation differs from a sequence of side-effects in the original. The translation distinguishes memory loads that are believed to be directed to well-behaved memory from memory loads that are believed to be directed to non-well-behaved memory device(s). Instruction execution circuitry identifies a memory reference that has a side-effect that has been reordered by translation, the memory reference having been believed at translation time to be directed to well-behaved memory but at execution it is found that the reference cannot be guaranteed to be well-behaved. The instruction execution circuitry identifies whether the difference in side-effect order may have a material effect on the execution of the program. A roll-back program state is established, and execution of the original code resumes.

Abstract: To improve computer performance, problems of emulation such as WAR hazard, uneven utilization of machine resources, unnecessary dependencies, wasted hardware resources and data buffer pollution, are alleviated by responding to dynamic execution information, such as branch prediction, register usage, overflow, a history of branch predictions of groups of branches combined, and a history of register usage for: dynamically modifying instruction parameters of an emulation sequence of instructions; reordering emulated instructions; and adding or changing the dynamic execution information.

Abstract: In an embodiment, a method includes receiving a binary of a program code. The binary is based on a first instruction set architecture. The method also includes translating the binary, wherein the translated binary is based on a combination of the first instruction set architecture and a second instruction set architecture.

Abstract: Techniques are described for emulating an instruction processor for use during the development of a computer system. Specifically, the techniques describe an emulated instruction processor that accurately and efficiently emulates an instruction processor having separate interfaces to fetch op-codes and operands. Further, the emulated instruction processor may provide detection of errors associated with the separate interfaces. By making use of the techniques described herein, detailed information relating to errors associated with the memory architecture may be gathered for use in verifying components within the memory architecture, such as first and second-level caches.

Abstract: A method and system for emulating instructions of legacy microprocessors which execute a compiled high-ordered language, such as C/C++, in which the compiled code is structured such that data and instructions segments are segregated. In order to improve the real-time performance of the system, legacy instructions are directly mapped to equivalent instructions of the host processor where possible. Additional techniques may optionally be employed to further increase the real-time performance of the system. By utilizing the direct mapping of the legacy instructions to host instructions, the emulation system in accordance with the present invention provides increased real-time performance for relatively modern RISC microprocessors.

Abstract: A system, method, and computer program product for estimating the function point count of a software application or portfolio. Strata are defined, and random samples are chosen for a function point count. Results are analyzed and quantified, and a confidence interval is determined to qualify the accuracy of the estimate.

Abstract: Method and apparatus for providing a user interface application programming interface (API) for providing extended access to the database by third-party and user software products. In accordance with one embodiment, a method for accessing a business database includes instantiating a company object as an instance of a company class conforming to a component object model standard, setting a server property of the company object to a database server name, setting a company database name property of the company object to the name of a company, setting a user name property of the company object to the name of a user, setting a password property of the company object to a password of the user, setting a language property of the company object to a desired language of the user; and invoking a connect method within the company object, the connect method opening a software connection to a database identified by the company database name property.

Abstract: The invention is a method for allowing Java objects to communicate with .Net Remoting objects, with a first step of receiving metadata information from a .Net Remoting server on a Java client. Then, Java proxies are generated from said metadata information, using a Java development tool, with the Java proxies generated by a one-to-one mapping of .Net classes to Java classes. Finally, the Java proxies are implemented on the Java client, with the method provided solely in Java. Therefore, the Java client does not require any .Net components. The method can also be used to allow .Net Remoting objects to communicate with Java objects in a similar manner.

Abstract: A program storage medium storing an emulation system for performing dynamic real time translation of first program code written for the first programmable machine into second program code (target code) for running on a second programmable machine employing run time generation of an intermediate representation of the first program code. Upon first encountering a given portion of program code, only the target code necessary to execute that portion of program code under a prevailing set of entry conditions is initially generated and stored. When the same portion of program code is again encountered, a determination is made as to whether intermediate representation corresponding to a second subsequent set of conditions has been generated. If not, the target code necessary to execute the same portion of program code under that second set of conditions is generated.

Abstract: Interoperability of a first framework or platform (e.g., COM) and a second different framework or platform (e.g., .NET) is provided via an attribute mechanism. The attribute mechanism is provided in a non-COM based platform (e.g., .NET) to expose classes to COM. In this manner, a compiler (e.g., the .NET compiler) creates class and events interfaces and adds attributes to the class and interfaces as appropriate for correct interoperability and marshaling. By adding this attribute mechanism to a class in .NET, the .NET compiler is able to use the class declarations (such as public methods, properties, and events) to automatically generate a class interface and an events interface, including appropriate dispatch IDs and GUIDs. Validation is performed on the class being mapped to provide an indication, such as an error message or warning, to the user that the underlying framework marshaling layer cannot marshal certain data types as desired or expected.

Abstract: A method and system for instrumenting testcase execution processing of a hardware description language (HDL) model using a simulation control program. In accordance with the method of the present invention, a set name application program interface (API) entry point is called wherein the set name API entry point includes program instructions for naming a simulation control program in association with testcase execution of the HDL model. A create event API entry point is called, wherein the create event API entry point includes an event identifier input parameter which identifies a testcase execution event with respect to the named simulation control program. In response to executing a testcase simulation cycle, signal values are retrieved from the HDL model into an instrumentation code block, wherein the instrumentation code block includes program instructions for processing the retrieved signals to detect whether the testcase execution event has occurred during the testcase simulation cycle.

Abstract: A region on a memory device may be provided, where the region is protected from direct access by the operating system without the use of a hardware controller. Access may be provided through firmware with the use of a virtual machine manager. The system may be used to provide a software controlled RAID without the use of a hardware controller.

Abstract: A combination of a first programmable machine and an emulation system operable to perform dynamic real time translation of first program code written for the first programmable machine into second program code (target code) for running on a second programmable machine employing run time generation of an intermediate representation of the first program code. Upon first encountering a given portion of program code, only the target code necessary to execute that portion of program code under a prevailing set of entry conditions is initially generated and stored. When the same portion of program code is again encountered, a determination is made as to whether intermediate representation corresponding to a second subsequent set of conditions has been generated. If not, the target code necessary to execute the same portion of program code under that second set of conditions is generated.

Abstract: A method of dynamic real time translation of first program code written for a first programmable machine into second program code (target code) for running on a second programmable machine employing run time generation of an intermediate representation of the first program code. Upon first encountering a given portion of program code, only the target code necessary to execute that portion of program code under a prevailing set of entry conditions is initially generated and stored. When the same portion of program code is again encountered, a determination is made as to whether intermediate representation corresponding to a second subsequent set of conditions has been generated. If not, the target code necessary to execute the same portion of program code under that second set of conditions is generated.

Abstract: A threaded interpreter executes a program having a series of program instructions stored in a memory. For the execution of a program instruction the threaded interpreter includes a preparatory unit for executing a plurality of preparatory steps making th program instruction available in the threaded interpreter, and an execution unit with one or more machine instructions emulating the program instruction. The threaded interpreter is designed such that during the execution on an instruction-level parallel processor of the series of program instructions. Machine instructions implement a first one of the preparatory steps for execution in parallel with machine instructions implementing a second one of the preparatory steps for respective ones of the series of program instructions.

Abstract: A simulation control program receives a hardware description language (HDL) model including design entities and count event registers. Each count event registers is associated with a respective instance of an event. The count event registers include first and second registers for counting occurrences of a same replicated event generated within different instances of a same design entity having a same hierarchical level within the HDL model. The simulation control program also receives a correlation data structure indicating which count event registers are associated with instances of the same replicated event. During simulation processing, each of the count event registers maintains a respective count value representing a number of times an associated event instance occurs. The simulation control program sums count values of the first and second count event registers in accordance with the correlation data structure and outputs a count event data packet containing the aggregate count value.

Abstract: A method and apparatus for managing the configuration of a computing arrangement having a host operating system and an emulator operating system includes establishing host operating system interfaces to computing arrangement components. The computing arrangement is scanned, using the host operating system interfaces, to determine configuration information about computing arrangement components reserved for use by the emulator operating system. At least a portion of the scanned configuration information is communicated to the emulator operating system.

Abstract: A method is used for generating a system protocol for control and/or monitoring equipment for one or more machines and/or processes. The equipment comprises a number of modules which can communicate with each other via a serial digital connection in accordance with said system protocol. A first memory location is fed with first data concerning a base protocol and is also supplied with second data concerning one or more additional protocols which indicate possible basic functions for the mutual relationship of the modules in the intercommunication. A second memory location receives third data concerning a base protocol and can also be supplied with fourth data concerning one or more additional protocols which indicate desired basic functions for the mutual relationship of the modules in the intercommunication. The system protocol is based on first, second, third and fourth data in said first and second memory locations.

Abstract: A method and apparatus for emulating a high-precision, high-accuracy clock. In one embodiment, two clocks are used in the emulation. The first clock has precision greater than precision of the second clock and accuracy less than accuracy of the second clock. A checkpoint time relative to elapsed cycles of the second clock and a checkpoint cycle count of cycles of the first clock are periodically stored relative to a checkpoint period that lasts for a selected number of cycles of the second clock. A reference cycle rate of the first clock is calculated relative to the cycle rate of the second clock. The current time is determined as a function of the checkpoint time, a number of cycles of the first clock elapsed since storing the most recent checkpoint cycle count, and the reference cycle rate of the first clock.

Abstract: This invention is a method of complex cache memory analysis and synthesis. This invention proceeds in the normal fashion of writing a program and simulating it, but makes use of a closed loop design approach to completing the analysis-synthesis process. A program behavior analysis tool PBAT is integrated as part of an otherwise conventional program development tool. The PBAT offers a single environment where code development, simulator trace capture, and cache analysis take place. The cache analysis tool of PBAT is designed to match the current cache design of the processor and to identify any weakness in the current design or special features that need to be added. Code adjustments are passed back to the assembler and linker and in successive simulations using the integrated PBAT tool resulting in code that better fits a specific cache design.

Abstract: A core file derived from an application crash is created. The application belongs to a source platform and is run on a target platform. The application is emulated on the target platform. In response to the crash occurring, detecting whether the crash corresponds to the failure of a process corresponding to the emulated application. The crash process is mediated by intercepting information relating to the failure of the emulated application and writing a core file corresponding to the failure of the emulated application running on the source platform. A dynamic binary translator performs the steps and debugs an emulated application as if it had crashed and dumped a core file on its native platform.

Abstract: Functions of a programmable logic controller are located in physically separable units. These physically separable units include a program execution device, or control device, whose function is limited to sequencing through the user logic program and a communication/programming device, which provides the programmability function. The micro controller incorporates a micro processor, RAM, and a re-programmable Flash EPROM in a single package implements the logical core of the program execution device.

Abstract: A virtual memory system implementing the invention provides concurrent access to translations for virtual addresses from multiple address spaces. One embodiment of the invention is implemented in a virtual computer system, in which a virtual machine monitor supports a virtual machine. In this embodiment, the invention provides concurrent access to translations for virtual addresses from the respective address spaces of both the virtual machine monitor and the virtual machine. Multiple page tables contain the translations for the multiple address spaces. Information about an operating state of the computer system, as well as an address space identifier, are used to determine whether, and under what circumstances, an attempted memory access is permissible. If the attempted memory access is permissible, the address space identifier is also used to determine which of the multiple page tables contains the translation for the attempted memory access.

Abstract: Emulation of a guest computer architecture on a host system of another computer architecture. Legacy instructions are translated into translated instructions. If the particular legacy instruction is an operand-setting instruction for storing a value of a precedent operand, a corresponding flag is set when the value of the precedent operand has not been determined. If the particular legacy instruction is an operand-using instruction for using the precedent operand, a check is made to determine if the corresponding flag is set.

Abstract: An emulation system, computer program product, and method for emulating the execution of a target program comprising instructions of an instruction set of a target computer on a host computer having a different instruction set operate by performing a static translation of the instructions of the target program into a series of instructions of an intermediate instruction set, the intermediate instruction set being optimized for interpretation on the host computer, and then executing the series of instructions of the intermediate instruction set by interpretation on the host computer.

Abstract: A computer is disclosed. The computer has a general register file of registers, a RISC instruction decoder, and a CISC instruction decoder. The RISC instruction decoder is exposed for execution of user-state programs in a RISC instruction set, being an instruction set having fixed-length instructions and a load/store/operate organization. The hardware CISC instruction decoder is exposed for execution by user-state programs in a CISC instruction set, being an instruction set with variable-length instructions and many instructions having multiple side-effects. The CISC decoder is designed to decode a portion of an instruction set for the computer, and to deliver the decoded instructions to an instruction execution pipeline designed to execute the output of both the RISC instruction decoder and the CISC instruction decoder. A software emulator is programmed to implement a remainder of the instruction set.

Abstract: In order to reduce the traffic over the communication bus between the host processing unit and an emulator server unit during the test of a target processing unit, the commands are divided into groups of test commands. A group of commands is transferred to the emulator server unit and stored in a memory unit of the emulator server unit. The emulator server unit then applies each command of the group of commands to a target processing unit. The resultant data generated as a result of the application of each command is stored in the emulator server unit. When all the commands of the group of commands have been executed by the target processing unit and the resultant data stored in the emulator server unit, the resultant data is transferred to the host processing unit in a single communication bus access.

Abstract: Selectively emulating sequential consistency in software improves efficiency in a multiprocessing computing environment. A writing CPU uses a high priority inter-processor interrupt to force each CPU in the system to execute a memory barrier. This step invalidates old data in the system. Each CPU that has executed a memory barrier instruction registers completion and sends an indicator to a memory location to indicate completion of the memory barrier instruction. Prior to updating the data, the writing CPU must check the register to ensure completion of the memory barrier execution by each CPU. The register may be in the form of an array, a bitmask, or a combining tree, or a comparable structure. This step ensures that all invalidates are removed from the system and that deadlock between two competing CPUs is avoided. Following validation that each CPU has executed the memory barrier instruction, the writing CPU may update the pointer to the data structure.

Abstract: A method for use by a host microprocessor which translates sequences of instructions from a target instruction set for a target processor to sequences of instructions for the host microprocessor including the steps of beginning execution of a speculative sequence of target instructions by committing state of the target processor and storing memory stores previously generated by execution at a point in the execution of instructions at which state of the target processor is known, executing the speculative sequence of host instructions until another point in the execution of target instructions at which state of the target processor is known, rolling back to last committed state of the target processor and discarding the memory stores generated by the speculative sequence of host instructions if execution fails, and beginning execution of a next sequence of target instructions if execution succeeds.

Abstract: A system and a method are disclosed for dynamically analyzing software, some of whose potentially-important behaviors (such as worm-like behavior) may only be displayed when the software is executed in an environment where it has, or appears to have, access to a production network and/or to the global Internet. The software can be executed in a real or an emulated network environment that includes a monitoring component and an emulation component. The monitoring component serves to capture and/or record the behaviors displayed by the software and/or other components of the system, and the emulation component gives the software being analyzed the impression that it is executing with access to a production network and/or to the global Internet. The software being analyzed is effectively confined to the analysis network environment, and cannot in fact read information from, or alter any information on, any production network or the global Internet.

Abstract: A method for creating a second file system on a device implementing a first file system is provided. One or more first files are selected from a set of files. The files comprise one or more characteristics particular to the second file system. One or more ancestors of the first files are selected automatically. The ancestors comprise one or more characteristics particular to the second file system. Based on the first files and the ancestors, data is generated to emulate one or more of the first files and the ancestors (and/or characteristics of one or more of the first files and the ancestors) that the first file system does not support. A file system comprising the first files, ancestors, and the data is generated.

Abstract: A method and system for dynamically linked emulation with a mix of target debuggers on a host computer wherein a debugger for each processor on the target system connects to a target interface for that kind of processor. That target interface then communicates with an emulator dynamic loader on the host computer connected to an emulator. The target interface communicates with the dynamic loader on the host computer to determine if there is support for the desired kind on the emulator. If not a target interface is loaded to the emulator and connected to the already running software on the host. A connection to this target interface software on the emulator is then provided to the host computer.

Abstract: In an autonomous cooperative control system a job description of job steps is drafted in a scripting language and compared to corresponding machine steps associated with each independently controlled machine also drafted in the same scripting language for simple comparison and generation of sub-bids for further bidding. The machine steps generated for each ACU provides a vocabulary for the job description language which may be further simplified by hiding lower level machine steps in the ACUs to be activated only upon a matching with a job step. The ACUs may select between connected and unconnected messaging based on historical communication patterns to reduce network traffic.

Abstract: A system and method for dynamically patching code. In one embodiment, a method includes intercepting original program instructions during execution of the program using a software interface, determining whether associated instructions have been cached in a code cache of the software interface and, if so, executing the cached instructions from the code cache, if associated instructions have not been cached, determining if the original program instructions require unavailable hardware functionality, and dynamically replacing the original program instructions with replacement instructions that do not require unavailable hardware functionality if it is determined that the original program instructions require unavailable hardware functionality, the dynamic replacing including fetching replacing instructions, storing the replacement instructions in the code cache, and executing the replacement instructions from the code cache.

Abstract: Initially, “libraying” text is inserted on all scripts executed on the computer, allowing administrators to discern at a glance every script that has been executed. Furthermore, administrators can easily ascertain the results of all automatically run programs (such as overnight batch jobs) by looking in a common location rather than all over the computer. All scripts installed on a computer system are required to have the ability to generate uniform output. This output includes the script name, the time it was run, the user name and the script execution results. When a script is executed, it will write this detailed output into a predefined directory. There, a file is generated which lists all the parameters associated with the script execution. The parameters are then available for future review by administrators. Additionally, an executed script writes a summary output to a common file. This file provides a single point of reference and further provides a summary description for all activities.

Abstract: A method and a apparatus for testing a software emulator while executing the software emulator on a target machine architecture are disclosed. The method may include the steps of executing a test program on a target machine architecture, with a test program producing a first output, executing an emulator on the target machine architecture, and the emulator executing the test program under emulation, with the test program producing a second output.

Abstract: A method for determining a process to use for converting instructions in a target instruction set to instructions in a host instructions set including the steps of executing code morphing software including an interpreter and a translator to generate host instructions from target instructions, detecting at intervals whether the interpreter or the translator is executing, increasing a count if the interpreter is executing and decreasing the count if the translator is executing, and changing from interpreting to translating a sequence of target instructions when the count reaches a selected maximum.

Abstract: A method for use by a host microprocessor which translates sequences of instructions from a target instruction set for a target processor to sequences of instructions for the host microprocessor including the steps of beginning execution of a speculative sequence of target instructions by committing state of the target processor and storing memory stores previously generated by execution at a point in the execution of instructions at which state of the target processor is known, executing the speculative sequence of host instructions until another point in the execution of target instructions at which state of the target processor is known, rolling back to last committed state of the target processor and discarding the memory stores generated by the speculative sequence of host instructions if execution fails, and beginning execution of a next sequence of target instructions if execution succeeds.

Abstract: The present invention relates to a system and method for emulating a greater range of behavior of a peripheral device connected to a host device or host computer than was available in the prior art. The emulation of a greater range of activity of the peripheral device provides an opportunity to more fully test the interaction of a host device with the emulated peripheral device. More specifically, the present invention preferably adds control data line and power data line connections to user data line connections between the host device and an intelligent emulator so that variations in control settings and power levels may be exercised in addition to manipulation of transmissions along a user data line, thereby more fully exercising host device interaction with an emulated device.

Abstract: In a computer which translates instructions from a target instruction set to a host instruction set, a method for determining validity of a translation of a target instruction linked to an earlier translation including the steps of testing a memory address of a target instruction to be executed against a copy of the memory address of the target instruction from which a translation of the target instruction was made, executing the translation if the addresses compare, and generating an exception if the addresses do not compare.

Abstract: A high precision floating point emulator and associated method for emulating subject program code on a target machine where the subject machine base operands possess a different precision than the target machine. The high precision floating point emulator is provided for the emulation of subject program code instructions having a higher precision than that supported by the target machine architecture by utilizing intermediate calculations having values with a higher precision than that supported by the target machine.

Abstract: The present invention is software that turns an inexpensive, standard personal computer (PC) into a platform for running embedded software. The present invention consists of two software components: a compiler assist component and a runtime component. The compiler assist component works in conjunction with a standard PC compiler to compile an embedded system application to run on a conventional PC. The runtime component executes on the PC and works in conjunction with the standard operating system drivers to allow an emulated system to communicate with real hardware connected to the PC or to virtual hardware that is simulated on the PC.

Abstract: A packet core network (PCN) includes a plurality of interconnected routers. An emulator is provided along with at least one of the routers and operates to control transmission of Internet Protocol (IP) datagrams there through in order to simulate the effects of having one of the non-radio inter-router connections fictionally comprise a wireless cellular radio link. The emulator responds to user input specifying wireless cellular radio link conditions to determine a time delay to be applied by the router against the transmission of each datagram. This time delay is set roughly equivalent to the delay introduced, under the user specified wireless cellular radio link conditions, by emulated radio link operation to erase uncorrectable frames to obtain retransmission. The emulator further sets a data rate for router handling of datagrams based on the user input to simulate congestion on the radio link due to the presence of other, competing users.

Abstract: The present invention includes a native language verification method for verifying native language information associated with an emulation class. Verification information associated with native language code is obtained. The native language code is referred to by an emulation language class. The legitimacy of the verification information is examined to confirm the native language is uncorrupted.

Abstract: A data processor includes a hardware translator converting non-native code into a native code to a processor, a software translator converting non-native code into a native code to the processor by software, and a software interpreter sequentially interpreting a code that is non-native to the processor, and executing the interpreted code using a native code of the processor. The data processor includes a circuit selecting the hardware translator, software translator or software interpreter according to a predetermined criterion for operation.

Abstract: An improved method and apparatus for performing program code conversion is provided and, more particularly, for generating improved intermediate representations for use in program code conversion. During program code conversion, a partial dead code elimination optimization technique is implemented to identify partially dead register definitions within a block of program code being translated. The partial dead code elimination is an optimization to the intermediate representation in the form of code motion for blocks of program code ending in non-computed branches or computed jumps, where target code for all dead child nodes of a partially dead register definition is prevented from being generated and target code for partially dead child nodes of a partially dead register definition is delayed from being generated until after target code is generated for all fully live child nodes for the partially dead register definition.

Abstract: An improved method and apparatus for performing program code conversion is provided and, more particularly, for generating improved intermediate representations for use in program code conversion. During program code conversion, a partial dead code elimination optimization technique is implemented to identify partially dead register definitions within a block of program code being translated. The partial dead code elimination is an optimization to the intermediate representation in the form of code motion for blocks of program code ending in non-computed branches or computed jumps, where target code for all dead child nodes of a partially dead register definition is prevented from being generated and target code for partially dead child nodes of a partially dead register definition is delayed from being generated until after target code is generated for all fully live child nodes for the partially dead register definition.

Abstract: A method and apparatus for verifying program code conversion performed by an emulator. A first emulator configured in a same-to-same (X-X) mode converts subject code into target code for execution by a subject processor. Execution of the subject code natively by the subject processor is compared against execution through the first emulator, to verify that program code conversion. Optionally, the first emulator is then used to incrementally validate program code conversion (i.e. optimisation and/or translation) performed by a second emulator, such as a this-to-that (X-Y) mode emulator running on a target processor.

Abstract: An improved architecture for a program code conversion apparatus and method for generating intermediate representations for program code conversion. The program code conversion apparatus determines which types of IR nodes to generate in an intermediate representation of subject code to be translated. Depending upon the particular subject and target computing environments involved in the conversion, the program code conversion apparatus utilizes either base nodes, complex nodes, polymorphic nodes, and architecture specific nodes, or some combination thereof, in generating the intermediate representation.

Abstract: The first model described in a software description language is converted into the second model described in a hardware description language without considering whether a plurality of parallel procedures for writing with respect to the same shared variable are contained in the first model. It is detected whether a plurality of parallel processes corresponding to the plurality of parallel procedures for writing with respect to the same shared variable exist in the second model obtained in this manner. A value solving process is generated, in which a pair of a data signal and an assignment timing signal are input from each process of all or some of the detected parallel processes, and a signal of the data signals which corresponds to a process in which the assignment timing signal has changed is output to a signal holding the value of the shared variable.