Abstract: A mechanism is described that predicts the usefulness of a prefetching instruction during the instruction's decode cycle. Prefetching instructions that are predicted as useful (prefetch useful data) are sent to an execution unit of the processor for execution, while instructions that are predicted as not useful are discarded. The prediction regarding the usefulness of a prefetching instructions is performed utilizing a branch prediction mask contained in the branch history mechanism. This mask is compared to information contained in the prefetching instruction that records the branch path between the prefetching instruction and actual use of the data. Both instructions and data can be prefetched using this mechanism.

Abstract: Described is a mechanism that preserves the state of computer system shared resources and/or settings, and ensures that changes thereto are reverted when an application exits. A shared resource change bubble logically surrounds application code that causes system resource and/or setting data to change. The bubble preserves existing data before it gets changed, and restores the data when the application program code exits. In one implementation, the bubble is implemented as a library loaded by the application. In an alternative implementation, the bubble is run in a separate process, whereby the bubble can restore changed data even if the application program crashes. In another implementation, a bubble is automatically run for any application that the user has specified needs a bubble. Multiple settings and states may be preserved in a bubble for multiple applications, allowing changes to be undone and reapplied per application, e.g., whenever focus changes.

Abstract: Vectorizing misaligned references in compiled code for SIMD architectures that support only aligned loads and stores is presented. In the framework presented herein, a loop is first simdized as if the memory unit imposes no alignment constraints. The compiler then inserts data reorganization operations to satisfy the actual alignment requirement of the hardware. Finally, the code generation algorithm generates SIMD codes based on the data reorganization graph, addressing realistic issues such as runtime alignments, unknown loop bounds, residue iteration counts, and multiple statements with arbitrary alignment combinations. Beyond generating a valid simdization, a preferred embodiment further improves the quality of the generated codes. Four stream-shift placement policies are disclosed, which minimize the number of data reorganization generated by the alignment handling.

Abstract: A method of reordering a sequence of code for processing by a target data processor in order to reduce an execution time for said code on said target data processor is disclosed. The method comprises the steps of: in response to a request to execute said sequence of code, loading said sequence of code into a volatile data store associated with said target data processor; analyzing said sequence of code in relation to properties of said target data processor; identifying interlocks within said sequence of code when executing on said target data processor, in which a portion of code would be stalled while waiting for an earlier portion to complete; reordering said sequence of code to remove at least some of said interlocks; and executing said reordered sequence of code; wherein said steps of analyzing, identifying, reordering and executing are performed by said target data processor.

Abstract: One embodiment disclosed relates to a method of compiling a program to be executed on a target microprocessor with multiple execution units of a same type. The method includes selecting one of the execution units for testing and scheduling the parallel execution of program code and diagnostics code. The diagnostic code is scheduled to be executed on the selected execution unit. The program code is scheduled to be executed on remaining execution units of the same type.

Abstract: A compilation technique for computer programs forms a data flow graph of vertices which are analysed to form clusters C for parallel execution where those clusters are added to up to the point at which arbitrary selection between further vertices C, D to be added must be made. This data flow graph with these small clusters is then scheduled such that the clusters do not overlap with other clusters or with vertices outside of clusters. This starting point scheduled data flow graph is then subject to iterative processing whereby a window of timestamps is analysed to see if a candidate cluster formed by the parallel execution of the vertices within that window will result in faster execution whilst avoiding exceeding architectural constraints, such as register occupancy. If the rescheduled vertices do improve performance without exceeding architectural constraints, then this new schedule is adopted and the following vertices are subject to an adjustment in their timestamps to account for this.

Abstract: A system and method is provided for vectorizing misaligned references in compiled code for SIMD architectures that support only aligned loads and stores. In this framework, a loop is first simdized as if the memory unit imposes no alignment constraints. The compiler then inserts data reorganization operations to satisfy the actual alignment requirements of the hardware. Finally, the code generation algorithm generates SIMD codes based on the data reorganization graph, addressing realistic issues such as runtime alignments, unknown loop bounds, residual iteration counts, and multiple statements with arbitrary alignment combinations. Loop peeling is used to reduce the computational overhead associated with misaligned data. A loop prologue and epilogue are peeled from individual iterations in the simdized loop, and vector-splicing instructions are applied to the peeled iterations, while the steady-state loop body incurs no additional computational overhead.

Abstract: Programs having a given instruction-set architecture are executed on a multiprocessor system comprising a plurality of processors, for example of a VLIW type, each of said processors being able to execute, at each processing cycle, a respective maximum number of instructions. The instructions are compiled as instruction words of given length executable on a first processor. At least some of the instruction words of given length are converted into modified-instruction words executable on a second processor. The operation of modifying comprises in turn at least one operation chosen in the group consisting of: splitting the instruction words into modified-instruction words; and entering no-operation instructions in the modified-instruction words.

Abstract: Methods and apparatus to insert prefetch instructions based on garbage collector analysis and compiler analysis are disclosed. In an example method, one or more batches of samples associated with cache misses from a performance monitoring unit in a processor system are received. One or more samples from the one or more batches of samples based on delinquent information are selected. A performance impact indicator associated with the one or more samples is generated. Based on the performance indicator, at least one of a garbage collector analysis and a compiler analysis is initiated to identify one or more delinquent paths. Based on the at least one of the garbage collector analysis and the compiler analysis, one or more prefetch points to insert prefetch instructions are identified.

Abstract: A compiler apparatus is capable of generating instruction sequences causing a processor to operate with lower power consumption. The compiler apparatus translates a source program into a machine language program for a processor including execution units which can execute instructions in parallel, and including instruction issue units which issue the instructions executed, respectively, by the execution units. The compiler apparatus includes a parser unit operable to parse the source program, an intermediate code conversion unit operable to convert the parsed source program into intermediate codes, an optimization unit operable to optimize the intermediate codes to reduce a hamming distance between instructions from the same instruction issue unit in consecutive instruction cycles, and includes a code generation unit operable to convert the optimized intermediate codes into machine language instructions.

Abstract: Compiler device optimizes a program by changing an order of executing instructions.

Abstract: A method for increasing the speed of execution by a processor including the steps of selecting a sequence of instructions to optimize, optimizing the sequence of instructions, creating a duplicate of instructions from the sequence of instructions which has been selected to optimize, executing the optimized sequence of instructions, and responding to an error during the execution of the optimized sequence of instructions by rolling back to the duplicate of instructions from the sequence of instructions.

Abstract: Methods and apparatus to optimize computer instructions are disclosed. An example method includes receiving a set of computer instructions, determining a first location of a first computer instruction that indicates the end of a critical section in the set of computer instructions, and modifying the execution order of the set of computer instructions to cause the first computer instruction to be executed earlier than the first location. In an example implementation, the disclosed methods and apparatus may be used to optimize the performance of computer instructions executing on multi-processing computer systems.

Abstract: Methods and apparatus for reducing memory latency in a software application are disclosed. A disclosed system uses one or more helper threads to prefetch variables for a main thread to reduce performance bottlenecks due to memory latency and/or a cache miss. A performance analysis tool is used to profile the software application's resource usage and identifies areas in the software application experiencing performance bottlenecks. Compiler-runtime instructions are generated into the software application to create and manage the helper thread. The helper thread prefetches data in the identified areas of the software application experiencing performance bottlenecks. A counting mechanism is inserted into the helper thread and a counting mechanism is inserted into the main thread to coordinate the execution of the helper thread with the main thread and to help ensure the prefetched data is not removed from the cache before the main thread is able to take advantage of the prefetched data.

Abstract: An efficient method for software-pipelining (SWP) of loops to translate programs, from higher level languages into equivalent object or machine language code for execution on a computer. In one example embodiment, this is accomplished by spilling and filling multiple computed values, in a register, that are live across multiple stages in a software-pipelined loop, using multiple rotating stack memory locations to reduce compiler-time of SWP, and complexity of the implemented SWP.

Abstract: An apparatus, program product and method utilize a heuristic-based algorithm such as simulated annealing to order program code segments in a computer memory to provide improved computer performance in terms of memory access, e.g., by minimizing cache misses or other memory-related performance penalties that may be present in a multi-level memory architecture. Program code is ordered in a computer memory by selecting an ordering from among a plurality of orderings for a plurality of program code segments using a heuristic algorithm, and ordering the plurality of program code segments in a memory of a computer using the selected ordering.

Abstract: A method and apparatus for creating a compressed trace for a program, wherein events are compressed separately to provide improved compression and tracing. A sequence of events for a program is selected, and a sequence of values is then determined for each of the selected events occurring during an execution of the program. Each sequence of values is then compressed to generate a compressed sequence of values for each event. These values are then ordered in accordance with information stored in selected events (such as for example, branch events), where the ordered values correspond to the trace.

Abstract: A method and apparatus are provided for repacking of memory data. For at least one embodiment, data for a plurality of store instructions in a source code program is loaded from memory into the appropriate sub-location of a proxy storage location. The packed data is then written with a single instruction from the proxy storage location into contiguous memory locations.

Abstract: In accordance with a plurality of processing requests, a SAM chip generates IC card entity data including job execution order data showing an order of execution of a plurality of jobs forming processing in accordance with a processing request and status data showing a state of progress of execution of said plurality of jobs for each of said processing requests. Further, the SAM chip selects one entity data from said plurality of entity data, selects and executes the job to be executed next based on the status data and processing order data of said selected entity data, and updates the status data in accordance with execution of said job.

Abstract: A method for processing data in a data processing system (1) which includes a number of data processing units (2), and operator and observation units (4), which are interconnected by way of a data transmission unit (6), whereby a respective data processing program (8) with corresponding function modules (FB1 to FBn) and data modules (DB 1 to DBn) is implemented in the data processing units (2). At least one identifier (K, KE, KI) for the function modules and data modules is stored in a respective conversion table (10) belonging to each data processing unit (2). When an external data processing unit (2) accesses a data module (DB1 to DBn) and/or a function module (FB1 to FBn) of another data processing unit (2), a conversion table (10) mediates by using an external identifier (KE) that characterizes the access and verifies whether a matching internal identifier (KI) is stored for the particular external identifier (KE).

Abstract: One embodiment of the present invention provides a system that generates code to perform anticipatory prefetching for data references. During operation, the system receives code to be executed on a computer system. Next, the system analyzes the code to identify data references to be prefetched. This analysis can involve: using a two-phase marking process in which blocks that are certain to execute are considered before other blocks; and analyzing complex array subscripts. Next, the system inserts prefetch instructions into the code in advance of the identified data references. This insertion can involve: dealing with non-constant or unknown stride values; moving prefetch instructions into preceding basic blocks; and issuing multiple prefetches for the same data reference.

Abstract: An apparatus and method for distributing work on a doubly linked list to a plurality of worker threads are provided. With the apparatus and method, an initial thread obtains the list lock for the linked list and inserts a marker element at the beginning of the linked list. Elements in the linked list that are before the marker element in the linked list are considered work that has been assigned or work that has been completed. Elements of the linked list that are after the marker element in the linked list are work to be done. The initial thread spawns worker threads to perform the work on the linked list and passes the address of the marker element to each of the worker threads. Each worker thread then operates independently to perform work on the linked list based on the current position of the marker element in the linked list.

Abstract: A method for modifying serial dependencies in a procedure includes a step of building a graph representation of the procedure. The graph representation has an origin as well as a unique position, relative to the origin, for each memory operation in the procedure. Each memory operation in the representation is designated with a location type. Each of these location types are based on one or more characteristics of the corresponding memory operation that are sufficient to notify the compiler that the memory operation accesses a distinct or disjoint memory location. Memory operations having the same location type as subsequent memory operations are identified. When the graph representation does not include additional memory operations of the same location type between pairs of such memory operations, the subsequent memory operation is moved to a position in the intermediate representation that is closer to the origin.

Abstract: Techniques and a set of heuristics are described to perform allocation of the special instruction memory where indirect very long instruction words (VLIW's) are stored for the ManArray family of multiprocessor digital signal processors (DSP). This approach substantially reduces the cost of pre-initializing the contents of VLIWs.

Abstract: Method and apparatus for simultaneous optimization of the compiler to generate codes that may be compatible and acceptable for two or more different processors without potentially sacrificing the performance on any processors is provided. In particular, the rules of instructions scheduling for the machines of interest of different processors are abstracted. From the abstractions, a hypothetical machine is generated that is the restrictive or constraining set of the actual machines modeled in the abstraction step. After generating the hypothetical machine, the restricted hypothetical machine is targeted rather than the actual machines modeled in the first step. Thereafter, conflicts, if any are resolved by modeling the performance impact and selecting the less damaging choice.

Abstract: Interlocked floating-point instructions are detected, and a register address referring to and assigning an operand in the interlocked instructions is changed to an odd-number address not assigned as any operation at the time of compiling. Next, an instruction not in any register-dependency relation with the interlocked instructions is detected, and the detected instruction is inserted between instructions interlocked with each other. Thus a program can be executed with an improved efficiency.

Abstract: A data access method in an information system including a plurality of data utilization systems connected to a network N1, and a plurality of data provision systems connected to a network, wherein a data utilization system transmits a request for utilizing data in a data provision system to another data utilization system P2 through the network N1, the data utilization system, upon receipt of the data utilization request, transmits a processing execution request corresponding to the data utilization request to the data provision system through the network N2, the data provision system, upon receipt of the execution request, executes processing corresponding to this execution request and transmits necessary data to the data provision system through the network, and the data provision system receives the data and stores the same.

Abstract: An optimization apparatus (compiler program, method and recording medium) for changing the order of execution of instructions in a program to be optimized includes an exception occasion instruction detection section which detects a first instruction having a possibility to cause an exception, an assurance instruction detection section which detects a second instruction executed prior to the first instruction, the second instruction assuring that no exception of the first instruction occurs, and an execution order control section which changes the position of the first instruction in execution order so that the first instruction is executed before a conditional branch instruction for selectively executing the first instruction and after the second instruction.

Abstract: Methods and apparatus to avoid dynamic micro-architectural penalties in an in-order processor are disclosed. In an example, a compiler inserts decision code into the object code to thereby cause the in-order processor to operate like an out of order processor to operate with respect to at least some memory access instructions. The decision code determines at run time of the object code whether a load instruction is a likely cache hit. Based on that determination, the decision code causes the in-order processor to execute a use instruction at a first time if the load instruction is a likely cache hit, and to execute a copy of the use instruction at a second, later time if the load instruction is not a likely cache hit.

Abstract: This invention relates to a method, system and program product to detect reduction variables in assignment statements in the source code for enabling the parallel execution of program loops. The reduction variables found using the method herein described can be tagged to the respective loops and passed to a compiler through compiler directives for parallelizing the reduction operation, along with the information about each variable's respective associative operator.

Abstract: In a parallel processor system for executing a plurality of threads in parallel to each other by a plurality of thread execution units, the respective thread execution units allow for forking of a slave thread from an individual thread execution unit into another arbitrary thread execution unit. The respective thread execution units are managed in three states, a free state where fork is possible, a busy state where a thread is being executed, and a term state where a thread being terminated and yet to be settled exists. At the time of forking of a new thread, when there exists no thread execution unit at the free state, a thread that the thread execution unit at the term state has is merged into its immediately succeeding slave thread to bring the thread execution unit in question to the free state and conduct forking of a new thread.

Abstract: We disclose a function unit based finite state automata data structure for use in computer program compilers. According to an aspect of an embodiment, the data structure comprises a function unit vector, having no more used bits than there are issue ports for any particular microprocessor, and a plurality of valid template assignments for each function unit vector. In a preferred embodiment, the template assignments are constructed so as to account for dispersal rules associated with the particular microprocessor. Further, the template assignments can be sorted according to priority data.

Abstract: When a branch instruction is decoded by the instruction decoders 409a˜409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the lower PC calculator 405. The lower PC calculator 405 adds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PC 404 and sends the result to the lower PC 404 as the updated lower PC. The upper PC calculator 411 adds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC 403, and a carry that may be received from the lower PC calculator 405, and sends the result to the upper PC 403 as the updated upper PC.

Abstract: Run-time parallelization of loops with static irregular read-write memory access patterns is performed across multiple arrays. More than one element from each array can be read or written during each iteration of the loop.

Abstract: A compiler device includes a conditional-executable-instruction generation unit and a branch instruction insertion unit. The conditional-executable-instruction generation unit generates a conditional executable instruction that is executed when a condition that the conditional executable instruction refers to is satisfied. In the case where there is a section containing a non-executive condition under which no instruction is executed in one cycle or a plurality of cycles in series, the branch instruction insertion unit inserts a conditional branch instruction that refers to the non-executive condition and instructs to branch to a cycle immediately after a last cycle of the section, to after an instruction of a cycle immediately before a start of the section.

Abstract: In some embodiments of the present invention, a method and system are provided in a multiple resource environment for relieving a thermal condition by applying cooling techniques or throttling to lower priority threads.

Abstract: A method and a system for scheduling a software pipelined loop with indirect loads. The system may include a data structure in communication with a processor and a memory. The processor may determine a condition associated with a potential for saturation of the data structure. Accordingly, the processor may provide a number of instructions associated with the software pipelined loop from the memory to a queue of the data structure prior to processing of the instructions by the processor based on the condition associated with a potential for saturation of the data structure.

Abstract: A compiler comprising an integrated instruction scheduler and resource management system is provided. According to an aspect of an embodiment, the resource management system includes a function unit based finite state automata system. Instructions to be compiled are modeled through the function unit based finite state automata system based on their function unit usage, before they are emitted as compiled computer code. We also disclose a function unit based finite state automata data structure and computer implemented methods for making the same.

Abstract: A method and system for optimizing the use of a plurality of processors when compiling a program in a computer system is disclosed. The method and system comprises providing a list of directories and a list of processors. The method and system further includes determining when a directory is available. The method and system includes assigning a directory to a next available processor in an ordered manner to allow the next available processor to compile at least one file within the directory. Finally, the method and system includes ensuring that the maximum number of directories can be processed by assigning a processor thereto. Through the use of the method and system in accordance with the present invention, compile cycle time for large programs is significantly reduced. Accordingly, the dependencies are updated simultaneously with the code changes, thereby allowing for the compiling of the large program with minimal dependency violations.

Abstract: A computer system and method is provided for prioritizing software tests. Software tests are prioritized based on coverage indicators for the software tests and an indication of impacted areas of the software. Each of the coverage indicators indicates which portions of the software are executed for a respective one of the software tests. The portions of the software include at least one of a plurality of blocks. The indication of impacted areas of the software indicates ones of the plurality of blocks that are modified or new with respect to a previous version of the software. A prioritized list of software tests is output. The prioritized list includes at least one test sequence.

Abstract: Method and apparatus for verifying at runtime an invariant property of a data structure. In various example embodiments, code that verifies whether a runtime value of the data structure is consistent with the invariant property is automatically generated in response to an annotation of the data structure in the source code. In executing the program, the runtime value of the data structure is compared to the invariant property in the automatically generated code. If the runtime property is inconsistent with the invariant property, the program branches to exception handler code.

Abstract: One embodiment of the present invention provides a system that facilitates multi-versioning loops to facilitate modulo scheduling. Upon receiving a computer program, the system analyzes the code to locate loops within the program. When a loop is located, the system examines the loop termination condition to determine if it is based on a “not-equal-to” condition that makes it hard to determine beforehand whether the loop will terminate. If the loop termination condition is based on a “not-equal-to” condition, the system creates multiple versions of the loop, at least one of which will terminate and can be modulo scheduled, and at least one of which might be an infinite loop and consequently cannot be modulo scheduled.

Abstract: A system and method for processing a variable looping statement into a constant looping statement to enable loop unrolling. A lower bound and an upper bound of the loop index within the variable looping statement are determined. A constant looping statement is then formed using the lower bound and upper bound to define a range over which the loop index varies within the constant looping statement. The constant looping statement further includes a conditional statement that reflects conditions in the initial expression and/or the exit expression of the variable looping statement. The conditional statement controls execution of the body of the generated constant looping statement, which includes the body from the original variable looping statement. Loop unrolling may then be performed on the generated constant looping statement.

Abstract: Branch prediction circuitry including a bimodal branch history table, a fetch-based branch history table and a selector table is provided. The local branch history table includes a plurality of entries each for storing a prediction value and accessed by selected bits of a branch address. The fetch-based branch history table included a plurality of entries for storing a prediction value and accessed by a pointer generated from selected bits of the branch address and bits from a history register. The selector table includes a plurality of entries each for storing a selection bit and accessed by a pointer generated from selected bits from the branch address and bits from the history register, each selector bit is used for selecting between a prediction value accessed from the local history table and a prediction value accessed from the fetch-based history table.

Abstract: A method of processing a general-purpose, high level language program to determine a hardware representation of the program can include compiling the general-purpose, high level language program to generate a language independent model (105, 110, and 115). The language independent model can be scheduled such that each component is activated when both control and valid data arrive at the component (120). An interface structure specifying a hardware interface through which devices external to the language independent model interact with a physical implementation of the language independent model can be defined and included in the language independent model (200, 300, 400).

Abstract: A system and method for isolating the execution of a plurality of applications. The applications may utilize or share one or more “original” classes. Only one copy of each original class is maintained, regardless of how many applications utilize it. Static fields are extracted from the original classes. A separate copy of the static fields is created for each of the utilizing applications. A static field class which includes instance fields corresponding to the static fields may be created, wherein each instance of the static field class corresponds to one of the utilizing applications. Access methods for the one or more static fields may be created, wherein the access methods are operable to access the corresponding separate copy of the static fields based upon the identity of the utilizing application. A single access methods class may be created for each original class, wherein the single access methods class includes the access methods for accessing the extracted fields from the original class.

Abstract: In some embodiments of the present invention, a method and system are provided in a multiple resource environment for relieving a thermal condition by applying cooling techniques or throttling to lower priority threads.

Abstract: A first type of debugger impact reduction includes removing, from within a loop, an initial conditional breakpoint (“ICB”); extracting a first Boolean expression (“BE_1”) therefrom; setting a special conditional breakpoint (“SCB”) including the BE_1; and reestablishing the ICB if the SCB is satisfied. Optionally, the first type may further include extracting, from code within the loop, a second Boolean expression (“BE_2”); disjunctively including its complement in the SCB; and setting a reset breakpoint at loop exit program positions to remove reset breakpoints and/or the ICB. A second type includes setting the SCB with the complement of BE_1; and removing the ICB when the SCB is satisfied. Optionally, the second type may further include conjunctively including the BE_2 in the SCB; and setting a reset breakpoint to remove reset breakpoints and/or reestablish the ICB. The above may be embodied in a method, a program debugger and an article of manufacture.

Abstract: A method comprising: converting bytecodes into a graph of jop objects to track where jump operations pointed before modification of the bytecodes; adjusting constant pool references from local to global numbers based on the graph; and combining the bytecodes into a bundle.

Abstract: The present invention discloses a method and device for ordering memory operation instructions in an optimizing compiler. for a processor that can potentially enter a stall state if a memory queue is full. The method uses a dependency graph coupled with one or more memory queues. The dependency graph is used to show the dependency relationships between instructions in a program being compiled. After creating the dependency graph, the ready nodes are identified. Dependency graph nodes that correspond to memory operations may have the effect of adding an element to the memory queue or removing one or more elements from the memory queue. The ideal situation is to keep the memory queue as full as possible without exceeding the maximum desirable number of elements, by scheduling memory operations to maximize the parallelism of memory operations while avoiding stalls on the target processor.