Abstract: A machine provides a system and interface to allow domain experts and other users to develop, deploy, and iterate on analytical models. The machine facilitates building, deploying, and/or training analytical models by, e.g., exposing analytical model configuration parameters to a user while abstracting model building and model deployment activities. The machine can also determine resource loads or execution times for various analytical models and can schedule model execution accordingly. The machine also provides a dynamically reconfigurable user interface for controlling the system.

Abstract: A computer-implemented method and computer processing system are provided for coordinated heap contraction. The method includes starting a contraction of a heap responsive to a physical memory use of the heap approaching a limit. The contraction starts from a particular runtime system that was estimated to be slowest for the contraction from among a plurality of runtime systems that use the heap, based on previously determined estimates. The method also includes decreasing the physical memory use of the heap by compacting the heap with only one Garbage Collection (GC) thread, responsive to the contraction of the heap being unable to catch up to the physical memory use.

Abstract: The technology disclosed presents a novel spatial attention model that uses current hidden state information of a decoder long short-term memory (LSTM) to guide attention and to extract spatial image features for use in image captioning. The technology disclosed also presents a novel adaptive attention model for image captioning that mixes visual information from a convolutional neural network (CNN) and linguistic information from an LSTM. At each timestep, the adaptive attention model automatically decides how heavily to rely on the image, as opposed to the linguistic model, to emit the next caption word. The technology disclosed further adds a new auxiliary sentinel gate to an LSTM architecture and produces a sentinel LSTM (Sn-LSTM). The sentinel gate produces a visual sentinel at each timestep, which is an additional representation, derived from the LSTM's memory, of long and short term visual and linguistic information.

Abstract: A method for scheduling a data flow task and an apparatus. The method includes: preprocessing a data flow task to obtain at least one subtask; classifying the subtask into a central processing unit (CPU) task group, a graphics processing unit (GPU) task group, or a to-be-determined task group; allocating the subtask to a working node; when the subtask belongs to the CPU task group, determining that a CPU executes the subtask; when the subtask belongs to the GPU task group, determining that a GPU executes the subtask; or when the subtask belongs to the to-be-determined task group, determining, according to costs of executing the subtask by a CPU and a GPU, a running platform (e.g., the CPU or the GPU) executes the subtask, where the cost includes duration of executing the subtask.

Abstract: A communication control apparatus including an acquisition section that acquires first information related to communication quality of a wireless channel through which target data to be distributed to a terminal apparatus is transmitted to the terminal apparatus, and second information related to data among the target data, the data being accumulated in the terminal apparatus, and a control section that performs control over transmission of the target data to the terminal apparatus on the basis of the first information and the second information.

Abstract: A computer has a secondary storage device with a filesystem for persistent storage of application data, the filesystem having filesystem objects including files, directories, and group objects such as consistency groups. The group objects specify respective groups of the filesystem objects on which certain filesystem group operations act as a unit. The filesystem also has filesystem routines for performing filesystem operations including single-object operations and group operations. A single-object operation acts upon a specified user file or directory independently (e.g., opening or reading from a file), while a group operation acts upon a respective set of filesystem objects grouped together by a specified group object.

Abstract: A computer receives data from a storage device. The computer identifies a state value of the storage device and at least one maintenance task included in the received data. The computer generates a set of instructions for limiting the workload of a storage device executing maintenance tasks. According to the generated instructions, the computer limits the workload placed on the storage device.

Abstract: Concurrent threads may be synchronized at the level of the memory words they access rather than at the level of the lock that protects the execution of critical sections. Each lock may be associated with an array of flags and each flag may indicate ownership of certain memory words. A pessimistic thread may set flags corresponding to memory words it is accessing in the critical section, while an optimistic thread may read the corresponding flag before any memory access to ensure that the flag is not set and that therefore the associated memory word is not being accessed by the other thread. Thus, optimistic threads that do not have conflicts with the pessimistic thread may not have to wait for the pessimistic thread to release the lock before proceeding.

Abstract: Disclosed aspects relate to checkpointing a set of stream computing data with respect to a stream computing environment having a set of windowed stream operators including both a first windowed stream operator and a second windowed stream operator. It may be identified that the first windowed stream operator has a first subset of the set of stream computing data. It may be identified that the second windowed stream operator has the first subset of the set of stream computing data. It may be determined to checkpoint the first subset of the set of stream computing data without a redundant checkpoint related to the first and second windowed stream operators. The set of stream computing data may be checkpointed without the redundant checkpoint of the first subset of the set of stream computing data.

Abstract: A technology is provided for using a program code with a monitoring service in computing service environment. An application programming interface (API) call is prepared at a monitoring service according to one or more API call parameters, using a security data template, to be sent to the program code. The API call having the security data template can be sent from the monitoring service having a dashboard to the program code to query a target resource. A response can be received from the program code as return information from the program code and the target resource using the security data template according to the API call. The response can be displayed as a templated data response in the dashboard of the monitoring service according to a defined template.

Abstract: A method of operating a CPU including a memory for storing a load tracker and a booster and a core for executing the load tracker and the booster includes determining, by the load tracker, whether an idle task is executed in the core, generating, by the load tracker, an event corresponding to a result of the determination, broadcasting, by the load tracker, a generated event to the booster, and setting, by the booster, a QoS minimum value of the core based on the event. The method of operating a CPU may further include registering, by the load tracker, an idle start worker callback and an idle end worker callback in an idle module when the CPU is initialized, and generating, by the load tracker, an idle start worker and an idle end worker when the CPU is initialized.

Abstract: The invention provides a method and apparatus comprising at least one processor; at least one memory including computer program code, at least one memory and the computer program code configured to, with the at least one processor, cause the apparatus to perform identification of music data or other audio metadata played on an iOS device.

Abstract: A processor has functional units that fetch and decode architectural instructions of an architectural instruction set at a first rate, a register that stores a value of an indicator programmable by execution of an architectural instruction of the architectural instruction set, and an execution unit. The execution unit includes a first memory that holds data, a second memory that holds instructions of a program, and a plurality of processing units that execute the program instructions at a second rate to perform operations on data received from the first memory to generate results to be written to the first memory. The instructions are of an instruction set that is distinct from the architectural instruction set. The second rate is the first rate when the indicator is programmed with a first value and the second rate is less than the first rate when the indicator is programmed with a second value.

Abstract: A method for improving performance of a system including a first processor and a second processor includes obtaining a code region specified to be executed on the second processor, the code region including a plurality of instructions, calculating a performance improvement of executing at least one of the plurality of instructions included in the code region on the second processor over executing the at least one instruction on the first processor, removing the at least one instruction from the code region in response to a condition including that the performance improvement does not exceed a first threshold, and repeating the calculating and the removing to produce a modified code region specified to be executed on the second processor.

Abstract: Application virtualization at the thread level, rather than at the process level. the operation of a thread across virtualization contexts. For instance, one virtualization context might be a native environment, whereas another virtualization context might be a virtualization environment in which code running inside a virtualization package has access to virtualized computing resources. A thread operating in a first virtualization context then enters an entry point to code associated with a second virtualization context. For instance, a native thread might enter a plug-in operating as part of a virtualized package in a virtualization environment. While the thread is operating on the code, the thread might request access to the second computing resources associated with the second virtualization environment. In response, the thread is associated with the second virtualization context such that the thread has access to the second computing resources associated with the second virtualization context.

Abstract: Provided are techniques for an operating system (OS) to be modified on a running system such that running programs, including system services, so not have to be stopped and restarted for the modification to take effect. The techniques include detecting, by a processing thread, when the processing thread has entered a shared library; in response to the detecting, setting a thread flag corresponding to the thread in an operating system (OS); detecting an OS flag, set by the OS, indicating that the OS is updating the shared library; in response to detecting the OS flag, suspending processing by the processing thread and transferring control from the thread to the OS; resuming processing by the processing thread in response to detecting that the OS has completed the updating; and executing the shared library in response to the resuming.

Abstract: Methods, systems, and products are provided for thread-agile dynamic programming language (‘DPL’) program execution. Thread-agile DPL program execution may be carried out by receiving, in a message queue, a message for an instance of a DPL program and determining whether the host application has a stored state object for the instance of the DPL program identified by the message. If the host application has a stored state object for the DPL program, thread-agile DPL program execution may also carried out by retrieving the state object; preparing a thread available from a thread pool for execution of the instance of the DPL program in dependence upon the state object and an execution context for the instance of the DPL program; providing, to an execution engine for executing the DPL program, the state object and the prepared thread; and passing the message to the execution engine.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for managing an application having sub-applications sharded across different servers. A plurality of servers each serve a separate sub-application of a primary application that includes one or more of the sub-applications. The sub-applications are combined at a client device to create a graphical user interface of the primary application. Each of the sub-applications is separately served in response to multiple different network calls to multiple different servers initiated by the client device. Synchronization code, served by one or more of the servers, prevents the client device from initiating a network call for UI code that renders static user interface elements of each sub-application until the client device has initiated one or more networks calls requesting data that will be presented by a given user interface view of the sub-application.

Abstract: Method and system are provided for preventing local processing problems interfering with a time-sensitive validation process. The method monitors an elapsed time of an instance of a time-sensitive validation process of a software component including dispatching of the process instance and determines if the elapsed time is significantly greater than a preset processing time. If so, the method may dynamically alter error processing of the time-sensitive validation process of the software component.

Abstract: A technique for short-circuiting normal read-copy update (RCU) grace period computations in the presence of expedited RCU grace periods. The technique may include determining during normal RCU grace period processing whether at least one expedited RCU grace period elapsed during a normal RCU grace period. If so, the normal RCU grace period is ended. If not, the normal RCU grace period processing is continued. Expedited RCU grace periods may be implemented by expedited RCU grace period processing that periodically awakens a kernel thread that implements the normal RCU grace period processing. The expedited RCU grace period processing may conditionally throttle wakeups to the kernel thread based on CPU utilization.

Abstract: A technique for short-circuiting normal read-copy update (RCU) grace period computations in the presence of expedited RCU grace periods. The technique may include determining during normal RCU grace period processing whether at least one expedited RCU grace period elapsed during a normal RCU grace period. If so, the normal RCU grace period is ended. If not, the normal RCU grace period processing is continued. Expedited RCU grace periods may be implemented by expedited RCU grace period processing that periodically awakens a kernel thread that implements the normal RCU grace period processing. The expedited RCU grace period processing may conditionally throttle wakeups to the kernel thread based on CPU utilization.

Abstract: Functional units of a processor fetch and decode architectural instructions of an architectural program. The architectural instructions are of an architectural instruction set of the processor. An execution unit includes first and second memories, a register and processing units. The first memory holds data in rows with addresses. The second memory holds non-architectural instructions of a non-architectural program. The architectural and non-architectural instruction sets are distinct. The processing units execute the non-architectural program instructions to read data from the first memory, perform operations on the data read from the first memory to generate results, and to write the results to the first memory. The register holds information that indicates progress made by the non-architectural program during execution. The first memory is also readable and writable by the architectural program. The architectural program uses the information to decide where in the first memory to read/write data.

Abstract: Hardware transactional memory (HTM) systems may guarantee that transactions commit without falling back to non-speculative code paths. A transaction that fails to progress may enter a power mode, giving the transaction priority when it conflicts with non-power-mode transactions. If, during execution of a power-mode transaction, another thread attempts, using a non-power-mode transaction, to access a shared resource being accessed by the power-mode transaction, it may be determined whether any actual data conflict occurs between the two transactions. If no data conflict exists, both transactions may continue to completion. If, however, a data conflict does exist, the power-mode transaction may deny the other transaction access to the shared resource. HTM systems may, in some embodiments, ensure that only one power-mode transaction exists at a time. In other embodiments, multiple, concurrent, power-mode transactions may be supported while ensuring that they access disjoint data sets.

Abstract: A method of controlling a display device including a touch screen is provided. The method includes displaying, on the touch screen, a plurality of windows respectively corresponding to executing applications, such that the windows do not overlap each other, displaying a plurality of boundary lines differentiating the plurality of windows, and a center button disposed at an intersection point of the plurality of boundary lines, receiving, through the touch screen, an input of a window size change command to change a size of at least one of the plurality of windows, and resizing and displaying at least one of the plurality of windows in correspondence to the window size change command.

Abstract: Techniques are disclosed for efficiently sequencing operations performed in multiple threads of execution in a computer system. In one set of embodiments, sequencing is performed by receiving an instruction to advance a designated next ticket value, incrementing the designated next ticket value in response to receiving the instruction, searching a waiters list of tickets for an element having the designated next ticket value, wherein searching does not require searching the entire waiters list, and the waiters list is in a sorted order based on the values of the tickets, and removing the element having the designated next ticket value from the list using a single atomic operation. The element may be removed by setting a waiters list head element, in a single atomic operation, to refer to an element in the list having a value based upon the designated next ticket value.

Abstract: Disclosed aspects relate to checkpointing a set of stream computing data with respect to a stream computing environment having a set of windowed stream operators including both a first windowed stream operator and a second windowed stream operator. It may be identified that the first windowed stream operator has a first subset of the set of stream computing data. It may be identified that the second windowed stream operator has the first subset of the set of stream computing data. It may be determined to checkpoint the first subset of the set of stream computing data without a redundant checkpoint related to the first and second windowed stream operators. The set of stream computing data may be checkpointed without the redundant checkpoint of the first subset of the set of stream computing data.

Abstract: In one embodiment a graphics processing system comprises a graphics processor having execution logic and shared memory and a shader compiler unit to compile a shader program for execution by the execution logic of the graphic processor, wherein the shader is to optimize the shader program during the compile, wherein to optimize the shader program includes to convert a divergent block of parallel instructions into a divergent block and a non-divergent block of instructions.

Abstract: Systems and methods are disclosed for automatically constructing output media stream from multiple input media sources by applying models learned from existing media products.

Abstract: A method for executing two tasks in timesharing, includes: decomposing offline each task in a repetitive sequence of consecutive frames, and defining a start date and deadline by which an associated atomic operation must respectively start and end; verifying for each frame of a first of the repetitive sequences the corresponding operation can be performed between any two successive operations of a group of frames of the second repetitive sequence, overlapping the first repetitive sequence frame; and if the verification is satisfied, allowing the execution of the two tasks. Scheduling the operations of the two tasks, if two operations can start, executing the operation having the shorter deadline; and if a single operation can start, executing it if its execution need is less than the time remaining until the next frame start date of the other sequence, plus the time margin associated with the next frame of the other sequence.

Abstract: A system has one or more primary power regions having restrictions indicating that the primary power regions are not to be placed in an offline state. The system also includes one or more secondary power region that can either be parked or off-lined into a limited state having limited functionality in that functionality is removed from the one or more secondary power regions when placed in a limited state. At least one interrupt is allocated to one of the primary power regions, based on interrupt characteristics.

Abstract: Caching extracted information from application containers by one or more processors. Upon extracting relevant information from a temporary container, the relevant information is cached at a container template level. A space guard is applied controlling an amount of storage consumed by the cached relevant information, and a time guard is applied controlling an expiration of the cached relevant information. The cached relevant information is maintained for injection into a working container. Applying the space guard includes defining a purge process for pruning or removing cached relevant information stored in the cache, and candidate files for the purge process may be identified using a predetermined criterion. Applying the time guard includes using a time metric defined in a profile of an information injection agent, where the time metric is based on one of a creation time, a last access time or a last modified time of the cached relevant information.

Abstract: A thread in a computing system is processed for execution of instructions to perform an action. The action is one of the following: accessing a shared resource or executing a critical section of code. A schedule of the thread is managed. The management prevents suspension of the thread during execution of the action.

Abstract: For effective joint evaluation of a medical image dataset on a first data processing device and at least one second data processing device that is connected to the first data processing device via a data transmission network, a first application is performed in the first data processing device, and a second application is performed in the second data processing device. Each of the applications has a respective graphical user interface having at least one segment for display of a view of the image dataset. An image processing pipeline is associated with each segment for deriving the view from the image dataset. Partially processed data of the image dataset is decoupled from the image processing pipeline of the segment of the first application, is transferred to the second application, and there is coupled to the image processing pipeline of the segment of the second application for preparing the view.

Abstract: A management agent operates transparently in the background on each endpoint computing device that needs to be managed. The agent sets up a sandboxed environment on the endpoint computing device on which it is operating in order to capture applications that have been installed on the endpoint device. The application capture is performed after the applications have been installed on the endpoint device and therefore does not require installing the application on any dedicated staging machine, nor any recording of the pre-installation state. The application capture process involves running the application from an isolated sandboxed environment on the computing device in order to identify all necessary components of the application by monitoring accesses by the application to components located outside of the sandbox. The identified components can then be packaged together and managed as individual application packages.

Abstract: A task control circuit maintains, in response to task event information, a task information queue that includes task information for a plurality of tasks. Based upon the task information in the task information queue, a future task switch condition is identified as corresponding to a task switch time for a particular task of the plurality of tasks. A load start time is determined for a set of instructions for the particular task. A pre-fetch request is generated to load the set of instructions for the particular task into the memory circuit. The pre-fetch request is forwarded to a hardware loader circuit. In response to the task switch time, a task event trigger is generated for the particular task. The hardware loader circuit is used to load, in response to the pre-fetch request, the set of instructions from a non-volatile memory into the memory circuit.

Abstract: Pre-fetching instructions for tasks of an operating system (OS) is provided by calling a task scheduler that determines a load start time for a set of instructions for a particular task corresponding to a task switch condition. The OS calls, and in response to the load start time, a loader entity module that generates a pre-fetch request that loads the set of instructions for the particular task from a non-volatile memory circuit into a random access memory circuit. The OS calls the task scheduler to switch to the particular task.

Abstract: An outcast index in a distributed file system is described. A first server can receive an indication that a first replica stored on the first server is to be modified in view of a second replica stored on a second server. The first replica and the second replica are replicas of a same file. The first server updates metadata associated with the first replica to indicate an outcast state of the first replica. The first server receives an indication that the modification of the first replica is complete. The first server updates the metadata associated with the first replica to remove the outcast state of the first replica.

Abstract: A method and apparatus are disclosed for enhancing operable functionality of input source code files from a software program by identifying a first code snippet and a first library function which generate similar outputs from a shared input by parsing each and every line of code in a candidate code snippet to generate a templatized code snippet data structure for the first code snippet, and then testing the templatized code snippet data structure against extracted library function information to check for similarity of outputs between the first code snippet and the first library function in response to a shared input so that the developer is presented with a library function recommendation which includes the first code snippet, the first library function, and instructions for replacing the first code snippet with the first library function.

Abstract: A system and method can use continuation-passing to transform a queue from non-blocking to blocking. The non-blocking queue can maintain one or more idle workers in a thread pool that is not accessible from outside of the non-blocking queue. The continuation-passing can eliminate one or more serialization points in the non-blocking queue, and allows a caller to manage the one or more idle workers in the thread pool from outside of the non-blocking queue.

Abstract: A multi-threaded processing unit includes a hardware pre-processor coupled to one or more processing engines (e.g., copy engines, GPCs, etc.) that implement pre-emption techniques by dividing tasks into smaller subtasks and scheduling subtasks on the processing engines based on the priority of the tasks. By limiting the size of the subtasks, higher priority tasks may be executed quickly without switching the context state of the processing engine. Tasks may be subdivided based on a threshold size or by taking into account other consideration such as physical boundaries of the memory system.

Abstract: Expediting content delivery is disclosed. A request for content is received from a requestor. A cached component of the requested content that includes at least some cached executable content is identified. The cached component of the requested content is provided to the requestor for provisional execution. It is determined whether a change, if any, in the requested content may invalidate the provisional execution.

Abstract: A system, method and computer product for predicting a content attribute are provided by collecting labeled media objects labeled with one or more attributes, constructing a feature vector of content-derived values for each of the labeled media objects, generating a model based on the feature vector and the one or more attributes, and applying the model to one or more unlabeled media objects to generate one or more attribute labels.

Abstract: A processor includes a front end, an execution pipeline, and a binary translator. The front end includes logic to receive an instruction and to dispatch the instruction to a binary translator. The binary translator includes logic to determine whether the instruction includes a control-flow instruction, identify a source address of the instruction, identify a target address of the instruction, determine whether the target address is a known destination based upon the source address, and determine whether to route the instruction to the execution pipeline based upon the determination whether the target address is a known destination based upon the source address. The target address includes an address to which execution would indirectly branch upon execution of the instruction.

Abstract: A present disclosure provides a garbage collector capable of freeing memory reachable only by a terminated thread immediately upon thread exit without scanning the heap or blocking other threads. A heap, including a plurality of spans, is walked, for example when the heap reaches a predetermined size. Reachable objects are marked in a mark bitmap. A mutator sweeps the mark bitmap without clearing mark bits, and newly allocated objects are not marked. When the thread terminates, sweep pointers in each of the spans owned by the terminated thread are reset. Moreover, a write barrier that makes a first unpublished object reachable from a second published object, also publishes the first object and all objects reachable from the first object.

Abstract: Methods, systems and computer program products for resolving multiple magnitudes assigned to a target vector are disclosed. A target vector that includes one or more target vector dimensions is received. One of the target vector dimensions is processed to determine a total number of magnitudes assigned to the processed target vector dimension. Also, a source vector that includes one or more source vector dimensions is received. The received source vector is processed to determine a total number of features associated with the source vector. When it is detected that the total number of magnitudes assigned to the processed target vector dimension exceeds one, one of the assigned magnitudes is selected based on one of the determined features associated with the source vector.

Abstract: Disclosed in the present application are a method and device for managing a shared memory in a robot operating system.

Abstract: A method of controlling a display device including a touch screen is provided. The method includes displaying, on the touch screen, a plurality of windows respectively corresponding to executing applications, such that the windows do not overlap each other, displaying a plurality of boundary lines differentiating the plurality of windows, and a center button disposed at an intersection point of the plurality of boundary lines, receiving, through the touch screen, an input of a window size change command to change a size of at least one of the plurality of windows, and resizing and displaying at least one of the plurality of windows in correspondence to the window size change command.

Abstract: One or more processors determine that a user is attempting to execute an unscheduled computing task and estimate the time for execution. One or more processors determine that a computing task is scheduled to execute along with the unscheduled computing task. One or more processors warn the user that the computing task is scheduled to execute along with the unscheduled computing task. One or more processors estimate one or both of: a utilization of processing and a memory consumption for the computing tasks and determine whether a threshold will be exceeded. If the threshold will be exceeded, one or more processors warn the user.

Abstract: One or more processors determine that a user is attempting to execute an unscheduled computing task and estimate the time for execution. One or more processors determine that a computing task is scheduled to execute along with the unscheduled computing task. One or more processors warn the user that the computing task is scheduled to execute along with the unscheduled computing task. One or more processors estimate one or both of: a utilization of processing and a memory consumption for the computing tasks and determine whether a threshold will be exceeded. If the threshold will be exceeded, one or more processors warn the user.

Abstract: Information representative of a graph-based program specification has components, and directed links between ports of said components, defining a dependency between said components. A directed link exists between a port of a first component and a port of a second component. The first component specifies first-component execution code that when compiled enables execution of a first task. The second component specifies second-component execution code that when compiled enables execution of a second task. Compiling the graph-based program specification includes grafting first control code to said first-component execution code, which changes a state of said second component to a pending state, an active state, or a suppressed state. Based on said state, said first control code causes at least one of: invoking said second component if said state changes from pending to active, or suppressing said second component if said state changes from pending to suppressed.