Abstract: A method for automatic task-level parallelization of execution of a computer program with automatic concurrency control. According to this invention, shared data in memory must be queried. Such memory queries represent side-effects of their enclosing tasks and allow determining how tasks must be executed with regard to each other based on intersections of their queried data. Tasks that have intentions to modify the same data (their side-effects intersect) must be executed sequentially; otherwise, tasks can be executed in parallel.

Abstract: A parallel allocation calculating unit calculates a parallel allocation candidate which is an element candidate in target data allocated per processing performed in parallel. A parallel calculation amount estimation processing unit estimates the calculation amount required for parallel processing when a parallel allocation candidate is allocated, based on a nonzero element count in the target data. An optimality decision processing unit decides whether or not the parallel allocation candidate is optimal based on the calculated calculation amount, and allocates the optimal element per processing performed in parallel.

Abstract: A method, apparatus and computer program product is provided to create an integration process between a source system and target system. The method includes creating a mapping between one or more source objects and one or more target objects and generating a complete workflow as part of an integration process between a respective source system and target system. A limited subset of operations is selectively included from a sequence of activities in the complete workflow that interact with the one or more source objects and one or more target objects. The limited subset of operations selected from the complete workflow is sequenced in a stepwise template that streamlines the integration process between the source system and target system, by focusing on mappings between and operations performed upon source objects and target objects associated with the limited subset of operations selected from the operations in the complete workflow.

Abstract: Provided is a method and apparatus for measuring a performance or a progress state of an application program to perform data processing and execute particular functions in a computing environment using a micro architecture. A thread progress tracking apparatus may include a selector to select at least one thread constituting an application program; a determination unit to determine, based on a predetermined criterion, whether an instruction execution scheme corresponds to a deterministic execution scheme having a regular cycle or a nondeterministic execution scheme having an irregular delay cycle with respect to each of at least one instruction constituting a corresponding thread; and a deterministic progress counter to generate a deterministic progress index with respect to an instruction that is executed by the deterministic execution scheme, excluding an instruction that is executed by the nondeterministic execution scheme.

Abstract: An electronic device, and a method for executing a plurality of processes with the electronic device, wherein, in a resource-conserving manner, rapid response times are achievable, in that the electronic device, during operation, executes first and second processes (P1, P2), of which the first processes (P1) are executable as approximate solutions (P1-A) and as detailed calculations (P1-C). The electronic device includes a processor for executing processes (P1, P2) and an electronic unit or a multitasking-capable operating system. The electronic unit includes a component, which recognizes whether the processor is active, and serves, while the processor is active and a simultaneous execution of at least two processes is required, for executing the first processes (P1), in that it, itself, determines the approximate solution (P1-A) and sets such in the place of a detailed calculation (P1-C) determined with the processor.

Abstract: A data processing device includes an instruction executing part executing a normal task and a management task scheduling an execution order of the normal task with switching the normal task and the management task, a counter measuring an execution state of the normal task being executed in the instruction executing part, and a state controller controlling the counter based on the normal task being executed in the instruction executing part. The instruction executing part determines whether the normal task to be executed next of a plurality of normal tasks scheduled by the management task is a measurement object or not, and outputs an operation signal notifying the state controller of the determination result. The state controller operates the counter in accordance with the branch operation.

Abstract: A communication system is applicable to communications between client terminals and a server via the Internet, and includes a communication service unit creating a communication interface and a memory region in response to a communication request from a client terminal via the Internet, starting an application program in the created memory region in response to the communication request, sending contents of the started application program to the client terminal, and updating data in the memory region and sending the updated data to the client terminal when the communication request includes data updating.

Abstract: A method of executing an algorithm in a parallel manner using a plurality of concurrent threads includes generating a lock-free barrier that includes a variable that stores both a total participants count and a current participants count. The total participants count indicates a total number of threads in the plurality of concurrent threads that are participating in a current phase of the algorithm, and the current participants count indicates a total number of threads in the plurality of concurrent threads that have completed the current phase. The barrier blocks the threads that have completed the current phase. The total participants count is dynamically updated during execution of the current phase of the algorithm. The generating, blocking, and dynamically updating are performed by at least one processor.

Abstract: Technologies are described herein for adapting a processor core on a multicore processor to achieve a quality of service target. Some example technologies may identify a target level of a resource on the computer. The technologies may identify a first utilization value and a second utilization value of the resource when the processor core operates at a first frequency and a second frequency. The technologies may generate a linear interpolation between a first point and a second point. Coordinates of the first point may include the first frequency and the first utilization value. Coordinates of the second point may include the second frequency and the second utilization value. The technologies may set the processor core to operate at a third frequency, which can be specified as one of the coordinates in an intersection point between the linear interpolation and the target level.

Abstract: A method of determining a location of one or more print production items in a storage facility may include identifying one or more print production items used by one or more autonomous production cells in a print shop, and determining, by a computing device, a demand value associated with each of the identified print production items. The demand value may represent a frequency with which the print production item is used by the autonomous production cells over a period of time. The method may include grouping the identified print production items into one or more groups based on the autonomous production cell that uses the identified print production items, assigning each group to an autonomous storage cell, and determining a location of one or more autonomous storage cells based on the demand values associated with the print production items in the group associated with the autonomous storage cell.

Abstract: Embodiments relate to systems and methods for a shared object lock under state machine control. An operating system or virtual machine environment can host a set of multiple executing threads, and provide those threads with mutual access to one or more objects such as storage objects, memory objects, or others. The threads can independently request that the object be locked or unlocked, and the locked or unlocked state can be shared between the threads. Rather than communicate with the object(s) directly, in embodiments the threads communicate with a state machine that in turn controls the state of the object(s). When a request to change the state of the object(s) is received, the state machine can permit the object(s) to change between locked, unlocked, or other states based on the current state of the machine and the received message. Contention between threads can be reduced or eliminated.

Abstract: Disclosed are a workflow monitoring control system, method, and program, wherein, when workflows are executed by passing through processing sections, each provided with business application software, in order, the service quality of the workflows can be ensured in as many workflows as possible with limited computer resources. A workflow monitoring and control system connected to a plurality of processing sections each of which executes a unit process assigned respectively, a unit process being one of parts constituting business data processing, by using business application software and computer resources, comprises a workflow defining means, a service quality lower limit setting means, a service quality calculation means, a quality insufficiency judging means, a computer resource reallocation means.

Abstract: A virtual storage management method that can increase the overall processing speed while preventing a processor from being overloaded. A request for acquisition of a memory area in a primary storage device is received from a process executed by a processor. It is determined whether or not the process that has made the acquisition request is a utility process executable in cooperation with another process. Control is provided so as to restrict swap-out of the utility process when it is determined that the process that has made the received acquisition request is a utility process executable in cooperation with another process, and a process cooperating with the utility process executed by the processor is a preferred process of which swap-out is restricted, and a processor utilization of the preferred process is greater than a predetermined value.

Abstract: A circuit configuration for a data processing system and a corresponding method for executing multiple tasks by way of a central processing unit having a processing capacity assigned to the processing unit, the circuit configuration being configured to distribute the processing capacity of the processing unit uniformly among the respective tasks, and to process the respective tasks in time-offset fashion until they are respectively executed.

Abstract: Described embodiments provide a packet classifier for a network processor that generates tasks corresponding to each received packet. The packet classifier includes a scheduler to generate contexts corresponding to tasks received by the packet classifier from a plurality of processing modules of the network processor. A multi-thread instruction engine processes threads of instructions, each thread of instructions corresponding to a context received from the scheduler. A thread status manager maintains a thread status table having N entries to track up to N active threads. Each status entry includes a valid status indicator, a sequence value, and a thread indicator. A sequence counter generates a sequence value for each thread and is incremented when processing of a thread is started, and is decremented when a thread is completed, by the multi-thread instruction engine. Instructions are processed by the multi-thread instruction engine in the order in which the threads were started.

Abstract: Software development tools and techniques for configuring parallel processing systems to execute software modules implementing processes for solving complex problems, including over-the-counter trading processes and foreign exchange trading processes, to execute quickly and efficiently. The parallel processing system may include low-cost, consumer-grade multicore processing units. A process for solving a complex problem may be divided into software modules, including by evaluating the process to determine discrete processing steps that produce an intermediate result on which later steps of the process depend. The software modules created for a process may form a template processing chain describing multiple processing chains of the process that are to be executed.

Abstract: A computer implemented method and system for data processing. The method including: (a) setting at least one SMT preliminary value for at least one operating node; (b) monitoring performance metrics for the at least one operating node set to the at least one SMT preliminary value; and (c) determining a SMT revised value based on performance metrics. The system including: a memory; a processor communicatively coupled to the memory; and a feature selection module communicatively coupled to the memory and processor, wherein the feature selection module is configured to perform steps of a method including: setting, using a setting device, at least one SMT preliminary value for at least one operating node; monitoring, using a monitoring device, performance metrics for the at least one operating node set to the at least one SMT preliminary value; and determining, using a determining device, a SMT revised value based on performance metrics.

Abstract: In a method for minimizing occurrences of hanging escalations in a computer system, a computer determines that a number of escalations are scheduled for simultaneous execution in a time interval in a production environment. The computer divides the time interval by the number of escalations to form a shortened time interval. Moreover, the computer reschedules execution of the number of escalations in the production environment such that a plurality of subsets of the number of escalations execute in a staggered order according to the shortened time interval. A hanging escalation is an escalation that fails to complete, fails to process all data or records that the escalation was to process, or completes beyond an allotted processing time.

Abstract: An application programming interface (API) provides various software constructs that allow a developer to assemble a processing pipeline having arbitrary structure and complexity. Once assembled, the processing pipeline is configured to include a set of interconnected pipestages. Those pipestages are associated with one or more different CTAs that may execute in parallel with one another on a parallel processing unit. The developer specifies the configuration of the pipestages, including the configuration of the different CTAs across all pipestages, as well as the different processing operations performed by each different CTA.

Abstract: An application programming interface (API) provides various software constructs that allow a developer to assemble a processing pipeline having arbitrary structure and complexity. Once assembled, the processing pipeline is configured to include a set of interconnected pipestages. Those pipestages are associated with one or more different CTAs that may execute in parallel with one another on a parallel processing unit. The developer specifies the configuration of the pipestages, including the configuration of the different CTAs across all pipestages, as well as the different processing operations performed by each different CTA.

Abstract: Provided is a radio base station apparatus capable of transmitting a control signal efficiently even in radio communications using a system band that includes a plurality of component carriers. In the radio base station apparatus, control signals of transport blocks corresponding to the plural component carriers are coded jointly and the coded control signal is assigned to one or plural component carriers to be transmitted. A mobile terminal apparatus receives data from the radio base station apparatus, separates the control signal from the received data and decodes the separated control signal thereby to obtain control information of the transport blocks of the corresponding component carriers.

Abstract: Methods and systems for scenario-based process modeling are described. In one example embodiment, a system for scenario-based process modeling can include a scenario module, a deviations module, a parallel tasks module, and a workflow generation engine. The scenario module is to receive a series of tasks to define a standard process flow. The deviations module is to receive a deviation from the standard process flow. The parallel tasks module is to enable identification of one or more parallel tasks. The workflow generation engine is to generate a workflow model based on the standard process flow, deviation, and one or more parallel tasks.

Abstract: The present disclosure provides a method, computer program product, and system for compensating for event counts for a thread occurring during targeted states on the thread. In example embodiments, the state is a spin loop state and instructions completed during the spin loop are eliminated from a performance report and are presented in the absence of the spin loop. In another embodiment, the event counts are interrupt counts eliminated during the spin loop.

Abstract: A method and system for achieving time-awareness in the highly available, fault-tolerant execution of components in a distributed computing system, without requiring the writer of these components to explicitly write code (such as entity beans or database transactions) to make component state persistent. It is achieved by converting the intrinsically non-deterministic behavior of the distributed system to a deterministic behavior, thus enabling state recovery to be achieved by advantageously efficient checkpoint-replay techniques. The system is deterministic by repeating the execution of the receiving component by processing the messages in the same order as their associated timestamps and time-aware by allowing adjustment of message execution based on time.

Abstract: A system and method for parallel processing of semantically grouped data in data warehouse environments is disclosed. A datastore object having a number of records is generated in a data warehouse application. A hash value is added to each record. The hash value has an integer domain, and is uniformly distributed over the integer domain across the datastore object. A selection table is generated to create a number of tasks based on discrete ranges of the hash value. Then, a transformation routine is executed on each of the number of tasks in parallel to generate an infocube of data that corresponds to each range of the discrete ranges of the hash value.

Abstract: A system and method of terminating processing requests dispatched to a coprocessor hardware accelerator in a multi-processor computer system based on matching various fields in the request made to the coprocessor to identify the process to be terminated. A kill command is initiated by a write operation to a coprocessor block kill register and has match enable and value for each field in the coprocessor request to be terminated. Enabled fields may have one or more values associated with a single request or multiple requests for the same coprocessor. At least one match enable must be set to initiate a kill request. A process kill active signal prevents other coprocessor jobs from moving between operational stages in the coprocessor hardware accelerator. Processing jobs that are idle or do not match the fields with match enables set signal done with no match and continue processing. Processing jobs that do match the fields with match enables set are terminated and signal done with match.

Abstract: The present invention suggests a data parallel processing device that performs parallel processing on input data by varying a flow ID generating manner depending on a loading degree of the processor in the multi-processor structure configured by processor array. The suggested device includes a flow ID generating unit which generates a flow ID for input data which is differentiated in accordance with a status of a buffer; a data allocating unit which allocates data having the same flow ID to a specified processor; and a data processing unit which sequentially processes data allocated to each processor so that the parallel processing performance is improved as compared with the related art.

Abstract: In one embodiment, the present invention includes a method of assigning a location within a shared variable for each of multiple threads and writing a value to a corresponding location to indicate that the corresponding thread has reached a barrier. In such manner, when all the threads have reached the barrier, synchronization is established. In some embodiments, the shared variable may be stored in a cache accessible by the multiple threads. Other embodiments are described and claimed.

Abstract: Disclosed is an automatic optimization system capable of searching for an allocation with a good performance from among a plurality of task allocations which can be scheduled in a system of a development target configured with a plurality of periodic tasks. A task allocation optimization system for a multi-core processor including a plurality of cores calculates a response time of each of a plurality of tasks which are core allocation decision targets, and outputs an accumulative value of the calculated response time as an evaluation function value which is an index representing excellence of a task allocation. A task allocation from which a good evaluation function value is calculated is searched based on the evaluation function value. A candidate having a good evaluation function value among a plurality of searched task allocation candidates is held.

Abstract: A computing apparatus identifies that a first physical processor of a host has forwarded information regarding a device interrupt for a device to a second physical processor executing at least one of a virtual processor that controls the device or an application thread that controls the device. After identifying that the first physical processor has forwarded the information regarding the device interrupt to the second physical processor and in response to determining that one or more update criteria have been satisfied, the computing apparatus updates at least one of the device or an interrupt controller to cause at least one of the device or the interrupt controller to send future device interrupts for the device to the second physical processor.

Abstract: In a cellular phone applicable to an information processing apparatus according to the present invention, a CPU of a main control unit executes monitor threads 1 to 3, monitors groups including a plurality of threads set with priority by executing a keep-alive operation to a plurality of monitor threads that monitor operations of threads in the groups, determines whether there is a monitor thread without a response to the keep-alive operation based on responses from the plurality of monitor threads, and terminates delivery of events to the groups with priority higher than the group monitored by the monitor thread without a response to the keep-alive operation if it is determined that there is a monitor thread without a response to the keep-alive operation.

Abstract: A technique for improving the performance of RCU-based searches and updates to a shared data element group where readers must see consistent data with respect to the group as a whole. An updater creates one or more new group data elements and assigns each element a new generation number that is different than a global generation number associated with the data element group, allowing readers to track update versions. The updater links the new data elements into the data element group and then updates the global generation number so that referential integrity is maintained. This is done using a generation number element that is referenced by a header pointer for the data element group, and which in turn references or forms part of one of the data elements. After a grace period has elapsed, the any prior version of the generation number element may be freed.

Abstract: The present invention relates to a data broadcast processing device, method, and program which enable secure control of an operation of a data broadcast processing device. Since a flag standalone is not set in a script NCL Script 133, the script NCL Script 133 is executed from time t13 till time t15, simultaneously with a script NCL Script 132 and a script NCL Script 134. In contrast, a script NCL Script 135, in which the flag standalone is set, is prohibited from being executed simultaneously with another script NCL Script 134 in which the flag standalone is set.

Abstract: Parallel graphics-processing methods and mobile computing apparatus with parallel graphics-processing capabilities are disclosed. One exemplary embodiment of a mobile computing apparatus includes physical memory, at least two distinct graphics-processing devices, and a bus coupled to the physical memory and the at least two graphics-processing devices. A virtual graphics processing component enables each of at least two graphics-processing operations to be executed, in parallel, by a corresponding one of the at least two distinct graphics-processing devices, which operate in the same memory surface at the same time.

Abstract: A technique for managing read-copy update readers that have been preempted while executing in a read-copy update read-side critical section. A single blocked-tasks list is used to track preempted reader tasks that are blocking an asynchronous grace period, preempted reader tasks that are blocking an expedited grace period, and preempted reader tasks that require priority boosting. In example embodiments, a first pointer may be used to segregate the blocked-tasks list into preempted reader tasks that are and are not blocking a current asynchronous grace period. A second pointer may be used to segregate the blocked-tasks list into preempted reader tasks that are and are not blocking an expedited grace period. A third pointer may be used to segregate the blocked-tasks list into preempted reader tasks that do and do not require priority boosting.

Abstract: A data processing apparatus includes a processor configured to receive an interrupt request that is a trigger for execution of an interrupt process executed by the processor; store the received interrupt request to a recording area; calculate based on a time when the interrupt request is received and particular time information read from the recording area, a predicted time when a subsequent interrupt request is to be received; detect a thread to be executed by the processor, among executable threads of the processor; judge based on the calculated predicted time and a current time, whether there is a possibility of the interrupt process being executed while the detected thread is under execution; decide based on a judgment result, whether to execute the detected thread on the processor; and execute the detected thread on the processor, based on a decision result.

Abstract: A method comprising receiving data, where the data includes one or more elements, the data is associated with a first set of indices, and the first set of indices references the one or more elements. The method may further include folding a plurality of indices into a single index, where the single index references the one or more elements of the received data that were referenced by the plurality of indices, the folding generates a second set of indices, and the folding is performed when concurrent process threads are not generated based on the first set of indices. The method may further include determining whether concurrent process threads should be generated based on the second set of indices and generating the concurrent process threads for the second set of indices when the determining determines that the concurrent process threads should be generated based on the second set of indices.

Abstract: The present disclosure involves systems, software, and computer implemented methods for reducing transaction load for process instance completion. One process includes identifying an end event triggered by an initial token of a process instance, determining a type of the end event, performing a search for additional tokens associated with the process instance that are distinct from the initial token, and performing a termination action based on the type of end event and a number of additional tokens identified in the search. The end event type may be non-terminating or terminating, and the end event type can determine the termination action to be performed. If the end event is non-terminating, then the termination action includes joining each finalization action for each process instance variable to a completion transaction if no additional tokens are found and executing the completion transaction to terminate the process instance.

Abstract: A technique for executing normally interruptible threads of a process in a non-preemptive manner includes in response to a first entry associated with a first message for a first thread reaching a head of a run queue, receiving, by the first thread, a first wake-up signal. In response to receiving the wake-up signal, the first thread waits for a global lock. In response to the first thread receiving the global lock, the first thread retrieves the first message from an associated message queue and processes the retrieved first message. In response to completing the processing of the first message, the first thread transmits a second wake-up signal to a second thread whose associated entry is next in the run queue. Finally, following the transmitting of the second wake-up signal the first thread releases the global lock.

Abstract: Whether or not allocation to router control is used up is determined. Whether or not CPU utilization allocated to the router control is used up is determined. If it is determined that the allocation for router control is used up, a sub-allocation changing process is executed for changing the CPU utilization. If it is determined that the allocation for router control is not used up, a router control allocation subtracting process is executed.

Abstract: An information processing apparatus assigns the calculation of a first submatrix included in a matrix including zero elements and non-zero elements to a first thread and the calculation of a second submatrix included in the matrix to a second thread. The information processing apparatus compares the distribution of non-zero elements in the rows or columns of the first submatrix with the distribution of non-zero elements in the rows or columns of the second submatrix. The information processing apparatus determines allocation of storage areas for storing vectors to be respectively used in the calculations by the first and second threads, according to the result of the comparison.

Abstract: A mechanism for asynchronous input/output (I/O) using second stack switching in kernel space is disclosed. A method of the invention includes receiving, by a kernel executing in a computing device, an input/output (I/O) request from an application thread executing using a first stack, allocating a second stack in kernel space of the computing device, switching execution of the thread to the second stack, and processing the I/O request synchronously using the second stack.

Abstract: Controlling a device having a shared processing resource includes ascertaining a supervision timer value for a client service that uses the shared processing resource. The client service is caused to make a server request and a supervision timer is set to cause a timeout after a supervision timer value time period. Ascertaining the supervision timer value includes ascertaining which of a number of use scenarios represents an operation state of the device, the use scenarios being at least in part distinguished from one another by which services are presently active, including the client service. Each of the plurality of services utilizes the shared processing resource when active. One supervision timer value is selected from a number of values each associated with the client service, selection being made at least partly as a function of the ascertained use scenario. The value is retrieved from the set of stored supervision timer values.

Abstract: Techniques are disclosed for qualified checkpointing of a data flow model having data flow operators and links connecting the data flow operators. A link of the data flow model is selected based on a set of checkpoint criteria. A checkpoint is generated for the selected link. The checkpoint is selected from different checkpoint types. The generated checkpoint is assigned to the selected link. The data flow model, having at least one link with no assigned checkpoint, is executed.

Abstract: System, method, and computer program product to process parallel computing tasks on a distributed computing system, by computing an execution plan for a parallel computing job to be executed on the distributed computing system, the distributed computing system comprising a plurality of compute nodes, generating, based on the execution plan, an ordered set of tasks, the ordered set of tasks comprising: (i) configuration tasks, and (ii) execution tasks for executing the parallel computing job on the distributed computing system, and launching a distributed computing application to assign the tasks of the ordered set of tasks to the plurality of compute nodes to execute the parallel computing job on the distributed computing system.

Abstract: Techniques are disclosed for qualified checkpointing of a data flow model having data flow operators and links connecting the data flow operators. A link of the data flow model is selected based on a set of checkpoint criteria. A checkpoint is generated for the selected link. The checkpoint is selected from different checkpoint types. The generated checkpoint is assigned to the selected link. The data flow model, having at least one link with no assigned checkpoint, is executed.

Abstract: A method includes determining, for a first thread of execution, a first speculative decoded operands signal and determining, for a second thread of execution, a second speculative decoded operands signal. The method further includes determining, for the first thread of execution, a first constant and determining, for the second thread of execution, a second constant. The method further compares the first speculative decoded operands signal to the second speculative decoded operands signal and uses the first and second constant to detect a wordline collision for accessing the memory array.

Abstract: Techniques are disclosed to identify concurrently used applications based on application state. Upon determining that usage of a plurality of applications, including a first state of a first application of the plurality of applications, satisfies a criterion for identifying concurrently used applications, the plurality of applications is designated as a first meta-application having a uniquely identifiable set of concurrently used applications. The first meta-application has an associated criterion for launching the first meta-application. Upon determining that the criterion for launching the first meta-application is satisfied, at least one of the plurality of applications is programmatically invoked.

Abstract: A method for memory space management in a multitasking capable data processing system including a data processing device and software running thereon. The data processing device includes at least one central processing unit (CPU) and at least one user memory, and the software running on the CPU includes a first computer program application and at least a second computer program application which respectively jointly access the user memory used by both computer program applications during execution. Information of the first computer program application is stored in at least a portion of the memory space of the user memory in a temporary manner, and the integrity of the contents memory space is checked after interrupting the execution of the first computer program application. The first computer program application is only executed further when the memory integrity is confirmed through the checking or when the memory integrity has been reestablished.

Abstract: The present invention discloses method and device for executing multi-tasks by a microcontroller of an electronic cigarette. The method includes these steps: determining tasks to be executed by the microcontroller and an allowed time interval between two executions of each of the tasks; dividing executing time of each task into a plurality of time slices in orderly, and making the sum of the time slices of each task to be less than or equal to the minimum value of all of the time interval; setting a status bit for each task, and directing the status bit to the time slice of the task; executing each task according to a time slice corresponding to the current status bit of the task, and switching to a next task while the time slice corresponding to the current status bit ends.