With Heterogeneous Nanostructures Patents (Class 977/790)
  • Patent number: 8536015
    Abstract: In accordance with aspects of the invention, a method of forming a metal-insulator-metal stack is provided. The method includes forming a first conducting layer, forming a resistivity-switching carbon-based material above the first conducting layer, and forming a second conducting layer above the carbon-based material, wherein the carbon-based material has a thickness of not more than ten atomic layers. Other aspects are also described.
    Type: Grant
    Filed: January 17, 2012
    Date of Patent: September 17, 2013
    Assignee: SanDisk 3D LLC
    Inventors: Roy E. Scheuerlein, Alper Ilkbahar, April D. Schricker
  • Patent number: 8512846
    Abstract: Methods for fabricating sublithographic, nanoscale microstructures in two-dimensional square and rectangular arrays utilizing self-assembling block copolymers, and films and devices formed from these methods are provided.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: August 20, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Dan B. Millward
  • Patent number: 8394483
    Abstract: Methods for fabricating sublithographic, nanoscale microstructures in two-dimensional square and rectangular arrays utilizing self-assembling block copolymers, and films and devices formed from these methods are provided.
    Type: Grant
    Filed: January 24, 2007
    Date of Patent: March 12, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Dan B. Millward
  • Patent number: 8247292
    Abstract: A method of making a uniform nanoparticle array, including performing diblock copolymer thin film self assembly over a first dielectric on silicon, creating a porous polymer film, transferring a pattern into the first dielectric, selectively growing epitaxial silicon off a silicon substrate from within pores to create a silicon nanoparticle array.
    Type: Grant
    Filed: April 27, 2011
    Date of Patent: August 21, 2012
    Assignee: International Business Machines Corporation
    Inventors: Charles T. Black, Kathryn Wilder Guarini
  • Patent number: 8110476
    Abstract: In accordance with aspects of the invention, a method of forming a memory cell is provided, the method including forming a steering element above a substrate, and forming a memory element coupled to the steering element, wherein the memory element comprises a carbon-based material having a thickness of not more than ten atomic layers. The memory element may be formed by repeatedly performing the following steps: forming a layer of a carbon-based material, the layer having a thickness of about one monolayer, and subjecting the layer of carbon-based material to a thermal anneal. Other aspects are also described.
    Type: Grant
    Filed: April 6, 2009
    Date of Patent: February 7, 2012
    Assignee: SanDisk 3D LLC
    Inventors: Roy E. Scheuerlein, Alper Ilkbahar, April D. Shricker
  • Patent number: 8101261
    Abstract: Methods for fabricating sublithographic, nanoscale microstructures in one-dimensional arrays utilizing self-assembling block copolymers, and films and devices formed from these methods are provided.
    Type: Grant
    Filed: February 13, 2008
    Date of Patent: January 24, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Dan B. Millward, Karl Stuen
  • Patent number: 7875884
    Abstract: A hetero-crystalline device structure and a method of making the same include a first layer and a nanostructure integral to a crystallite in the first layer. The first layer is a non-single crystalline material. The nanostructure is a single crystalline material. The nanostructure is grown on the first layer integral to the crystallite using epitaxial growth.
    Type: Grant
    Filed: September 8, 2009
    Date of Patent: January 25, 2011
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Nobuhiko Kobayashi, Shih Yuan Wang
  • Patent number: 7682449
    Abstract: Disclosed herein are heterostructure semiconductor nanowires. The heterostructure semiconductor nanowires comprise semiconductor nanocrystal seeds and semiconductor nanocrystal wires grown in a selected direction from the surface of the semiconductor nanocrystal seeds wherein the semiconductor nanocrystal seeds have a composition different from that of the semiconductor nanocrystal wires. Further disclosed is a method for producing the heterostructure semiconductor nanowires.
    Type: Grant
    Filed: August 8, 2007
    Date of Patent: March 23, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun Joo Jang, Shin Ae Jun
  • Patent number: 7608530
    Abstract: A hetero-crystalline device structure and a method of making the same include a first layer and a nanostructure integral to a crystallite in the first layer. The first layer is a non-single crystalline material. The nanostructure is a single crystalline material. The nanostructure is grown on the first layer integral to the crystallite using epitaxial growth.
    Type: Grant
    Filed: March 1, 2007
    Date of Patent: October 27, 2009
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Nobuhiko Kobayashi, Shih Yuan Wang