Abstract: The invention relates to a nitride semiconductor LED using a hybrid buffer layer with a minimum lattice mismatch between the buffer layer and the nitride semiconductor and a fabrication method therefor. The fabrication method of a nitride semiconductor LED using a hybrid buffer layer comprises: a first step, in which an AlxGa1-xN (0?x<1) layer is formed over a semiconductor; a second step, in which a crystalline seed layer of a 3D structure and AlOyNz are formed over the substrate, the crystalline seed layer being formed by recrystallizing the substrate with the AlxGa1-xN (0?x<1) layer formed thereover and containing a substance with a general formula of AlxGa1-xN (0?x<1); and a third step, in which the substrate having gone through the second step is subject to heat treatment under NH3 gas atmosphere to form an AlN nano structure, thus forming over the substrate a hybrid buffer layer consisting of the 3D crystalline seed layer and the AlN nano structure.

Abstract: A metal-base transistor is suggested. The transistor comprises a first and a second electrode (2, 6) and base electrode (6) to control current flow between the first and second electrode. The first electrode (2) is made from a semiconduction material. The base electrode (3) is a metal layer deposited on top of the semiconducting material forming the first electrode. According the invention the second electrode is formed by a semiconducting nanowire (6) being in electrical contact with the base electrode (3).

Abstract: Field effect devices having a gate controlled via a nanotube switching element. Under one embodiment, a non-volatile transistor device includes a source region and a drain region of a first semiconductor type of material and each in electrical communication with a respective terminal. A channel region of a second semiconductor type of material is disposed between the source and drain region. A gate structure is disposed over an insulator over the channel region and has a corresponding terminal. A nanotube switching element is responsive to a first control terminal and a second control terminal and is electrically positioned in series between the gate structure and the terminal corresponding to the gate structure. The nanotube switching element is electromechanically operable to one of an open and closed state to thereby open or close an electrical communication path between the gate structure and its corresponding terminal.

Abstract: A spin transistor includes a non-magnetic semiconductor substrate having a channel region, a first area, and a second area. The channel region is between the first and the second areas. The spin transistor also includes a first conductive layer located above the first area and made of a ferromagnetic material magnetized in a first direction; and a second conductive layer located above the second area and made of a ferromagnetic material magnetized in one of the first direction and a second direction that is antiparallel with respect to the first direction. The channel region introduces electron spin between the conductive layers. The spin transistor also includes a gate electrode located between the conductive layers and above the channel region; and a tunnel barrier film located between the non-magnetic semiconductor substrate and at least one of the conductive layers.

Abstract: A field effect transistor and a method for making the same. In one embodiment, the field effect transistor comprises a source; a drain; a gate; at least one carbon nanotube on the gate; and a dielectric layer that coats the gate and a portion of the at least one carbon nanotube, wherein the at least one carbon nanotube has an exposed portion that is not coated with the dielectric layer, and wherein the exposed portion is functionalized with at least one indicator molecule. In other embodiments, the field effect transistor is a biochem-FET.

Abstract: The present invention encompasses an organic field-effect transistor comprising an n-type organic semiconductor formed of a fullerene derivative having a fluorinated alkyl group which is expressed by the following chemical formula (wherein at least any one of R1, R2 and R3 is a perfluoro alkyl group or a partially-fluorinated semifluoro alkyl group each having a carbon number of 1 to 20), and a field-effect transistor production method comprising forming an organic semiconductor layer using the fullerene derivative by a solution process, and subjecting the organic semiconductor layer to a heat treatment in an atmosphere containing nitrogen or argon or in vacuum to provide enhanced characteristics to the organic semiconductor layer. The present invention makes it possible to form an organic semiconductor layer by a solution process and provide an organic field-effect transistor excellent in electron mobility and on-off ratio and capable of operating even in an ambient air atmosphere.

Abstract: This invention provides a substrate structure capable of controlling the threshold voltage of a MOS transistor independently of the substrate concentration and easily suppressing a short channel effect caused by reducing the channel length. A first nanosilicon film formed from nanosilicon grains having the same grain size is formed on a silicon oxide film on the surface of a silicon substrate. A silicon nitride film is formed on the first nanosilicon film. Then, a second nanosilicon film having an average grain size different from that of the first nanosilicon film is formed. A semiconductor circuit device is formed on a thus manufactured nanosilicon semiconductor substrate.

Abstract: According to some embodiments, an article of manufacture comprises a substrate; a molecular layer on the substrate comprising at least one charge storage molecule coupled to the substrate by a molecular linker; a solid barrier dielectric layer directly on the molecular layer; and a conductive layer directly on the solid barrier dielectric layer. In some embodiments, the solid barrier dielectric layer is configured to provide a voltage drop across the molecular layer that is greater than a voltage drop across the solid barrier dielectric layer when a voltage is applied to the conductive layer. In some embodiments, the molecular layer has a thickness greater than that of the solid barrier dielectric layer. The article of manufacture contains no electrolyte between the molecular layer and the conductive layer.

Abstract: An electronic device includes a substrate supporting mobile charge carriers, insulative features formed on the substrate surface to define first and second substrate areas on either side of the insulative features, the first and second substrate areas being connected by an elongate channel defined by the insulative features, the channel providing a charge carrier flow path in the substrate from the first area to the second area, the conductivity between the first and second substrate areas being dependent upon the potential difference between the areas. The mobile charge carriers can be within at least two modes in each of the three dimensions within the substrate. The substrate can be an organic material. The mobile charge carriers can have a mobility within the range 0.01 cm2/Vs to 100 cm2/Vs, and the electronic device may be an RF device. Methods for forming such devices are also described.

Abstract: A plurality of conductive pads (2) are formed on a mounting surface of a mounting board. Conductive pads (11) are formed on a principal surface of a semiconductor chip (10) at positions corresponding to the conductive pads of the mounting board, when the principal surface faces toward the mounting board. A plurality of conductive nanotubes (12) extend from the conductive pads of one of the mounting board and the semiconductor chip. A press mechanism (3) presses the semiconductor chip against the mounting board and restricts a position of the semiconductor chip on the mounting surface to mount the semiconductor chip on the mounting board, in a state that tips of the conductive nanotubes are in contact with the corresponding conductive pads not formed with the conductive nanotubes.

Abstract: A memory device, in particular to a resistively switching memory device such as a Phase Change Random Access Memory (“PCRAM”), with a transistor is disclosed. Further, the invention relates to a method for fabricating a memory device. According one embodiment of the invention, a memory device is provided, having at least one nanowire or nanotube or nanofibre access transistor. In one embodiment, the nanowire or nanotube or nanofibre access transistor directly contacts a switching active material of the memory device. According to an additional embodiment, a memory device includes at least one nanowire or nanotube or nanofibre transistor with a vertically arranged nanowire or nanotube or nanofibre.

Abstract: A transistor device may comprise a source having a first ferromagnetic contact thereto, a drain having a second ferromagnetic contact thereto, an electrically conductive gate positioned over a channel region separating the source and the drain, and an electrically insulating layer disposed between the gate and the channel region. The first and second ferromagnetic contacts have anti-parallel magnetic orientations relative to each other. The electrically insulating layer includes a number of paramagnetic impurities each having two spin states such that electrons interacting with the paramagnetic impurities cause the paramagnetic impurities to flip between the two spin states.

Abstract: A thin film transistor includes a source electrode, a drain electrode, a semiconducting layer, and a gate electrode. The drain electrode is spaced from the source electrode. The semiconducting layer is electrically connected to the source electrode and the drain electrode. The gate electrode is insulated from the source electrode, the drain electrode, and the semiconducting layer by an insulating layer. The at least one of the source electrode, drain electrode, and the gate electrode includes a metallic carbon nanotube layer. The metallic carbon nanotube layer includes a plurality of metallic carbon nanotubes.

Abstract: An apparatus has multiple sets of independently addressable interdigitated nanowires. Nanowires of a set are in electrical communication with other nanowires of the same set and are electrically isolated from nanowires of other sets.

Abstract: Methods and apparatuses for nanoenabled memory devices and anisotropic charge carrying arrays are described. In an aspect, a memory device includes a substrate, a source region of the substrate, and a drain region of the substrate. A population of nanoelements is deposited on the substrate above a channel region, the population of nanolements in one embodiment including metal quantum dots. A tunnel dielectric layer is formed on the substrate overlying the channel region, and a metal migration barrier layer is deposited over the dielectric layer. A gate contact is formed over the thin film of nanoelements. The nanoelements allow for reduced lateral charge transfer. The memory device may be a single or multistate memory device.

Abstract: A nanowire-based device includes the pair of isolated electrodes and a nanowire bridging between respective surfaces of the isolated electrodes of the pair. Specifically, the nanowire-based device having isolated electrodes comprises: a substrate electrode having a crystal orientation; a ledge electrode that is an epitaxial semiconductor having the crystal orientation of the substrate electrode; and a nanowire bridging between respective surfaces of the substrate electrode and the ledge electrode.

Abstract: Random access memory including nanotube switching elements. A memory cell includes first and second nanotube switching elements and an electronic memory. Each nanotube switching element includes conductive terminals, a nanotube article and control circuitry capable of controllably form and unform an electrically conductive channel between the conductive terminals. The electronic memory is a volatile storage device capable of storing a logic state in response to electrical stimulus. In certain embodiment the electronic memory has cross-coupled first and second inverters in electrical communication with the first and second nanotube switching elements. The cell can operate as a normal electronic memory, or can operate in a shadow memory or store mode (e.g., when power is interrupted) to transfer the electronic memory state to the nanotube switching elements. The device may later be operated in a recall mode where the state of the nanotube switching elements may be transferred to the electronic memory.

Abstract: A semiconductor apparatus in which a conducting path formed from organic semiconductor molecules as a material has a novel structure and exhibits high mobility, and a manufacturing method for fabricating the same are provided. Fine particles that include a conductor or a semiconductor and organic semiconductor molecules, are alternately bonded through a functional group at both terminals of the organic semiconductor molecules to form a conducting path in a network form such that the conducting path in the fine particles and the conducting path in the organic semiconductor molecules are two-dimensionally or three-dimensionally linked together.

Abstract: Provided is an electronic device, a field effect transistor having the electronic device, and a method of manufacturing the electronic device and the field effect transistor. The electronic device includes: a substrate; a first electrode and a second electrode which are formed in parallel to each other on the substrate, each of the first electrode and the second electrode comprising two electrode pads separated from each other and a heating element that connect the two electrode pads; a catalyst metal layer formed on the heating element of the first electrode; and a carbon nanotube connected to the second electrode by horizontally growing from the catalyst metal layer; wherein the heating elements are separated from the substrate by etching the substrate under the heating elements of the first and the second electrodes.

Abstract: A nonvolatile semiconductor memory device which can shorten data writing and erasing time, significantly improve the endurance characteristic and be activated with low power consumption includes an insulating layer with electric insulation, wherein, a charge retention layer formed adjacent to a tunnel insulating film contains nano-particles comprised of a compound which is constituted from at least one single-element substance or chemical compound having a particle diameter of at most 5 nm functions as a floating gate, and which are independently dispersed with a density of from 10+12 to 10+14 particles per square centimeter.

Abstract: The invention relates to a method for producing a support comprising nanoparticles (22) for the growth of nanostructures (23), said nanoparticles being organised periodically, the method being characterised in that it comprises the following steps: providing a support comprising, in the vicinity of one of its surfaces, a periodic array of crystal defects and/or stress fields (18), depositing, on said surface, a continuous layer (20) of a first material capable of catalysing the nanostructure growth reaction, fractionating the first material layer (20) by a heat treatment so as to form the first material nanoparticles (22).

Abstract: The invention is directed to a method of forming carbon nanomaterials or semiconductor nanomaterials. The method comprises providing a substrate and attaching a molecular precursor to the substrate. The molecular precursor includes a surface binding group for attachment to the substrate and a binding group for attachment of metal-containing species. The metal-containing species is selected from a metal cation, metal compound, or metal or metal-oxide nanoparticle to form a metallized molecular precursor. The metallized molecular precursor is then subjected to a heat treatment to provide a catalytic site from which the carbon nanomaterials or semiconductor nanomaterials form. The heating of the metallized molecular precursor is conducted under conditions suitable for chemical vapor deposition of the carbon nanomaterials or semiconductor nanomaterials.

Abstract: A locally gated graphene nanostructure is described, along with methods of making and using the same. A graphene layer can include first and second terminal regions separated by a substantially single layer gated graphene nanoconstriction. A local first gate region can be separated from the graphene nanoconstriction by a first gate dielectric. The local first gate region can be capacitively coupled to gate electrical conduction in the graphene nanoconstriction. A second gate region can be separated from the graphene nanoconstriction by a second gate dielectric. The second gate region can be capacitively coupled to provide a bias to a first location in the graphene nanoconstriction and to a second location outside of the graphene nanoconstriction. Methods of making and using locally gated graphene nanostructures are also described.

Abstract: A field ionization device can include a first insulator layer on a first side of a substrate, a conductive gate layer on the first insulator layer, a cavity in the substrate, a portion of first insulator over the cavity, an aperture in the portion of the first insulator layer and the conductive gate layer thereby forming an aperture and aperture sidewall. The device can include a second insulator layer on the aperture sidewall and surface of the cavity, a metallization layer over the second insulator layer, a catalyst layer on the metallization layer, and a carbon nanotube. The cavity can be made by etching a second side of the substrate to near the insulator layer, wherein the second side is opposite the first side. The carbon nanotube can be grown from the catalyst layer. The device can further include a collector located near the carbon nanotube. The conductive gate layer can be biased negative with respect to the carbon nanotube.

Abstract: A functional device includes a pair of electrodes 1 and 4 and a macromolecular structure including a hole-conducting layer 5 and an electron-conducting layer 2. The macromolecular structure includes a first hyperbranched macromolecule and a second hyperbranched macromolecule, at least one of the first hyperbranched macromolecule and the second hyperbranched macromolecule has a hole conductivity or an electron conductivity, one of the hole-conducting layer and the electron-conducting layer includes one of the first hyperbranched macromolecule and the second hyperbranched macromolecule, and the macromolecular structure has a self-assembled structure formed by a non-covalent interaction via the first hyperbranched macromolecule or the second hyperbranched macromolecule in at least one of the hole-conducting layer, the electron-conducting layer and the interface between the hole-conducting layer and the electron-conducting layer.

Abstract: Nanoelectromechanical systems utilizing nanometer-scale assemblies are provided that convert thermal energy into another form of energy that can be used to perform useful work at macroscopic level. Nanometer-scale beams are provided that reduce the velocity of working substance molecules that collide with this nanometer-scale beam by converting some of the kinetic energy of a colliding molecule into kinetic energy of the nanometer-scale beam. In embodiments that operate without a working substance, the thermal vibrations of the beam itself create the necessary beam motion. Automatic switches may be added to realize a regulator such that the nanometer-scale beams only deliver voltages that exceed a particular amount. The output energy of millions of these devices may be efficiently summed together.

Abstract: Disclosed is a carbon nanotube (CNT) thin film having metallic nanoparticles. The CNT thin film includes a plastic transparent substrate and a CNT composition coated on the substrate. The CNT composition includes a CNT and metallic nanoparticles distributed on the CNT surface. The plastic transparent substrate is flexible. The metallic nanoparticles are formed by heating a metallic precursor adsorbed in the CNT surface. A method of manufacturing the CNT thin film having metallic nanoparticles is also disclosed. A CNT-dispersed solution is prepared by mixing a CNT with a dispersant or a dispersion solvent. The CNT-dispersed solution is used to form a CNT thin film. Metallic precursors are implanted in the CNT thin film. Then, a heat-treatment is applied to transform the metallic precursors into metallic particles including metallic nanoparticles.

Abstract: An integrated circuit layout of a carbon nanotube transistor device includes a first and second conductive material. The first conductive material is connected to ends of single-walled carbon nanotubes below (or above) the first conductive material. The second conductive material is not electrically connected to the nanotubes below (or above) the second conductive material. The first conductive material may be metal, and the second conductive material may be polysilicon or metal. The nanotubes are perpendicular to the first conductive material. In one implementation, the first and second conductive materials form interdigitated fingers. In another implementation, the first conductive material forms a serpentine track.

Abstract: An apparatus composed of: (a) a substrate; and (b) a deposited composition comprising a liquid and a plurality of metal nanoparticles with a covalently bonded stabilizer.

Abstract: A tri-gated molecular field effect transistor includes a gate electrode formed on a substrate and having grooves in a source region, a drain region and a channel region, and at least one molecule inserted between the source and drain electrodes in the channel region. The effects of the gate voltage on electrons passing through the channel can be maximized, and a variation gain of current supplied between the source and drain electrodes relative to the gate voltage can be greatly increased. Thus, a molecular electronic circuit having high functionality and reliability can be obtained.

Abstract: Nanotube-based logic circuitry is disclosed. Tri-stating elements add an enable/disable function to the circuitry. The tri-stating elements may be provided by nanotube-based switching devices. In the disabled state, the outputs present a high impedance, i.e., are tri-stated, which state allows interconnection to a common bus or other shared communication lines. In embodiments wherein the components are non-volatile, the inverter state and the control state are maintained in the absence of power. Such an inverter may be used in conjunction with and in the absence of diodes, resistors and transistors or as part of or as a replacement to CMOS, biCMOS, bipolar and other transistor level technologies.

Abstract: A spin transistor includes a first conductive layer that is made of a ferromagnetic material magnetized in a first direction, and functions as one of a source and a drain; a second conductive layer that is made of a ferromagnetic material magnetized in one of the first direction and a second direction that is antiparallel with respect to the first direction, and functions as the other one of the source and the drain. The spin transistor also includes a channel region that is located between the first conductive layer and the second conductive layer, and introduces electron spin between the first conductive layer and the second conductive layer; a gate electrode that is located above the channel region; and a tunnel barrier film that is located between the channel region and at least one of the first conductive layer and the second conductive layer.

Abstract: Indium oxide nanowires are used for determining information about different chemicals or Biologics. Chemicals are absorbed to the surface of the nanowires, and cause the semiconducting characteristics of the Nanowires to change. These changed characteristics are sensed, and used to determine either the presence of the materials and/or the concentration of the materials. The nanowires may be between 10 and 30 nm in diameter, formed using a comparable size particle of catalyst material. The nanowires may then be used as part of the channel of a field effect transistor, and the field effect transistor is itself characterized.

Abstract: Methods and apparatuses for nanoenabled memory devices and anisotropic charge carrying arrays are described. In an aspect, a memory device includes a substrate, a source region of the substrate, and a drain region of the substrate. A population of nanoelements is deposited on the substrate above a channel region, the population of nanolements in one embodiment including metal quantum dots. A tunnel dielectric layer is formed on the substrate overlying the channel region, and a metal migration barrier layer is deposited over the dielectric layer. A gate contact is formed over the thin film of nanoelements. The nanoelements allow for reduced lateral charge transfer. The memory device may be a single or multistate memory device.

Abstract: Artificial dielectrics using nanostructures, such as nanowires, are disclosed. In embodiments, artificial dielectrics using other nanostructures, such as nanorods, nanotubes or nanoribbons and the like are disclosed. The artificial dielectric includes a dielectric material with a plurality of nanowires (or other nanostructures) embedded within the dielectric material. Very high dielectric constants can be achieved with an artificial dielectric using nanostructures. The dielectric constant can be adjusted by varying the length, diameter, carrier density, shape, aspect ratio, orientation and density of the nanostructures. Additionally, a controllable artificial dielectric using nanostructures, such as nanowires, is disclosed in which the dielectric constant can be dynamically adjusted by applying an electric field to the controllable artificial dielectric. A wide range of electronic devices can use artificial dielectrics with nanostructures to improve performance.

Abstract: A memory device using a nanotube cell comprises a plurality of nanotube sub-cell arrays each having a hierarchical bit line structure including a main bit line and a sub-bit line. In the memory device, a nanotube cell array comprising a capacitor and a PNPN nanotube switch which does not require an additional gate control signal is located between a word line and the sub-bit line, so that a cross point cell array is embodied to reduce the whole chip size.

Abstract: The invention relates to a semiconductor device comprising at least two electrodes and at least one nanotube or nanowire, in particular a carbon nanotube or nanowire, the device including at least one semiconductive nanotube or nanowire having at least one region that is covered at least in part by at least one layer of molecules or nanocrystals of at least one photosensitive material, an electrical connection between said two electrodes being made by at least one nanotube, namely said semiconductive nanotube or nanowire and optionally by at least one other nanotube or nanowire.

Abstract: A nano-electrode or nano-wire may be etched centrally to form a gap between nano-electrode portions. The portions may ultimately constitute a single electron transistor. The source and drain formed from the electrode portions are self-aligned with one another. Using spacer technology, the gap between the electrodes may be made very small.

Abstract: A method of fabricating an integrated circuit comprises forming or providing a solution containing carbon nanotubes and forming a metal layer utilizing the solution.

Abstract: The present invention relates generally to sub-microelectronic circuitry, and more particularly to nanometer-scale articles, including nanoscale wires which can be selectively doped at various locations and at various levels. In some cases, the articles may be single crystals. The nanoscale wires can be doped, for example, differentially along their length, or radially, and either in terms of identity of dopant, concentration of dopant, or both. This may be used to provide both n-type and p-type conductivity in a single item, or in different items in close proximity to each other, such as in a crossbar array. The fabrication and growth of such articles is described, and the arrangement of such articles to fabricate electronic, optoelectronic, or spintronic devices and components.

Abstract: Embodiments of the invention provide a semiconductor component and a method of manufacture thereof. A semiconductor component comprises: a gate electrode layer adjacent a substrate, and a gate dielectric layer adjacent the gate electrode layer. The gate dielectric layer comprises a monolayer of at least one compound, wherein the compound has an aromatic or a condensed aromatic molecular group. The molecular group is capable of ?-? interactions, which stabilize the monolayer. In an embodiment, the semiconductor component is an organic field effect transistor (OFET). In an embodiment of the invention, a method includes forming the monolayer using a liquid phase immersion process.

Abstract: A random access memory cell includes first and second nanotube switching elements and an electronic memory with cross-coupled first and second inverters. Each nanotube switching element includes a nanotube channel element having at least one electrically conductive nanotube, and a set electrode and a release electrode disposed in relation to the nanotube channel element to controllably form and unform an electrically conductive channel between a channel electrode and an output node. Input nodes of the first and second inverters are coupled to the set electrodes and the output nodes of the first and second nanotube switching elements. The cell can operate as a normal electronic memory, or in a shadow memory or store mode to transfer the electronic memory state to the nanotube switching elements. The device may later be operated in a recall mode to transfer the state of the nanotube switching elements to the electronic memory.

Abstract: A bulk-doped semiconductor that is at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers. Such a semiconductor may comprise an interior core comprising a first semiconductor; and an exterior shell comprising a different material than the first semiconductor. Such a semiconductor may be elongated and may have, at any point along a longitudinal section of such a semiconductor, a ratio of the length of the section to a longest width is greater than 4:1, or greater than 10:1, or greater than 100:1, or even greater than 1000:1.

Abstract: New, hybrid vacuum electron devices are proposed, in which the electrons are extracted from the nanotube into vacuum. Each nanotube is either placed on the cathode electrode individually or grown normally to the cathode plane. Arrays of the nanotubes are also considered to multiply the output current. Two- and three-terminal device configurations are discussed. In all the cases considered, the device designs are such that both input and output capacitances are extremely low, while the efficiency of the electron extraction into vacuum is very high, so that the estimated operational frequencies are expected to be in a tera-hertz range. New vacuum triode structure with ballistic electron propagation along the nanotube is also considered.

Abstract: Three trace electromechanical circuits and methods of using same. A circuit includes first and second electrically conductive elements with a nanotube ribbon (or other electromechanical elements) disposed therebetween. An insulative layer is disposed on one of the first and second conductive elements. The nanotube ribbon is movable toward at least one of the first and second electrically conductive elements in response to electrical stimulus applied to at least one of the first and second electrically conductive elements and the nanotube ribbon. Such circuits may be formed into arrays of cells. One of the conductive elements may be used to create an attractive force to cause the nanotube ribbon to contact a conductive element, and the other of the conductive elements may be used to create an attractive force to pull the nanotube ribbon from contact with the contacted conductive element. The electrically conductive traces may be aligned or unaligned with one another.