In A Logic Circuit Patents (Class 977/940)
  • Publication number: 20150100839
    Abstract: The generalized modular redundancy fault tolerance method for combinational circuits utilizes redundancy techniques to improve soft error reliability and is based on probability of occurrence for combinations at the outputs of circuits. The generalized modular redundancy method enhances the reliability of combinational circuits. Types of redundant modules, complexity of voters and single versus multiple outputs protection are explored.
    Type: Application
    Filed: October 7, 2013
    Publication date: April 9, 2015
    Applicant: King Fahd University of Petroleum and Minerals
    Inventors: AIMAN HELMI EL-MALEH, FERAS M. CHIKH OUGHALI
  • Publication number: 20140368234
    Abstract: A device includes a housing, at least two qubits disposed in the housing and a resonator disposed in the housing and coupled to the at least two qubits, wherein the at least two qubits are maintained at a fixed frequency and are statically coupled to one another via the resonator, wherein energy levels |03> and |12> are closely aligned, wherein a tuned microwave signal applied to the qubit activates a two-qubit phase interaction.
    Type: Application
    Filed: September 2, 2014
    Publication date: December 18, 2014
    Inventors: Jerry M. Chow, Jay M. Gambetta, Seth T. Merkel, Chad T. Rigetti, Matthias Steffen
  • Patent number: 8872547
    Abstract: A nanomagnetic logic gate arranged on a substrate according to an embodiment includes at least one nanomagnetic first structure, at least one nanomagnetic second structure and at least two layers including a first layer and a second layer, wherein at least one first structure is arranged in the first layer on or parallel to a main surface of the substrate, wherein at least one second structure is arranged in the second layer parallel to the first layer, and wherein at least one second structure includes an artificial nucleation center arranged such that a magnetic field component essentially perpendicular to the main surface provided by at least one first structure couples to the artificial nucleation center such that a magnetization of the second structure is changeable in response to the magnetic field component coupled into the artificial nucleation center, when a predetermined condition is fulfilled.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: October 28, 2014
    Assignee: Technische Universitaet Muenchen
    Inventors: Markus Becherer, Josef Kiermaier, Stephen Breitkreutz, Irina Eichwald, Doris Schmitt-Landsiedel
  • Patent number: 8773882
    Abstract: Certain embodiments of the present invention are directed to a method of programming nanowire-to-conductive element electrical connections. The method comprises: providing a substrate including a number of conductive elements overlaid with a first layer of nanowires, at least some of the conductive elements electrically coupled to more than one of the nanowires through individual switching junctions, each of the switching junctions configured in either a low-conductance state or a high-conductance state; and switching a portion of the switching junctions from the low-conductance state to the high-conductance state or the high-conductance state to the low-conductance state so that individual nanowires of the first layer of nanowires are electrically coupled to different conductive elements of the number of conductive elements using a different one of the switching junctions configured in the high-conductance state.
    Type: Grant
    Filed: April 15, 2010
    Date of Patent: July 8, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Zhiyong Li, Warren Robinett
  • Patent number: 8698517
    Abstract: A computing multi-magnet device and method for solving complex computational problems is provided. Embodiments include a first magnet, a second magnet, and an interconnect between and interconnecting the first and second magnets, the interconnect configured to allow the first and second magnets to communicate via a voltage or current applied to the first and second magnet and conducted by the interconnect. The scalability of computing multi-magnet device provides solutions to algorithms that have exponentially increasing complexity.
    Type: Grant
    Filed: August 13, 2012
    Date of Patent: April 15, 2014
    Assignee: GlobalFoundries Inc.
    Inventor: Behtash Behin-Aein
  • Patent number: 8664091
    Abstract: A method for removing a metallic nanotube, which is formed on a substrate in a first direction, includes forming a plurality of conductors in a second direction crossing the first direction, electrically contacting the plurality of conductors with metallic nanotube, respectively, forming at least two voltage-applying electrodes on the conductors, each of which electrically contacting at least one of the conductors, and applying voltages to at least some of the conductors through the voltage-applying electrodes, respectively. Among the conductors to which the voltages are respectively applied, every two adjacent conductors have an electrical potential difference created therebetween, so as to burn out the metallic nanotube.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: March 4, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huilong Zhu, Zhijiong Luo, Haizhou Yin
  • Patent number: 8659940
    Abstract: Physical neural networks based nanotechnology include dendrite circuits that comprise non-volatile nanotube switches. A first terminal of the non-volatile nanotube switches is able to receive an electrical signal and a second terminal of the non-volatile nanotube switches is coupled to a common node that sums any electrical signals at the first terminals of the nanotube switches. The neural networks further includes transfer circuits to propagate the electrical signal, synapse circuits, and axon circuits.
    Type: Grant
    Filed: March 25, 2009
    Date of Patent: February 25, 2014
    Assignee: Nantero Inc.
    Inventors: Claude L. Bertin, Brent M. Segal, Darren K. Brock
  • Patent number: 8631562
    Abstract: An electrostatic discharge (ESD) protection circuit for protecting a protected circuit is coupled to an input pad. The ESD circuit includes a nanotube switch electrically having a control. The switch is coupled to the protected circuit and to a discharge path. The nanotube switch is controllable, in response to electrical stimulation of the control, between a de-activated state and an activated state. The activated state creates a current path so that a signal on the input pad flows to the discharge path to cause the signal at the input pad to remain within a predefined operable range for the protected circuit. The nanotube switch, the input pad, and the protected circuit may be on a semiconductor chip. The nanotube switch may be on a chip carrier. The deactivated and activated states may be volatile or non-volatile depending on the embodiment.
    Type: Grant
    Filed: November 23, 2010
    Date of Patent: January 21, 2014
    Assignee: Nantero Inc.
    Inventors: Claude L. Bertin, Brent M. Segal, Thomas Rueckes, Jonathan W. Ward
  • Patent number: 8558571
    Abstract: Illustrative embodiments of all-spin logic devices, circuits, and methods are disclosed. In one embodiment, an all-spin logic device may include a first nanomagnet, a second nanomagnet, and a spin-coherent channel extending between the first and second nanomagnets. The spin-coherent channel may be configured to conduct a spin current from the first nanomagnet to the second nanomagnet to determine a state of the second nanomagnet in response to a state of the first nanomagnet.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: October 15, 2013
    Assignee: Purdue Research Foundation
    Inventors: Behtash Behin-Aein, Srikant Srinivasan, Angik Sarkar, Supriyo Datta, Sayeef Salahuddin
  • Patent number: 8509584
    Abstract: A nano-electron fluidic logic (NFL) device for controlling launching and propagation of at least one surface plasma wave (SPW) is disclosed. The NFL device comprises a metallic gate patterned with a plurality of terminals at which SPWs may be launched and a plurality of drain terminals a which the SPWs may be detected. A wave guiding structure such as a 2 DEG EF facilitates propagation of the SPW within the structure so as to scatter/steer the SPW in a direction different from a pre-scattering direction. A bias SPW is excited by an application of a control SPW with a momentum vector at an angle to the bias SPW and a control current with a wavevector which scatters the bias SPW in the direction of at least one output SPW, towards a drain terminal. The NFL device is rendered with device speed as a function of SPW propagation velocity.
    Type: Grant
    Filed: April 29, 2009
    Date of Patent: August 13, 2013
    Inventor: Hector J. De Los Santos
  • Patent number: 8415968
    Abstract: The present disclosure relates to methods and systems for data tag control for quantum dot cellular automata (QCA). An example method includes receiving data, associating a data tag with the data, communicating the data tag along a first wire-like element to a local tag decoder, reading instructions from the data tag using the local tag decoder, communicating the instructions to a processing element, communicating the data along a second wire-like element to the processing element, and processing the data with the processing element according to the instructions. A length of the first wire-like elements and a length of the second wire-like element are approximately the same such that communication of the instructions and the data to the processing element are synchronized.
    Type: Grant
    Filed: July 30, 2010
    Date of Patent: April 9, 2013
    Assignee: The Board of Regents of the University of Texas System
    Inventors: Earl E. Swartzlander, Jr., Inwook Kong
  • Patent number: 8358153
    Abstract: A magnetic circuit in one aspect comprises a plurality of tapered magnetic wires each having a relatively wide input end and a relatively narrow output end, with the output end of a first one of the tapered magnetic wires being coupled to the input end of a second one of the tapered magnetic wires. Each of the tapered magnetic wires is configured to propagate a magnetic domain wall along a length of the wire in a direction of decreasing width from its input end to its output end. In an illustrative embodiment, the magnetic circuit comprises a logic buffer that includes at least one heating element. The heating element may be controlled to facilitate transfer of a magnetic moment from the output end of the first tapered magnetic wire to the input end of the second tapered magnetic wire.
    Type: Grant
    Filed: May 19, 2010
    Date of Patent: January 22, 2013
    Assignee: International Business Machines Corporation
    Inventors: Daniel Christopher Worledge, David William Abraham
  • Patent number: 8324940
    Abstract: An inverter device includes a first nanowire connected to a voltage source node and a ground node, a first p-type field effect transistor (pFET) device having a gate disposed on the first nanowire, and a first n-type field effect transistor (nFET) device having a gate disposed on the first nanowire.
    Type: Grant
    Filed: April 13, 2010
    Date of Patent: December 4, 2012
    Assignee: International Business Machines Corporation
    Inventors: Sarunya Bangsaruntip, Guy Cohen, Amlan Majumdar, Jeffrey W. Sleight
  • Publication number: 20120278650
    Abstract: Methods, apparatus and articles of manufacture for controlling nanostore operation based on monitored performance are disclosed. An example method disclosed herein comprises monitoring performance of a nanostore, the nanostore including compute logic and a datastore accessible via the compute logic, and controlling operation of the nanostore in response to detecting a performance indicator associated with wearout of the compute logic to permit the compute logic to continue to access the datastore.
    Type: Application
    Filed: April 29, 2011
    Publication date: November 1, 2012
    Inventors: Naveen Muralimanohar, Parthasarathy Ranganathan, Jichuan Chang
  • Patent number: 8299520
    Abstract: According to some embodiments, a semiconductor device includes first and second auxiliary gate electrodes and a semiconductor layer crossing the first and second auxiliary gate electrodes. A primary gate electrode is provided on the semiconductor layer so that the semiconductor layer is between the primary gate electrode and the first and second auxiliary gate electrodes. Moreover, the first and second auxiliary gate electrodes are configured to induce respective first and second field effect type source/drain regions in the semiconductor layer. Related methods are also discussed.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: October 30, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Suk-pil Kim, Yoon-dong Park, Jae-young Choi, June-mo Koo, Byung-hee Hong
  • Publication number: 20120176154
    Abstract: Illustrative embodiments of all-spin logic devices, circuits, and methods are disclosed. In one embodiment, an all-spin logic device may include a first nanomagnet, a second nanomagnet, and a spin-coherent channel extending between the first and second nanomagnets. The spin-coherent channel may be configured to conduct a spin current from the first nanomagnet to the second nanomagnet to determine a state of the second nanomagnet in response to a state of the first nanomagnet.
    Type: Application
    Filed: January 6, 2012
    Publication date: July 12, 2012
    Inventors: Behtash Behin-Aein, Srikant Srinivasan, Angik Sarkar, Supriyo Datta, Sayeef Salahuddin
  • Publication number: 20120132898
    Abstract: The present invention relates to compositions comprising functionalized or un-functionalized multi cyclic hydrocarbons and functional organic compounds, which can be used in different electronic devices. The invention further relates to an electronic device comprising one or more organic functional layers, wherein at least one of the layers comprises at least one functionalized or un-functionalized multi cyclic hydrocarbon. Another embodiment of the present invention relates to a formulation comprising functionalized or un-functionalized multi cyclic hydrocarbons, from which a thin layer comprising at least one functionalized or un-functionalized multi cyclic hydrocarbon can be formed.
    Type: Application
    Filed: July 7, 2010
    Publication date: May 31, 2012
    Applicant: Merck Patent GmbH
    Inventors: Junyou Pan, Thomas Eberle, Herwig Buchholz
  • Patent number: 8188763
    Abstract: Field programmable device (FPD) chips with large logic capacity and field programmability that are in-circuit programmable are described. FPDs use small versatile nonvolatile nanotube switches that enable efficient architectures for dense low power and high performance chip implementations and are compatible with low cost CMOS technologies and simple to integrate.
    Type: Grant
    Filed: August 6, 2009
    Date of Patent: May 29, 2012
    Assignee: Nantero, Inc.
    Inventors: Claude L. Bertin, Brent M. Segal
  • Patent number: 8138491
    Abstract: A self-aligned carbon-nanotube field effect transistor semiconductor device comprises a carbon-nanotube deposited on a substrate, a source and a drain formed at a first end and a second end of the carbon-nanotube, respectively, and a gate formed substantially over a portion of the carbon-nanotube, separated from the carbon-nanotube by a dielectric film.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: March 20, 2012
    Assignee: International Business Machines Corporation
    Inventors: Joerg Appenzeller, Phaedon Avouris, Kevin K. Chan, Philip G. Collins, Richard Martel, Hon-Sum Philip Wong
  • Publication number: 20110286255
    Abstract: A magnetic circuit in one aspect comprises a plurality of tapered magnetic wires each having a relatively wide input end and a relatively narrow output end, with the output end of a first one of the tapered magnetic wires being coupled to the input end of a second one of the tapered magnetic wires. Each of the tapered magnetic wires is configured to propagate a magnetic domain wall along a length of the wire in a direction of decreasing width from its input end to its output end. In an illustrative embodiment, the magnetic circuit comprises a logic buffer that includes at least one heating element. The heating element may be controlled to facilitate transfer of a magnetic moment from the output end of the first tapered magnetic wire to the input end of the second tapered magnetic wire.
    Type: Application
    Filed: May 19, 2010
    Publication date: November 24, 2011
    Applicant: International Business Machines Corporation
    Inventors: Daniel Christopher Worledge, David William Abraham
  • Patent number: 8063455
    Abstract: A multi-terminal electromechanical nanoscopic switching device which may be used as a memory device, a pass gate, a transmission gate, or a multiplexer, among other things.
    Type: Grant
    Filed: November 22, 2005
    Date of Patent: November 22, 2011
    Assignee: Agate Logic, Inc.
    Inventors: Louis Charles Kordus, II, Colin Neal Murphy, Malcolm John Wing
  • Patent number: 8058906
    Abstract: A non-majority magnetic logic gate device for use in constructing compact and power efficient logical magnetic arrays is presented. The non-majority magnetic logic gate device includes a substrate, symmetrically aligned magnetic islands (SAMIs), at least one misaligned magnetic island (MAMI), magnetic field inputs (MFIs), and at least one magnetic field output (MFO). The SAMIs and MAMI are electrically isolated from each other but are magnetically coupled to one another through their respective magnetic fringe fields. The MAMI is geometrically and/or angularly configured to exhibit a magnetization ground state bias which is dependent upon which direction the applied magnetic clock field is swept. Non-majority logic gates can be made from layouts containing the SAMIs and the MAMI which contain a smaller number of components as comparable majority logic gate layouts.
    Type: Grant
    Filed: June 16, 2010
    Date of Patent: November 15, 2011
    Assignee: The University of Notre Dame Du Lac
    Inventors: Michael T. Niemier, Mohammad T. Alam, Gary H. Bernstein, Xiaobo Sharon Hu, Wolfgang Porod, Edit Varga
  • Patent number: 7990751
    Abstract: A nanogap switching element is equipped with an inter-electrode gap portion including a gap of a nanometer order between a first electrode and a second electrode. A switching phenomenon is caused in the inter-electrode gap portion by applying a voltage between the first and second electrodes. The nanogap switching element is shifted from its low resistance state to its high resistance state by receiving a voltage pulse application of a first voltage value, and shifted from its high resistance state to its low resistance state by receiving a voltage pulse application of a second voltage value lower than the first voltage value. When the nanogap switching element is shifted from the high resistance state to the low resistance state, a voltage pulse of an intermediate voltage value between the first and second voltage values is applied thereto before the voltage pulse application of the second voltage value thereto.
    Type: Grant
    Filed: December 18, 2008
    Date of Patent: August 2, 2011
    Assignees: Funai Electric Advanced Applied Technology Research Institute Inc., National Institute of Advanced Industrial Science and Technology, Funai Electric Co., Ltd.
    Inventors: Yuichiro Masuda, Shigeo Furuta, Tsuyoshi Takahashi, Tetsuo Shimizu, Yasuhisa Naitoh, Masayo Horikawa
  • Publication number: 20110181307
    Abstract: In one embodiment of the present invention, a microscale or sub-microscale signal line, interconnected with one set of parallel nanowires of a nanowire crossbar, serves as a multiplexer. The multiplexer is used to detect the conductivity state of a nanowire junction within the nanowire crossbar. In one method embodiment of the present invention, a first signal is output to the two nanowires interconnected by the nanowire junction, while a second signal is output to the remaining nanowires of the nanowire crossbar. Then, the second signal is output to the two nanowires interconnected by the nanowire junction, while the first signal is output to the remaining nanowires of the nanowire crossbar. The resulting signal detected on the multiplexer is reflective of the conductivity state of the nanowire junction.
    Type: Application
    Filed: March 5, 2009
    Publication date: July 28, 2011
    Inventor: Philip J. Kuekes
  • Patent number: 7985906
    Abstract: Nanotube-based switching elements and logic circuits are disclosed. Under one embodiment of the invention, a Boolean logic circuit includes at least one input terminal and an output terminal, and a network of nanotube switching elements electrically disposed between said at least one input terminal and said output terminal. The network of nanotube switching elements effectuates a Boolean function transformation of Boolean signals on said at least one input terminal. The Boolean function transformation includes a Boolean inversion within the function, such as a NOT or NOR function.
    Type: Grant
    Filed: November 22, 2010
    Date of Patent: July 26, 2011
    Assignee: Nantero, Inc.
    Inventors: Claude L. Bertin, Thomas Rueckes, Brent M. Segal
  • Publication number: 20110147709
    Abstract: A chain of field coupled nanomagnets includes at least one elements having substantially different anisotropy energy from that of the other nanomagnets. A signal can propagate from a first input nanomagnet having a relatively high anisotropy energy through the chain to an output nanomagnet. The output nanomagnet may have a relatively lower anisotropy energy than the other nanomagnets. Signal flow direction thus can be controlled. The higher anisotropy energy nanomagnet may be attained by use of a ferromagnet material having a higher anisotropy constant and/or configured with a larger volume than the other elements. The lower anisotropy energy magnet may be attained by use of a ferromagnet material having a lower anisotropy constant and/or configured with a smaller volume than the other elements. Logic signal flow control can also be attained making use of three dimensional geometries of nanomagnets with two different orientations.
    Type: Application
    Filed: December 22, 2009
    Publication date: June 23, 2011
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: An Chen, Zoran Krivokapic
  • Publication number: 20110102014
    Abstract: A three-dimensional semiconductor device, comprising: a first module layer having a plurality of circuit blocks; and a second module layer positioned substantially above the first module layer, including a plurality of configuration circuits; and a third module layer positioned substantially above the second module layer, including a plurality of circuit blocks; wherein, the configuration circuits in the second module control a portion of the circuit blocks in the first and third module layers.
    Type: Application
    Filed: July 12, 2010
    Publication date: May 5, 2011
    Inventor: Raminda Udaya Madurawe
  • Patent number: 7932543
    Abstract: Provided are a wire structure and a semiconductor device having the wire structure. The wire structure includes a first wire that has a first region having a width of several to tens of nanometers and a second region having a width wider than that of the first region.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: April 26, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-jun Choi, Jung-hyun Lee, Hyung-jin Bae, Chang-soo Lee
  • Publication number: 20110062993
    Abstract: Nanotube-based switching elements and logic circuits are disclosed. Under one embodiment of the invention, a Boolean logic circuit includes at least one input terminal and an output terminal, and a network of nanotube switching elements electrically disposed between said at least one input terminal and said output terminal. The network of nanotube switching elements effectuates a Boolean function transformation of Boolean signals on said at least one input terminal. The Boolean function transformation includes a Boolean inversion within the function, such as a NOT or NOR function.
    Type: Application
    Filed: November 22, 2010
    Publication date: March 17, 2011
    Applicant: Nantero, Inc.
    Inventors: Claude L. Bertin, Thomas Rueckes, Brent M. Segal
  • Patent number: 7902867
    Abstract: A device includes an array of electrodes configured for attachment in or on the human head interconnected to control circuitry via a programmable crossbar signal processor having reconfigurable resistance states. In various embodiments the device may be used as a controller for a video game console, a robotic prosthesis, a portable electronic device, or a motor vehicle.
    Type: Grant
    Filed: February 19, 2009
    Date of Patent: March 8, 2011
    Inventor: Blaise Laurent Mouttet
  • Patent number: 7897960
    Abstract: A self-aligned carbon-nanotube field effect transistor semiconductor device comprises a carbon-nanotube deposited on a substrate, a source and a drain formed at a first end and a second end of the carbon-nanotube, respectively, and a gate formed substantially over a portion of the carbon-nanotube, separated from the carbon-nanotube by a dielectric film.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: March 1, 2011
    Assignee: International Business Machines Corporation
    Inventors: Joerg Appenzeller, Phaedon Avouris, Kevin K. Chan, Philip G. Collins, Richard Martel, Hon-Sum Philip Wong
  • Patent number: 7880496
    Abstract: A novel conservative gate especially suiting a Quantum Dot Cellular Automata (QCA) majority voter-based design. The input-to-output mapping of the novel conservative QCA (CQCA) gate is: P=A; Q=AB+BC+AC [MV(A,B,C)]; R=A?B+A?C+BC [MV(A?,B,C)], where A, B, C are inputs and P, Q, R are outputs, respectively. A method of transferring information in a quantum-dot cellular automata device is also provided.
    Type: Grant
    Filed: February 9, 2010
    Date of Patent: February 1, 2011
    Assignee: University of South Florida
    Inventors: Nagarajan Ranganathan, Himanshu Thapliyal
  • Patent number: 7852114
    Abstract: Field programmable device (FPD) chips with large logic capacity and field programmability that are in-circuit programmable are described. FPDs use small versatile nonvolatile nanotube switches that enable efficient architectures for dense low power and high performance chip implementations and are compatible with low cost CMOS technologies and simple to integrate.
    Type: Grant
    Filed: August 6, 2009
    Date of Patent: December 14, 2010
    Assignee: Nantero, Inc.
    Inventors: Claude L. Bertin, Brent M. Segal
  • Patent number: 7847588
    Abstract: Field programmable device (FPD) chips with large logic capacity and field programmability that are in-circuit programmable are described. FPDs use small versatile nonvolatile nanotube switches that enable efficient architectures for dense low power and high performance chip implementations and are compatible with low cost CMOS technologies and simple to integrate.
    Type: Grant
    Filed: August 6, 2009
    Date of Patent: December 7, 2010
    Assignee: Nantero, Inc.
    Inventor: Claude L. Bertin
  • Patent number: 7839176
    Abstract: Nanotube-based switching elements and logic circuits. Under one embodiment of the invention, a switching element includes an input node, an output node, a nanotube channel element having at least one electrically conductive nanotube, and a control electrode. The control electrode is disposed in relation to the nanotube channel element to controllably form an electrically conductive channel between the input node and the output node. The channel at least includes said nanotube channel element. The output node is constructed and arranged so that channel formation is substantially unaffected by the electrical state of the output node. Under another embodiment of the invention, the control electrode is arranged in relation to the nanotube channel element to form said conductive channel by causing electromechanical deflection of said nanotube channel element.
    Type: Grant
    Filed: June 2, 2009
    Date of Patent: November 23, 2010
    Assignee: Nantero, Inc.
    Inventors: Claude L. Bertin, Thomas Rueckes, Brent M. Segal
  • Publication number: 20100283502
    Abstract: Asynchronous nanoelectronic circuits that operate according to principles of quasi-delay insensitive design are described. Circuit or logic elements comprising n-type devices are fabricated in a first n-plane, p-type devices are fabricated in a p-plane, and connections are formed in a routing plane of a compute tile. A state-holding element comprising a selected one of a C-element, a precharge function-block, and a read-write register is described. The state-holding element can hold a value of an output of a logic element during a time when the output is disconnected from a reference voltage. Isochronic forks having an adversary path designed to make state transitions safe are explained.
    Type: Application
    Filed: November 14, 2007
    Publication date: November 11, 2010
    Applicant: California Institute of Technology.
    Inventors: Alain J. Martin, Piyush Prakash
  • Patent number: 7768304
    Abstract: Nanotube-based logic circuitry is disclosed. Tri-stating elements add an enable/disable function to the circuitry. The tri-stating elements may be provided by nanotube-based switching devices. In the disabled state, the outputs present a high impedance, i.e., are tri-stated, which state allows interconnection to a common bus or other shared communication lines. In embodiments wherein the components are non-volatile, the inverter state and the control state are maintained in the absence of power. Such an inverter may be used in conjunction with and in the absence of diodes, resistors and transistors or as part of or as a replacement to CMOS, biCMOS, bipolar and other transistor level technologies.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: August 3, 2010
    Assignee: Nantero, Inc.
    Inventor: Claude L. Bertin
  • Patent number: 7759996
    Abstract: Data storage circuits and components of such circuits constructed using nanotube switching elements. The storage circuits may be stand-alone devices or cells incorporated into other devices or circuits. The data storage circuits include or can be used in latches, master-slave flip-flops, digital logic circuits, memory devices and other circuits. In one aspect of the invention, a master-slave flip-flop is constructed using one or more nanotube switching element-based storage devices. The master storage element or the slave storage element or both may be constructed using nanotube switching elements, for example, using two nanotube switching element-based inverters. The storage elements may be volatile or non-volatile. An equilibration device is provided for protecting the stored data from fluctuations on the inputs. Input buffers and output buffers for data storage circuits of the invention may also be constructed using nanotube switching elements.
    Type: Grant
    Filed: June 26, 2008
    Date of Patent: July 20, 2010
    Assignee: Nantero, Inc.
    Inventor: Claude L. Bertin
  • Publication number: 20100171525
    Abstract: A hybrid resistor/FET-logic demultiplexer (demux) is provided. According to an embodiment, hybrid nanoelectronics, which incorporate nanodevice crossbars on CMOS backplane circuits, can be implemented using the subject demux as the interface between the nanowires in the nanodevice crossbars and the microwires fabricated in the CMOS domain. Embodiments of the present invention incorporate resistor-logic and FET-logic to realize the demultiplexing function. In various embodiments, a single column of p-type FETs is used to convert the linear voltage output of a resistor-logic demux core into a nonlinear output so that the desired demultiplexing function can be much better approximated. The resistor-logic demux core design can still be optimized using constant weight codes, whereas the optimization constraint on the constant weight code construction is largely relaxed, which can result in a more area efficient demux.
    Type: Application
    Filed: December 12, 2008
    Publication date: July 8, 2010
    Inventors: Tong Zhang, Shu Li
  • Patent number: 7719318
    Abstract: A nanoelectromechanical (NEM) switch is formed on a substrate with a source electrode containing a suspended electrically-conductive beam which is anchored to the substrate at each end. This beam, which can be formed of ruthenium, bows laterally in response to a voltage applied between a pair of gate electrodes and the source electrode to form an electrical connection between the source electrode and a drain electrode located near a midpoint of the beam. Another pair of gate electrodes and another drain electrode can be located on an opposite side of the beam to allow for switching in an opposite direction. The NEM switch can be used to form digital logic circuits including NAND gates, NOR gates, programmable logic gates, and SRAM and DRAM memory cells which can be used in place of conventional CMOS circuits, or in combination therewith.
    Type: Grant
    Filed: November 5, 2008
    Date of Patent: May 18, 2010
    Assignee: Sandia Corporation
    Inventors: Christopher D. Nordquist, David A. Czaplewski
  • Publication number: 20100116631
    Abstract: A non-volatile bistable nano-electromechanical switch is provided for use in memory devices and microprocessors. The switch employs carbon nanotubes as the actuation element. A method has been developed for fabricating nanoswitches having one single-walled carbon nanotube as the actuator. The actuation of two different states can be achieved using the same low voltage for each state.
    Type: Application
    Filed: April 9, 2008
    Publication date: May 13, 2010
    Applicant: NORTHEASTERN UNIVERSITY
    Inventors: Sivasubramanian Somu, Ahmed Busnaina, Nicol McGruer, Peter Ryan, George G. Adams, Xugang Xiong, Taehoon Kim
  • Patent number: 7710157
    Abstract: Boolean logic circuits comprising nanotube-based switching elements with multiple controls. The Boolean logic circuits include input and output terminals and a network of nanotube switching elements electrically disposed between said at least one input terminal and said output terminal. Each switching element includes an input node, an output node, and a nanotube channel element having at least one electrically conductive nanotube. A control structure is disposed in relation to the nanotube channel element to controllably form and unform an electrically conductive channel along the nanotube channel element. At least one nanotube switching element non-volatilely retains an informational state and at least one nanotube switching elements volatilely retains an informational state. The network of nanotube switching elements effectuates a Boolean function transformation of Boolean signals on said at least one input terminal.
    Type: Grant
    Filed: October 6, 2008
    Date of Patent: May 4, 2010
    Assignee: Nantero, Inc.
    Inventors: Claude L. Bertin, Thomas Rueckes, Brent M. Segal
  • Publication number: 20100106348
    Abstract: Systems, methods and apparatus are provided through which in some embodiments an autonomic entity manages a system by generating one or more stay alive signals based on the functioning status and operating state of the system. In some embodiments, an evolvable synthetic neural system is operably coupled to one or more evolvable synthetic neural systems in a hierarchy. The evolvable neural interface receives and generates heartbeat monitor signals and pulse monitor signals that are used to generate a stay alive signal that is used to manage the operations of the synthetic neural system. In another embodiment an asynchronous Alice signal (Autonomic license) requiring valid credentials of an anonymous autonomous agent is initiated. An unsatisfactory Alice exchange may lead to self-destruction of the anonymous autonomous agent for self-protection.
    Type: Application
    Filed: October 21, 2009
    Publication date: April 29, 2010
    Applicant: U.S.A as represented by the Administrator of the National Aeronautics and Space Administration
    Inventors: Michael G. Hinchey, Roy Sterritt
  • Publication number: 20100079165
    Abstract: Field programmable device (FPD) chips with large logic capacity and field programmability that are in-circuit programmable are described. FPDs use small versatile nonvolatile nanotube switches that enable efficient architectures for dense low power and high performance chip implementations and are compatible with low cost CMOS technologies and simple to integrate.
    Type: Application
    Filed: August 6, 2009
    Publication date: April 1, 2010
    Inventors: Claude L. Bertin, Brent M. Segal
  • Publication number: 20100073031
    Abstract: Boolean logic circuits comprising nanotube-based switching elements with multiple controls. The Boolean logic circuits include input and output terminals and a network of nanotube switching elements electrically disposed between said at least one input terminal and said output terminal. Each switching element includes an input node, an output node, and a nanotube channel element having at least one electrically conductive nanotube. A control structure is disposed in relation to the nanotube channel element to controllably form and unform an electrically conductive channel along the nanotube channel element. At least one nanotube switching element non-volatilely retains an informational state and at least one nanotube switching elements volatilely retains an informational state. The network of nanotube switching elements effectuates a Boolean function transformation of Boolean signals on said at least one input terminal.
    Type: Application
    Filed: October 6, 2008
    Publication date: March 25, 2010
    Inventors: Claude L. Bertin, Thomas Rueckes, Brent M. Segal
  • Publication number: 20100072957
    Abstract: Nanotube based logic driver circuits. These include pull-up driver circuits, push-pull driver circuits, tristate driver circuits, among others. Under one embodiment, an off-chip driver circuit includes a differential input having first and second signal links, each coupled to a respective one of two differential, on-chip signals. At least one output link is connectable to an off-chip impedance load, and at least one switching element has an input node, an output node, a nanotube channel element, and a control structure disposed in relation to the nanotube channel element to controllably form and unform an electrically conductive channel between said input node and said output node. The input node is coupled to a reference signal and the control structure is coupled to the first and second signal links. The output node is coupled to the output link, and the channel element is sized to carry sufficient current to drive said off-chip impedance load.
    Type: Application
    Filed: August 31, 2007
    Publication date: March 25, 2010
    Inventor: Claude L. Bertin
  • Patent number: 7679080
    Abstract: A functional molecular device displaying its functions under the action of an electrical field is provided. A Louis base molecule, exhibiting positive dielectric constant anisotropy or exhibiting dipole moment along the long-axis direction of the Louis base molecule, is arrayed in the form of a pendant on an electrically conductive linear or film-shaped principal-axis molecule of a conjugated system, via a metal ion capable of acting as a Louis acid. The resulting structure is changed in conformation on application of an electrical field to exhibit its function. The electrically conductive linear or film-shaped principal-axis molecule and the Louis base molecule form a complex with the metal ion. On application of the electrical field, the Louis base molecule performs a swinging movement or a seesaw movement to switch the electrical conductivity of the principal-axis molecule.
    Type: Grant
    Filed: June 23, 2005
    Date of Patent: March 16, 2010
    Assignees: Sony Corporation, Sony Deutschland G.m.b.H.
    Inventors: Eriko Matsui, Nobuyuki Matsuzawa, Akio Yasuda, Oliver Harnack
  • Patent number: 7663911
    Abstract: Nanotube-based switching elements and logic circuits. Under one embodiment of the invention, a switching element includes an input node, an output node, a nanotube channel element having at least one electrically conductive nanotube, and a control electrode. The control electrode is disposed in relation to the nanotube channel element to controllably form an electrically conductive channel between the input node and the output node. The channel at least includes said nanotube channel element. The output node is constructed and arranged so that channel formation is substantially unaffected by the electrical state of the output node.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: February 16, 2010
    Assignee: Nantero, Inc.
    Inventors: Claude L. Bertin, Thomas Rueckes, Brent M. Segal
  • Patent number: 7649769
    Abstract: Circuit arrays having cells with combinations of transistors and nanotube switches. Under one embodiment, cells are arranged as pairs with the nanotube switching elements of the pair being cross coupled so that the set electrode of one nanotube switching element is coupled to the release electrode of the other and the release electrode of the one nanotube switching element being coupled to the set electrode of the other. The nanotube articles are coupled to the reference line, and the source of one field effect transistor of a pair is coupled to the set electrode to one of the two nanotube switching elements and the source of the other field effect transistor of the pair is coupled to the release electrode to the one of the two nanotube switching elements.
    Type: Grant
    Filed: November 27, 2007
    Date of Patent: January 19, 2010
    Assignee: Nantero, Inc.
    Inventors: Claude L. Bertin, Thomas Rueckes, Brent M. Segal, Frank Guo
  • Publication number: 20100002276
    Abstract: A system, method, and apparatus for photon logic gates based on quantum switch, where a single or multiple quantum switches are utilized for dark resonance interactions in which three-color lasers interact with a four-level or five-level nonlinear optical medium composed of three ground states and one or two excited states through nondegenerate four-wave mixing processes. The photon logic mechanism is based on combination of single or multiple dark resonance-induced two-photon coherence swapping among the three closely spaced ground states through optical transitions via a common excited state. The two-photon coherence induced on the ground states is optically detected via nondegenerate four-wave mixing processes. The nondegenerate four-wave mixing generation is enhanced owing to dark resonance or electromagnetically induced transparency.
    Type: Application
    Filed: March 7, 2007
    Publication date: January 7, 2010
    Applicant: INHA-INDUSTRY PARTNERSHIP INSTITUTE
    Inventor: Byoung Seung Ham