Abstract: A backlight unit includes an optical sheet, a receiving member configured to receive the optical sheet, the receiving member having a support surface supporting the optical sheet, an extension configured to protrude from a side surface of the optical sheet, an inner surface position defining portion configured to define a location of the optical sheet, the inner surface position defining portion being substantially perpendicular to the support surface of the receiving member and facing an inner surface of the extension, and an outer surface position defining portion substantially perpendicular to the supporting surface of the receiving member and facing an outer surface of the extension, wherein a first distance between the inner surface position defining portion and the inner surface of the extension is less than a second distance between the outer surface position defining portion and the outer surface of the extension.

Abstract: A thin film transistor array panel includes: a substrate, a gate line disposed on the substrate, a data line intersecting the gate line, a drain electrode separated from the data line a first insulating layer covering the data line, a color filter disposed on the first insulating layer, a second insulating layer disposed on the color filter and having a contact hole exposing the drain electrode and the color filter and a pixel electrode disposed on the second insulating layer and connected to the drain electrode through the contact hole. The contact hole partially exposes the color filter near a portion where the drain electrode and the pixel electrode are connected to each other, and the pixel electrode covers the color filter exposed through the contact hole.

Abstract: A high-intensity discharge (HID) lamp comprising a discharge vessel including a first and a second end region and defining an arc chamber containing an arc generating medium, a cathode and an anode in the first and the second end regions of the discharge vessel, respectively, the cathode and the anode each comprising a terminal end disposed within the arc chamber and separated by an arc gap, and an electrically conductive starting aid configured to initiate a dielectric barrier discharge (DBD) with the anode at or after a voltage across the first and second electrodes reaches an open circuit value. A ballast may control power provided to the HID lamp.

Abstract: A nonvolatile memory device includes resistive memory devices in a three-dimensional structure. A block select circuit generates a block select signal for selecting a memory block. In response to the block select signal, local word line selection units connected to each memory block connect global word lines connected to a word line decoder and local word lines, and local bit line selection units connected to each memory block connect global bit lines connected to a sense amplifier and local bit lines. Each memory block includes local word lines which extend in a first direction and are stacked in a second direction perpendicular to the first direction on a second plane perpendicular to a first plane. Local bit lines extend in the second direction to cross local word lines. Memory cells are formed at cross-points where local word lines and local bit lines cross one another.

Abstract: This invention develops a mathematical model to describe battery behavior during individual discharge cycles as well as over its cycle life. The basis for the form of the model has been linked to the internal processes of the battery and validated using experimental data. Effects of temperature and load current have also been incorporated into the model. Subsequently, the model has been used in a Particle Filtering framework to make predictions of remaining useful life for individual discharge cycles as well as for cycle life. The prediction performance was found to be satisfactory as measured by performance metrics customized for prognostics for a sample case. The work presented here provides initial steps towards a comprehensive health management solution for energy storage devices.

Abstract: A frequency detector includes an error measurement unit measuring a time interval between zero-crossing points of an input signal that is modulated. An error conversion unit quantizes the measured time interval using one of modulation time intervals. An error calculation unit calculates a frequency error based upon a difference between the measured time interval and the quantized time interval. An error generation control unit controls whether to output the frequency error based upon the quantized time interval, the calculated frequency error, and a predetermined critical value.

Abstract: A solid-state lighting device (500) includes a plurality of light-emitting elements (510, 525, 530) configured for generating light that are thermally coupled to a heat spreading chassis configured for coupling to one or more heat sinks (520). The lighting device further includes a mixing chamber which is optically coupled to the plurality of light-emitting elements and configured to mix the light emitted by the plurality of light-emitting elements. A control system is operatively coupled to the plurality of light-emitting elements, and configured to control operation of the plurality of light-emitting elements.

Abstract: A gamma control circuit includes a first gray-scale voltage selection unit that selects and outputs a highest gray-scale voltage and a lowest gray-scale voltage from among a plurality of first voltages present between a first supply voltage and a second supply voltage. A second gray-scale voltage selection unit receives the highest and lowest gray-scale voltages and selects and outputs a first intermediate voltage and a second intermediate voltage between the highest and lowest gray-scale voltages. A third gray-scale voltage selection unit receives the highest and lowest gray-scale voltages and the first and second intermediate voltages and generates a plurality of reference voltages from the received voltages. A gray-scale voltage generation unit receives the highest and lowest gray-scale voltages and the plurality of reference voltages and outputs a plurality of gray-scale voltages.

Abstract: A neural interface system including an electrode array and a carrier that supports the electrode array, in which the electrode array includes a substrate rolled into a three-dimensional shape, a plurality of conductive traces patterned on the substrate and adapted to transmit electrical signals, and a plurality of elliptically shaped, externally facing electrode sites coupled to the plurality of conductive traces that electrically communicate with their surroundings. The plurality of electrodes are arranged in a triangular lattice circumferentially around and axially along the carrier, and the substrate includes an edge that extends axially along the carrier and is constrained between a first axial row portion of the plurality of electrode sites and a second axial row portion of the plurality of electrode sites adjacent to the first axial row portion.

Abstract: In a method of manufacturing a thin film transistor substrate, a semiconductor pattern is formed on a substrate, a first etch stop layer and a second etch stop layer are sequentially formed on the semiconductor pattern, and the second etch stop layer and the first etch stop layer are sequentially patterned to form a second etch stop pattern and a first etch stop pattern. Thus, when the second etch stop layer is patterned using an etchant, the first etch stop layer covers the semiconductor pattern, thereby preventing the semiconductor pattern from being etched by the etchant.

Abstract: A flash memory system includes a memory unit including a main cell that stores main data and a parity cell that stores parity data, and an ECC receiving a codeword including the stored main data and the stored parity data, performing error correction on the codeword by executing an operation on a finite field with respect to the codeword, and an element of the finite field comprising a codeword corresponding to an erased page of the memory unit.

Abstract: A semiconductor integrated circuit including a detector and a secure checker. The detector generates a detection signal upon sensing an abnormal state in an operating environment of the semiconductor integrated circuit. The secure checker generates a check signal to find an operating condition of the detector and receives the detection signal. The detector activates the detection signal in response to the check signal.

Abstract: This invention relates to a lighting module (101) comprising a carrier (103), a plurality of LED groups (109), arranged in an array on the carrier (103), a mesh (105), arranged at the carrier (103), and a front diffuser plate (107) arranged in front of the mesh (105). The mesh (105) has walls, which are arranged in a geometrical pattern forming a plurality of cells (113), such that the light emitted from at least some of the LED groups, which are adjacent to each other, is mixed before passing the diffuser plate.

Abstract: A vascular clip for use in end-to-side anastomoses having a handle connected to a lower ring and an upper ring. The handle includes a resilient element biasing the two rings together so that the rings are closely juxtaposed when the clip is closed. The respective facing surfaces of each of the rings may be provided with a rough surface. A graft vessel or an artificial aneurysm may be sutured to the lower ring. The graft vessel or artificial aneurysm may be autologous or heterologous material or may be made of synthetic material. The handle may fit into a clip applier that facilitates the application of the clip. The handle and the clip applier may be of different shapes depending on the various applications of the clip.

Abstract: A method for delivering physiological pacing includes selecting an electrode implant site for sensing cardiac signals, which is in proximity to the heart's intrinsic conduction system, where pacing stimulation results in a rhythm breaking out at an intrinsic location, and selected in response to a ratio of sensed P-wave amplitude to sensed R-wave amplitude.

Abstract: A computing device for securely executing authorized code includes a protected memory for storing authorized code, which contains an original digital signature, and a processor in signal communication with the protected memory for preparing to execute code from the protected memory by verifying that a digital signature contained in the code is original in accordance with a public key, and if the original digital signature is verified, then branching to a copy of the authorized code in the protected memory to begin execution.

Abstract: A container assembly (1) having a container body (11) and exterior shelf structures (41, 44) that are each reversibly attached to exterior surfaces (35, 38) of first (17) and second (20) sidewalls of the container body (11), is described. Each exterior shelf structure (41, 44) has a shelf base (47), and a forward shelf portion (56) and a rear shelf portion (62) that each extend upwardly from the shelf base (47). Each exterior shelf structure has a shelf space (77) that resides between and is defined in part by the forward (56) and rear (62) shelf portions. The forward shelf portion (56) of each exterior shelf structure (41, 44) has an open front or face (86) that is in communication with a recessed chamber (89) of the forward shelf portion (56). The exterior shelf structures (41, 44) may each be reversibly attached to the container body sidewalls (17, 20) by means of tabs (98) that are received within tab apertures (110) of the sidewalls.

Abstract: A method of transforming relational queries of a database into on a data processing system includes receiving a series of relational queries, transforming first parts of the queries into a continuous query embodied as a streaming application, sending parameters in second parts of the queries in the series to the streaming application as a data stream, and executing the continuous query based on the received data stream to generate query results for the series of relational queries. Each query in the series includes a first part and a second part. The first parts are a pattern common to all the queries in the series and the second parts each have one or more parameters that are not common to all of the queries in the series.