Abstract: An interface component for a positioning system. The interface component includes a positioning arm having a first end and a second end, the first end being positionable against an object to be positioned and the second end being attachable to an actuator arm of the positioning system, and a damping element operably connected in parallel with the positioning arm.

Abstract: A circuit board assembly has a circuit board coupled to a support plane and defining a space between the circuit board and the support member. A circuit board component mounts to the circuit board and is oriented within the space defined by the circuit board and the support plane. A heat pipe assembly, located within the defined space, has a relatively high thermal conductivity, compared to other thermally conductive materials, and transfers heat from the circuit board component to the support plane or carrier tray associated with the circuit board. The heat pipe assembly has an input portion that contacts the circuit board component and an output portion that contacts the support plane. The heat pipe assembly also has a compliant portion having a lower stiffness relative to the stiffness of either the input portion or the output portion.

Abstract: Mechanisms and techniques allow a data storage system to detect errors in data received for storage within the data storage system. To do so, the data storage system receives, from an originator application operating on a server computer system, portions of data which comprise an application data block which is to be written to storage in the data storage system. In conjunction with the data received at the data storage system, the data storage system also receives application error checking information which the originator application generates on the data within the application data block. The application error checking information may be, for example, checksum information embedded within one or more portions of the data which comprise the application data block. Upon receipt of the data and the application error checking information, the data storage system generates data storage error checking information on the data within all portions of data which comprise the application data block.

Abstract: A circuit board has a first signal layer having a set of conductors, a second signal layer having a conductive plane and a non-conductive region, and a third signal layer having a conductive region that mirrors the non-conductive region of the second signal layer. The circuit board further includes a first separating layer having non-conductive material which is disposed between the first signal layer and the second signal layer, and a second separating layer having non-conductive material which is disposed between the second signal layer and the third signal layer. Accordingly, traces within the first signal layer and overlying the conductive plane of the second signal layer will have a first impedance, while traces within the first signal layer and overlying the non-conductive region of the second signal layer and the conductive region of the third signal layer will have a second impedance that is different than the first impedance.

Abstract: Mechanisms and techniques provide a system that provides stream data to a client by monitoring operation of a stream control protocol such as RTSP associated with stream data transmitted between a client and a first stream server. The system detects a stream change event related to transmission of the stream data between the client and the first stream server and identifies a relative position within the stream data based on the operation of the stream control protocol. The system then establishes transmission of the stream data between the client and a second stream server starting at the relative position in the stream data. The system provides for mid-stream failover for the transmission of stream data such as real-time data with minimal perceptible loss of stream data by the client.

Abstract: A surface mount adaptor allows for removable attachment of debugging connectors to a circuit board and provides high density access to the circuit board under test at a single location. A circuit board testing assembly has a support member having debugging connectors coupled to a first surface of the support member, the debugging connectors being configured to attach to a circuit board testing device. The circuit board testing assembly also has a support member connector coupled to a second surface of the support member and in electrical communication with the debugging connectors. The support member is configured to removably attach to a circuit board connector surface mounted to a first surface of a circuit board. Removable attachment of the debugging connectors from the circuit board provides an availability of space on the top side of the circuit board for additional circuit board components and traces.

Abstract: The invention is directed to techniques for notifying a client device of the occurrence of an event using a web application activated based on an application-state data record. A persistent process monitors incoming data for the occurrence of an event and provides the application-state data record that can be used to activate a session of an event notification application. The persistent process provides an event indicator to a proxy browser which then activates the event notification application. The event notification application provides an event notification to the proxy browser, which in turn provides an audio notification of the event to the client device, which may be a telephony device or other two-way audio communication device. The user of the client device can then respond to the event notification or otherwise interact with the event notification application via the proxy browser.

Abstract: This invention discloses a voice communication system including a telephone network including a multiplicity of telephones interconnected by telephone network interconnections, a computer network having a multiplicity of nodes and enabling e-mail communication between said nodes, a multiplicity of voice response computers, each voice response computer being connected to a node of the computer network and being actuable by an input received from one of the multiplicity of telephones via the telephone network for communicating voice received via said one of the multiplicity of telephones via e-mail over the computer network. A method of voice communication including a telephone network including a multiplicity of telephones interconnected by telephone network interconnections is also disclosed.

Abstract: An electronic system has critical circuitry, non-critical circuitry having a first section and a second section, and a power sub-system. The power sub-system has a first power assembly, a second power assembly, and a set of connections. The set of connections is configured to connect the first and second power assemblies to the critical circuitry and the non-critical circuitry such that, when the first and second power assemblies operate to power the critical and non-critical circuitry through the set of connections, (i) a failure of only the second power assembly results in the first power assembly continuing to power the critical circuitry and the first section of the non-critical circuitry, and (ii) a failure of only the first power assembly results in the second power assembly continuing to power the critical circuitry and the second section of the non-critical circuitry.

Abstract: A memory system and method of using same are provided. One embodiment of the system includes a semiconductor memory that is configured to include a multiplicity of memory segments. The memory segments are grouped into groups. Each of the groups includes N respective memory segments, where N is an integer number. In each respective group of memory segments, the N respective memory segments include respective data segments and a respective parity segment. Also in each respective group of memory segments, the respective parity segment in the respective group stores a respective data value P that may be calculated by a logical exclusive-or of respective data values stored in the respective data segments in the respective group.

Abstract: The disclosed electronic processing apparatus calculates and applies calibrations to sensors that produce quasi-sinusoidal, quadrature signals. The apparatus includes either or both of fixed and programmable electronic circuits. The apparatus includes a circuit to calculate the phase and magnitude corresponding to the two input (quadrature) signals. The apparatus also includes a circuit for accumulating the number of cycles of the input signals. The apparatus also includes a circuit to generate Gain, Offset, and Phase calibration coefficients, wherein the circuit compares the phase space position of the measured phasor with the position of an idealized phasor, the locus of the idealized phasor in phase space being a circle of predetermined radius with no offset. The calculation of the coefficients occurs without user intervention, according to a pre-programmed rule or rules.

Abstract: A grounding member support forms an interference or friction fit with an opening defined by a circuit board. A compliant, electrically conductive grounding member couples to the grounding member support. The grounding member electrically couples a grounding layer of the circuit board with a support mount coupled to the circuit board. During assembly, insertion of the grounding member support within the opening defined by the circuit board creates an expansive or lateral force on the opening. Furthermore, during assembly, the support mount compresses the compliant, electrically conductive grounding member against the circuit board. The interference fit between the grounding member support and the opening along with compression of the grounding member between the circuit board and the support mount limits the amount of stress received by a surface of the circuit board.

Abstract: Mechanisms and techniques disclose a system that provides access to data using a two part cache. The system receives a data access request containing a first data reference, such as an open systems request to access data. The system then obtains a history cache entry from a history cache based on the first data reference and obtains a partition cache entry from a partition cache based on the first data reference. Cache entries contain mappings between open systems reference locations and non-open systems references to locations in the data to be accessed. The system then performs a data access operation as specified by the data access request using a second data reference based upon either the history cache entry or the partition cache entry. Upon performance of the data access operation, the system then updates the history and partition caches with new cache entries and can resize the partition and history caches as needed.

Abstract: A storage processor particularly suited to RAID systems provides high throughput for applications such as streaming video data. An embodiment is configured as an ASIC with a high degree of parallelism in its interconnections. The preferred embodiment provides a store and forward architecture configured around a switch with prioritization on data pathways critical to high throughput.

Abstract: Mechanisms and techniques operate in a computerized device to enable or disable speculative execution of instructions such as reordering of load and store instructions a multiprocessing computerized device. The mechanisms and techniques provide a speculative execution controller that can detect a multiaccess memory condition between the first and second processors, such as concurrent access to shared data pages via page table entries. This can be done by monitoring page table entry accesses by other processors. The speculative execution controller sets a value of a speculation indicator in the memory system based on the multiaccess memory condition. If the value of the speculation indicator indicates that speculative execution of instructions is allowed in the computerized device, the speculative execution controller allows speculative execution of instructions in at least one of the first and second processors in the computerized device.

Abstract: A system capable of dynamically reserving bandwidth and adjusting bandwidth reservations for active sessions of data communication in a data communications device is provided. The system generally separates the operation of bandwidth allocation and adjustment from the operation of data transport through the device, thereby allowing bandwidth reservations and adjustments to be made without disturbing sessions of data communication that are actively being transported through the device. The system can accept requests to allocate or reserve bandwidth in a data communications device using bandwidth reservation protocols such as RSVP. The reservation requests create sender state data that can be used to compute resource allocation data. The resource allocation data can be used to label data storage locations in a data storage mechanism according to the required bandwidth reservations.

Abstract: One or more queues store data information such as packets or data flows for later transmission to downstream communication devices. A real-time clock tracks current time and an advancement of a moving time reference, which is displaced with respect to the current time of the clock by an offset value. Thus, as current time advances, the moving time reference also advances in time. Upon servicing a queue, a time stamp associated with the serviced queue is also advanced in time. To monitor a rate of outputting data from the one or more queues, a processor device at least occasionally adjusts the offset value so that the moving time reference and values of the time stamps advance in relation to each other. Consequently, by tracking a relative time difference between current time of the real-time clock and a relative advancement of time stamps, a rate of outputting data information from the queue is monitored over time.

Abstract: The present invention provides a reversible jacket that includes two independently functional flexible hoods that allow a person wearing the jacket to utilize one hood in one configuration of the jacket, and the other hood in a reversed configuration. A reversible jacket of the invention can find a variety of different applications, for example, it can be employed as a camouflage jacket in two different environments.

Abstract: A power converter provides power to a phased-array radar antenna system. The converter adjusts its internal zero-voltage switching current so that it efficiently provides a clean power signal over a wide range of potential loads. More specifically, the zero-voltage switching current is increased in response to a decrease in load. The zero-voltage switching current in the converter can be maintained based on use of the same control signals that are otherwise used to regulate (via switching) the voltage output of the converter.

Abstract: Techniques test a clock signal by comparing different portions of that clock signal to each other. Such techniques enable the detection of a clock signal having anomalies such as missing pulses or occasional delayed pulses. In one arrangement, a data communications device has a clock signal generator, processing circuitry and a test circuit, both of which are coupled to the clock signal generator. The clock signal generator provides a clock signal. The processing circuitry uses the clock signal to receive data elements on a set of input ports, and to transmit the data elements on a set of output ports. The test circuit includes a node that receives the clock signal, a comparison circuit that provides a comparison signal based on a comparison between the clock signal and a delayed copy of the clock signal, and an output circuit that provides a result signal based on the comparison signal.