Abstract: Various systems and methods for signal synchronization are disclosed. For example, some embodiments of the present invention provide methods for reduced area delay signal timing. Such methods include providing a delay lock loop circuit with a plurality of selectable delay elements. The methods further include operating the delay lock loop circuit in a first mode where a program number is established in relation to a reference frequency. The program number corresponds to a number of the plurality of selectable delay elements used to establish a first delay time at the reference frequency. The program number is multiplied by a multiplicand, and the product of the multiplication is used while operating the delay lock loop circuit in a second mode to select the number of delay elements utilized in delaying an input signal. In the second mode, an input signal is delayed by a second delay time that is approximately the first delay time multiplied by the multiplicand.

Abstract: Transistors of low voltage specification are used to process information in a signal received at a high(er) voltage level. A protection circuit ensures that the cross terminal voltages do not exceed an allowed maximum voltage (e.g., 2.4 V for transistors of 1.8V specification). In an embodiment, the protection circuit contains a PMOS transistor which turns off if a protected cross terminal voltage exceeds such allowed maximum voltage. As a result, protection may be provided while consuming minimal power. The protection circuit may be employed in various types of circuits such as input buffers and logic gates. The protection circuits and the input buffers may potentially be implemented using transistors of a single voltage specification.

Abstract: A method, apparatus and/or system of a level shifter circuit having a structure to reduce fall and rise path delay is disclosed. In one embodiment, a level shifter circuit comprise a first set of sequentially coupled pull-up and pull-down sub-circuits cross coupled to a second set of sequentially pull-up and pull-down sub-circuits to generate a positive feedback loop; an output node coupled to a shared node between the first pull-up and pull-down sub-circuits through an output inverter; a pull-up NMOS transistor with a gate contact coupled to the input of the second set, a source contact coupled to an input of the output inverter and a drain contact coupled to the output voltage of the level shifter circuit; and a pull-down NMOS transistor with a gate contact coupled to the input of the second set, a drain contact coupled to an output of the output inverter and a source contact coupled to a ground.

Abstract: The summing comparator includes: a first integrator; a second integrator for receiving an output of the first integrator; and a comparator for switching when the output of the first integrator is greater than the output of the second integrator. The outputs of the first and second integrators are directly compared by the comparator without the necessity of a summing amplifier.

Abstract: A hysteresis receiver containing two inverters and a logic controller. The inverters are implemented with threshold voltages equaling Vil and Vih, which together define the hysteresis window. The inverters receive the input signal and generate a respective inverted value. The logic controller propagates as output one of the two inverted values if the two inverted values are equal, and a prior value (corresponding to a previous sample) if the two inverted values are not equal. A receiver circuit with a hysteresis window defined by Vil and Vih, is obtained as a result.

Abstract: Systems and methods for identification of outlier semiconductor devices using data-driven statistical characterization are described herein.

Abstract: A digital storage element (e.g., a flip-flop or a latch) comprise a master transparent latch that receives functional data from a data input port and scan data from a scan input port and a slave transparent latch coupled to the master transparent latch. The slave transparent latch comprises dedicated functional data and scan data output ports. A clock gating element is also included that gates off a clock to the slave latch, and not the master transparent latch, based on an enable signal that is asserted to disable use of the digital storage element.

Abstract: Determining piece-wise polynomials which together would represent large data sets having multi-dimensional input vectors and corresponding output element. In an embodiment, a function/procedure/routine is recursively called/invoked to determine piece-wise polynomial is a data set cannot be entirely modeled by one polynomial. Another aspect of the present invention reduces the number of combinations (of orders for sub-polynomials forming the polynomials) to be tried in determining polynomials, meeting various accuracy requirements. Such a reduction is obtained based on a recognition that when the order in one dimension alone is increased and the result does not lead to acceptable accuracy of the polynomial, the combinations with a lesser number for the order (of the dimension) can be ruled out.

Abstract: A novel match/mismatch emulation scheme for an addressed location in a CAM system that includes a plurality of CAM blocks. The plurality of CAM blocks are organized into at least one rectangular array having rows each having a plurality of CAM blocks, a group of CAM cells and associated read/write bit lines connecting the group of CAM cells to an addressed search circuit. During debug mode, where the individual array cells do not participate in search, all the cells in the debug column behave the same way to emulate a match/mismatch on all words. The circuit provides a control input to include address evaluation of a debug cell in a row. The circuit also provides simultaneous switching noise analysis on an evaluating row. The resulting CAM cell provides a circuit to test individual rows for defects and noise analysis.

Abstract: The CCD charge detection amplifier includes a floating diffusion charge detection node biased from a voltage reference node; a reset device coupled between the floating Diffusion charge detection node and the voltage reference node; a first source follower stage having a control node coupled to the charge detection node; and a positive feedback device coupled in series with the source follower stage and having a control node biased from the voltage reference node.

Abstract: A technique that provides width expansion of two CAMs of varying widths by combining match results from two CAMs by integrating the two CAMs. In one embodiment, a synchronizer circuit triggers the operation of an External Priority Encoder module which can be used to cascade two CAMs to form a wider CAM. When the External Priority Encoder module is used with the CAM, the External Priority Encoder module will receive MATCH signals and control signals from individual CAMs residing on either side, and will be triggered by the last arriving signal between two ports associated with two CAMs. In case one of the ports is disabled the External Priority Encoder module relies totally on the control signal from the other port for operation. The synchronizer circuit has the ability to handle mismatches between the CAMs as well as differentiating valid and invalid combinations between the CAMs.

Abstract: A circuit for balancing delays through true and complement phases of complementary drivers includes: a first driver; a second driver; a first delay device coupled to an input of the first driver and having an input coupled to an input signal node; a second delay device coupled to an input of the second driver and having an input coupled to the input signal node through a first inverter, wherein the first and second delay devices are clocked such that an input signal reaches the first driver simultaneously with an inverted input signal reaching the second driver.

Abstract: An apparatus for adjusting bandwidth for a receiver includes: (a) a receiver clock operating according to receiver clock parameters related to received signals for sampling received signals; (b) a local clock; (c) a tracker receiving an indicator related to the receiver clock parameter and generating a tracking parameter for comparing the receiver clock parameter and periodicity of the local clock; (d) a counter for counting events associated with the tracking parameter and generating an event count relating to the received signals; (e) a decision unit for reckoning the event count and generate a decision parameter relating to the reckoning; and (f) output logic coupled with the decision unit, the tracker and the receiver clock for evaluating the decision parameter and the tracking parameter by a logical routine for determining a need for changing operation of the receiver clock and for generating a change signal when the need exists.

Abstract: An equalizer comprises a sampler, a filter, and a summer. The sampler samples a signal indicative of an input communication signal to determine digital decision output signals having a communication device data rate. The filter receives digital decision output signals from the sampler and generates equalization signals therefrom. The summer couples to the sampler and the filter and combines together the input communication signal with the equalization signals. Further, a plurality of clocks control timing associated with the sampler. These clocks have frequencies that are less than the predetermined data rate of the digital decision output signals.

Abstract: A CMOS image sensor system includes first and second groups of CMOS sensors each responsive to periodic first and second clock signal edges, the second clock signal edge being out-of-phase with the first clock signal edge. Output signals of the first group of CMOS sensors are coupled to a first group of sampling capacitors, respectively, by a first group of sampling switches. Then output signals of the second group of CMOS sensors are coupled to a second group of sampling capacitors, respectively, by means of a second group of sampling switches. Sampled signals on the second group of sampling capacitors to an input of an ADC, and then sampled signals on the first group of sampling capacitors are coupled to the input of the ADC by means of by multiplexing and sample/hold circuitry. A phase of at least one of the first and second clock signal edges is adjusted in response to calibration information so as to avoid circuit noise from being superimposed on sampled signals coupled to the input of the ADC.

Abstract: A current mirror circuit that allows for over voltage stress testing includes: a first transistor; a second transistor having a gate coupled to a gate of the first transistor; a switch coupled between the gate of the first transistor and the drain of the first transistor; a bias source coupled to a control node of the switch such that the switch is ON during normal current mirror operation, and the switch is OFF during over voltage stress testing; and a clamp coupled between the control node of the switch and a source node.

Abstract: An electronic system (2001) for manipulating an input data argument (D[31:0]) comprising an integer number of bits. The system comprises an input (R) for receiving a right direction argument and an input (L) for receiving a left direction argument. The system also comprises circuitry (200) for producing a first data output having the integer number of bits by rotating the input data argument in response to the first direction argument and the second direction argument. The system also comprises circuitry for providing a modified data output (502). The circuitry for providing comprises circuitry for selecting a first set of bits from the first data output as a first portion of the modified data output and circuitry for providing a second set of bits from a source other than the first data output as a second portion of the modified data output.

Abstract: A bootstrapped circuit for sampling inputs with a signal range greater than supply voltage includes: a bootstrapped switch coupled between an input node and an output node; a first transistor coupled to a control node of the bootstrapped switch; a first capacitor having a first end coupled to the first transistor; a second transistor coupled between the first transistor and a supply node, and having a control node coupled to a first clock signal node; a third transistor coupled between the first transistor and the supply node; a charge pump having an output coupled to a control node of the third transistor; a level shifter coupled to a second end of the first capacitor; a fourth transistor coupled between the supply node and a control node of the first transistor; and a fifth transistor coupled between the control node of the fourth transistor and the output of the charge pump and, having a control node coupled to the supply node; wherein the second end of the first capacitor can be charged to an input voltag

Abstract: According to an aspect of the present invention, multiple scan enable signals (controlling corresponding scan chains) are used in an integrated circuit, and the scan chains are placed in evaluation mode in non-overlapping durations between scan-in and scan-out operations. In an embodiment, a single clock signal drives the elements in both the scan chains, and the start and end of the non-overlapping durations are timed associated with the edges of the pulses of the clock signal. Multiple pulses of the clock signal may be used between the scan-in and scan-out. According to another aspect of the present invention, the scan elements are conveniently connected to different scan enable signals to take advantage of the non-overlapping durations.

Abstract: The synchronous logic device with reduced pin count scan chain includes: more than two flip/flops coupled to form a shift register for receiving a scan data input signal; a combinational logic circuit for receiving device inputs, generating flip/flop inputs for the more than two flip/flops, and generating an output signal; a first multiplexer for providing a clock signal to the more than two flip/flops during a test mode; a second multiplexer for selecting between a test mode output from the shift register and the output signal from the combinational logic circuit, and for providing a scan data output signal; and wherein the scan data input signal and the scan data output signal share an input/output pin.