Abstract: According to one embodiment of the present invention a memory subsystem comprises a column and a column select signal line. The column comprises at least one bit line and a write precharge circuit. The write precharge circuit is operable to provide at least a portion of a charge on the at least one bit line. The column select signal line is operable to provide a column select signal selecting the column for a write operation. The write precharge circuit is gated with the column select signal line such that the column select signal is communicated to the write precharge circuit upon selection of the column for the write operation. The write precharge circuit is operable to at least partially restore the charge on the at least one bit line upon receipt of the column select signal after the write operation.

Abstract: System and method are implemented to allow phase lock loop (PLL) status testing during a Serializer/Deserializer (SERDES) internal loopback built-in self-test (BIST). An existing pseudo random binary sequence (PRBS) data generator is modified to include a mode that produces a data pattern having a frequency content low enough to be verified on the tester used at the probe.

Abstract: Combining a graphics object with a picture where only the luminance value of a graphics object pixel is written to a corresponding picture pixel if the chrominance values of the graphics object pixel indicate transparency and yet the luminance value indicates non-transparency.

Abstract: A technique to pre-charge a CAM block array including a plurality of CAM blocks that is organized into at least one rectangular array having rows each having a plurality of CAM blocks, an associated GMAT line, an associated LMAT line, and a group of CAM cells. The pre-charge technique of the present invention accommodates for all CAM block configurations without compromising performance at the cost of silicon area. In one example embodiment, this is accomplished by precharging each LMAT line in the CAM block array. A predetermined amount of delay is then applied substantially after precharging each LMAT line. Each GMAT line in the CAM block array is then precharged.

Abstract: A tracking circuit in a memory unit which generates sense enable signals at optimal time instances. The tracking circuit includes a scalable driver block containing a number of dummy cells, each having a drive strength identical to the drive strength of a cell in a memory array. The dummy cells are turned on and drive a column as would the memory cells in the memory array. As a result, the scalable driver block approximates the delay caused by (a number of rows in) a column at least when the number of rows is large. An inverse control logic emulates the delay in case of a smaller number of rows, and one of the inverse control logic and the scalable driver blocks provides a pulse, which is used to trigger a sense operation.

Abstract: A solid-state image sensor has a readout architecture that incorporates charge multiplier cells into a horizontal register of a CCD image sensor, and includes a first CCD register adjacent to at least a second CCD register and coupled to the said first register through a charge overflow barrier. A high Dynamic Range readout system results in which the DR is not restricted by the voltage swing limitations on the charge detection node. As the charge is multiplied, the horizontal register structure increases in width and more charge multiplication gates are added per stage. A charge overflow region follows the charge multiplier. In this region the amount of charge that exceeds a certain predetermined threshold is split off into another register. A detection node that has different conversion sensitivity may terminate this register. The process of charge overflow and splitting off may continue for more than two steps.

Abstract: A method for test data-driven detection of outlier semiconductor devices. Some illustrative embodiments may be a method used to test a semiconductor die comprising performing a burn-in test of a plurality of sample semiconductor dies to identify a failure of a defective semiconductor die, correlating variations in a parameter with the failure (the parameter comprising a characteristic associated with the plurality of sample semiconductor dies), defining a parameter constraint associated with the parameter, performing a production test of a production semiconductor die, and identifying the production semiconductor die as an outlier semiconductor die (the outlier semiconductor die passing the production test, but failing to conform to the parameter constraint).

Abstract: The charge pump circuit includes: a charge pump output branch having a first transistor and a second transistor coupled in series; an output branch replica having a third transistor and a fourth transistor coupled in series; a feedback circuit coupled between the output branch and the output branch replica; a charge pump input circuit coupled to the charge pump output branch, and having first and second input branches; and an input circuit branch replica controlled by the feedback circuit and coupled to the charge pump input circuit.

Abstract: The pass-gate circuit with backgate pull-up includes: a pass-gate transistor coupled between a first port and a second port; a backgate pull-up transistor coupled between a back gate of the pass-gate transistor and a gate of the pass-gate transistor; a first MOS transistor coupled between a first port and the gate of the pass-gate transistor; and a second MOS transistor coupled between a second port and the gate of the pass-gate transistor.

Abstract: A current control device for driving LED devices uses a switched-mode current control loop inside of an output intensity low-frequency pulse width modulation (PWM) control loop. This allows separate control of current level (for accurate light wavelength output) and light intensity. The current control device requires only one switch to regulate current level, and no other switches for the intensity control. This allows lower parts count for greater reliability and lower system cost.

Abstract: The invention relates to a DC/DC converter including an input to which an input voltage Vin is applied, a inductance L whose one terminal is connected to the input, a first controllable switch N1 via which the other terminal of the inductance is connectable to a reference potential Vss, a second controllable switch P1 via which the other terminal of the inductance is connectable to the output of the converter, and a regulator circuit 1 configured so that it is able to control the two switches in regulating the output voltage of the DC/DC converter to a predetermined wanted value. The second controllable switch is a PMOS-FET.

Abstract: A bipolar rail-to-rail class-AB output stage that provides improved AC performance in low voltage applications. The bipolar output stage includes an input buffer stage, first and second complementary common emitter stages, and first and second control circuits biased and configured to assure class-AB operation of the first and second common emitter stages, respectively. The input of the bipolar output stage is applied to the input buffer stage, and the output of the bipolar output stage is provided by the second common emitter stage. The combination of the first common emitter stage and the first AB-control circuit operates as a current booster stage for the second common emitter stage, thereby obviating the need for a large power supply.

Abstract: A class AD audio amplifier system (10) with DC output detection logic (26) is disclosed. The amplifier system (10) includes multiple audio channels (20), each of which includes a pulse-width-modulator (PWM) (24). The DC detection logic (26) includes a sigma-delta modulator (60) and a digital low-pass filter (62) that monitors the PWM output signals from the PWM modulators (24). The sigma-delta modulator (60) operates at a first clock frequency, while the low-pass filter (62) operates at a much lower clock frequency, so that AC audio components, PWM harmonics, and sigma-delta quantization error is suppressed from the DC detection. The modulated filtered signal is compared against a threshold level (THRSH) to determine whether the amplitude of a DC component at the PWM output is sufficiently high to constitute a fault. If so, a fault detection signal (DC_DET) is issued, and the PWM modulators (24) are disabled to prevent unsafe conditions in the system (10).

Abstract: A circuit (48) and method, which can be used in a mass data storage device, controls adaptation asymmetry of coefficients of an FIR filter (20) using an accumulator (52) or accumulating correlation results between unequalized FIR filter input data samples and FIR filter output equalized error samples. A circuit (52) generates coefficient increment and decrement requests from the accumulated correlation results. A circuit (120,102?,122) updates the coefficients within a symmetric coefficient pair on the basis of the increment and decrement requests only if a predetermined nonzero coefficient magnitude difference between the coefficient pair would not be exceeded by the update.

Abstract: A wireless communications base station (10) having a digital bit modulation function (72) is disclosed. The bit modulation function (72) may be realized by a software routine executable by a programmable device such as a digital signal processor (40), or alternatively by dedicated logic circuitry. The bit modulation function (72) receives a datastream corresponding to the payload, and a scrambling code, each of which include an in-phase component and a quadrature component. The bit modulation function (72) corresponds to a split adder (94) that performs a Gray Code addition of corresponding bits of the in-phase and quadrature data components with corresponding bits of the in-phase and quadrature scrambling code components. The result is a combined in-phase bit and a combined quadrature bit for each bit position in the datastream. The Gray Code addition takes the place of a complex multiplication, thus saving significant processing capacity or reducing circuit complexity.

Abstract: An oscillator circuit comprises a plurality of ring oscillators wherein each ring oscillator produces an oscillatory output signal. The ring oscillators are cross-coupled such that each ring oscillator drives only one other ring oscillator. In at least one embodiment, the oscillator circuit comprises four, three-stage ring oscillators. As such, each ring oscillator comprising three cells (e.g., inverters or delay elements). Further, in this embodiment, the oscillator circuit produces a four phase clock comprising the oscillatory output signals from each of the four ring oscillators.

Abstract: An imaging architecture is provided employing CMOS imaging sensors. The imaging architecture utilizes time domain sampling techniques to extract image data from a photodiode (PD) pixel array. The CMOS imaging architecture associates time index values with firing of CMOS imaging sensors in response to a capture of an image. The time index values correspond to the brightness of the illumination received by the CMOS imaging sensor. The time index value associated with the firing of the CMOS imaging sensor can be stored and employed in reconstruction of the image. The imaging architecture includes systems and methods for reading and compressing imaging data extracted from the PD pixel array.

Abstract: An amplifier apparatus having a gain programmable in discrete increments includes: (a) an operational amplifier having a first and second input and an output; (b) a feedback circuit between the output and the second input; (c) a reference signal source and supply circuit coupled with the first input; (d) a first resistor network coupled between a first signal locus and the first input conveying a first input signal to the first input and including a first plurality of parallel-connected first resistors; selected first resistors being independently coupled in a first connecting with the first input; (e) a second resistor network coupled between a second signal locus and the second input conveying a second input signal to the second input and including a second plurality of parallel-connected second resistors; selected second resistors being independently coupled in a second connecting with the second input.

Abstract: Managing temperature of a read/write head (120) in a disk drive system in which there is a power variance due to different operation modes. A circuit device (100) determines and delivers additional power needed for compensating for the temperature variance due to different operational power requirements. The power is delivered to a resistive heater (Rheat) associated with the head (120). The compensating power is based on the delivery voltage, delivery current, and resistance of the resistive heater (Rheat). The delivery current is varied to account for changes in the resistance of the resistive heater (Rheat) since it can vary with temperature. By sensing the current with a sensor (13), the resistance is determined via the sensed current and the delivery voltage. The current is adjusted for maintaining the compensating power.

Abstract: A multi-cycle, multi-slope analog to digital converter overlaps charge and discharge periods to reduce latency to the end of the measurement following a sampling window. Additionally, charging and discharging of an integration capacitor during the measurement cycle occurs between defined thresholds so as to avoid saturation within the analog to digital converter.