Abstract: A clocked instruction flow is managed subject to issue and fetch constraints through a plurality of instruction latches which receive instructions from selected memory locations. By checking the number of instructions fetched and issued, the fetch program counter is adjusted responsive to the status of selected state variables indicating instructions issued and fetched. The instruction latches are fully scheduled from cycle to cycle with instructions, by fetching instructions in accordance with a fetch program counter.
September 5, 1995
Date of Patent:
January 13, 1998
Akira Katsuno, Niteen A Patkar, Sunil W. Savkar, Michael C. Shebanow
Abstract: A CPU architecture is provided having a user mode (User32), a plurality of exception modes (IRQ32 etc) and a system mode (System) entered via one of the exception modes. The system mode re-uses the same set of registers (16) as the user mode and yet has access to a set of privileged resources compared to the standard resources of the user mode. Interrupt of the same type are disabled when the system is already in that exception mode, but are re-enabled when the system is moved into the system mode. Branch instructions may be used in the user and system modes, but not the exception modes.
Abstract: An instruction flow control circuit controls the selection and execution of instruction signals in a microprocessor having multiple execution units that can execute plural instructions at one time. The instruction flow control circuit compares a number of signals indicating how many execution units are available with a number of signals indicating how many execution units are required. The circuit is a matrix of transmission gates which propagate signals through, or shift signals between, various signal paths for available resources, depending on the signals requesting the executing units. A number of output gates suppress the execution of instruction signals where an execution unit is requested but none are available.
Abstract: Apparatus and method for data processing includes a common data bus (4) to interconnect a bus master circuit (6) with one or more bus slave circuits (8, 10, 12). The data processing apparatus (2) is configured to support burst mode transfers in which an address word is followed by a sequence of data words relating to addresses following on from that specified by the address word. Such transfers increase the number of data words transmitted per address word that need be specified. The data bus (4) includes an address request signal line (16) by which any of the bus slave circuits (8, 10, 12) may request an address word to be transmitted in the next processing cycle rather than a data word. In this way, the bus master circuit (6) need not be specifically adapted for the bus slaves that are attached to the bus (4), since the bus slaves can themselves indicate to what extent they are able to deal with burst mode transfers.
Abstract: Within a data processing system having two alternative clock signals of different frequencies (fclk, mclk) it is necessary to provide a mechanism for switching between the clock signals. When switching from the fast clock (fclk) to the slow clock (mclk), the system adopts the slow clock from the first falling edge (ffe) after a processing delay (PD) associated with the decision as to whether or not to change clocks. This processing delay can be greater than one half of a cycle of the fast clock. In contrast, when switching from the slow clock to the fast clock, the system adopts the fast clock from the first rising edge (fre) following the processing delay. Thus, a system is provided in which differing strategies for synchronization are adopted depending upon the direction of change of the clock signal.
Abstract: The present invention relates to ion emitter tip metals and alloys for ionizing the molecules of a gas which concurrently produces small diameter and very low numbers of unwanted particles. Specifically, the invention discloses ion emitter tip materials which, when subjected to normal operating electrical conditions of between about 0.1 and 100 microamperes per emitter tip, produces about 1 particle or less having a diameter of about 0.5 microns or less per cubic foot. Useful ion emitter tip materials include zirconium, titanium, molybdenum, tantalum, rhenium or alloys of these metals. In a specific embodiment, the metal alloys comprise zirconium and rhenium, titanium and rhenium, molybdenum and rhenium, or tantalum and rhenium. Silicon coated metal emitter tips, particularly titanium-silicon coated are disclosed. The emitter tip materials are useful to obtain Class 1 clean room standards in static air or flowing air environments used, for example, in semiconductor manufacture.
Abstract: A multimedia method and apparatus is able to digitally mix audio signals to produce combined audio output signals. Prior to digital mixing, the audio input signals are de-formatted using a digital de-formatter, volume adjusted using digital volume controllers and converted to a common sampling rate utilizing a digital interpolator or decimator.
Abstract: A data processing system is described in which trace signals are provided upon a trace bus 12 to track the address of an instruction code currently being executed and the latest address to which a data access was made. The system incorporates a central processing unit core 14 and an instruction pipeline 16 via which instruction codes are fed to the central processing unit core 14. When a non-sequential instruction code fetch is made, a number of cycles must pass before that non-sequential instruction has made its way along the instruction pipeline 16 to the central processing unit core 14. This period is utilised to output the address of the non-sequential instruction code fetch upon the trace bus. The multiple cycles available for this allow a time division multiplexing technique to be employed for different portions of the address thereby enabling the trace bus to be narrower.
Abstract: Apparatus and method for contact printing uses a vacuum contact plate and a screen frame to hold a master film sheet in contact registration with a screen having a region that is substantially porous to the passage of air disposed about a central photosensitive region. The vacuum contact plate receives the screen frame and supports the master film sheet and the screen on an elevated, substantially planar component. Air is evacuated from a hollow cavity within the elevated component to create a pressure differential across the master film sheet to urge the master film sheet in contact with the screen. If the master film sheet is not large enough to cover the entire porous region of the screen, the master film sheet is attached to a carrier sheet of sufficient size. The carrier sheet is then placed on the elevated component to be retained in contact registration with the photosensitive screen.
Abstract: An integrated circuit includes a plurality of data handling devices and a data buffer for enabling transfer of data between the internal data handling devices and one or more external data handling devices external to the integrated circuit. A controller responds to an original clock signal for supplying a clock signal to control data transfer between the data handling devices. The controller includes a delay circuit operable to delay the original clock signal to generate a delayed clock signal, and includes a selector for inhibiting operation of the delay circuit and for selecting the original clock signal for controlling data transfer from an internal data handling device to another data handling device. The selector also enables operation of the delay circuit and selects the delayed clock signal for controlling data transfer from an external data handling device to an internal data handling device.
August 18, 1994
Date of Patent:
June 24, 1997
Advanced Risc Machines Limited
David Walter Flynn, Philip Brian Endecott
Abstract: An integrated circuit test mechanism based upon the JTAG standard utilises serial scan chains for applying signals to and capturing signals from predetermined nodes within an integrated circuit (2). Multiple independent scan chains (12, 14, 16) are provided for different circuit units (4, 6, 8, 10) within the integrated circuit, i.e. individual scan chains (12, 14) for circuit elements such as a central processing core (4) or a cache memory (8). The scan chain controller (18) is responsive to a scan chain selecting instruction (Scan-N) received at its serial input (20) to capture a scan chain specifying value at the serial input. The scan chain specifying value is then used to control the position of a scan chain multiplexer (28) that selects one of the multiple scan chains to which subsequent instructions received at the serial input are applied.
Abstract: A monolithic CMOS phase-lock loop (PLL) circuit provides a high frequency of operation suitable for RF applications. The PLL produces an output clock with high spectral purity and very low jitter. The output clock has a low static phase error relative to a reference input, making the PLL also useful for clock synchronizing applications, such as clock recovery elements in transmission/recycling channels. The PLL provides in-phase and quadrature signals from a VCO which has two differential transconductor stages having negative output conductance.
Abstract: Method for two-way digital communication between Data Terminal Equipment (DTE) and Data Communication Equipment (DCE), includes a novel command set. The inventive method involves initiating communication by transmitting one command from a set of DTE commands to the command interpreter block. That block interprets the command, and acts on the command, directing the command to the appropriate control block. The control block receiving the decoded command then executes the command by sending a signal representative of the command to a hardware interface device which transmits the signal to the receiving DCE.
Abstract: A computer game controller system and method has a pulse position modulated (PPM) input device for encoding status information in a pulse position control signal and a bimodal interface having a first and second interface circuits, each for coupling an input device to a computer game program. The first interface circuit is a pulse position signal decoder for decoding a pulse position control signal. The second interface circuit is a capacitor charge decoding circuit for decoding a variable resistance input compatible with the IBM game port standard. When the bimodal interface is coupled to a PPM input device, the received pulse position control signal is decoded with improved accuracy and speed using the first interface (the PPM decoder). However, when the bimodal interface is coupled to a conventional input device which generates a variable resistance input conforming to the IBM game port standard, the second interface (the capacitor charging network) is used to decode the control signal.
Abstract: A transistor circuit is formed on a substrate having source and drain electrodes and multiple current-controlling gates. The two current-controlling gates are separated by spacer oxide material. The first gate is an metal oxide semiconductor (MOS) gate that is insulated from the substrate by a layer of gate oxide. The second gate is a junction field effect transistor (JFET) gate contiguous to the MOS gate that is insulated from the MOS gate by a layer of spacer oxide.
Abstract: A data memory having an addressable array of memory cells which can be accessed as predetermined groups of memory cells, comprises output buffer means for storing the contents of at least the most recently read group of memory cells and another previously read group of memory cells; and reading means, responsive to an indication that the contents of the group of memory cells containing the required memory cell is not stored in the output buffer means, for reading the contents of the group of memory cells containing the required memory cell into the output buffer means; the contents of at least the required memory cell being supplied as an output from the output buffer means.
Abstract: A data processing system is provided in which the central processing unit clock signal (mclk, fclk) to a central processing unit core (14) may be suspended to reduce power consumption. This suspension is controlled by a suspend controller (20) that responds to a write request to a predetermined address (0x0320001C) to hold asserted a bus request signal (REQ) that cooperates with a bus controller (18) to block the central processing unit clock signal. The central processing unit core sees the suspend mode as a write request of an indefinite length. The suspend controller is responsive to an asynchronous input signal (FIQ, IRQ, EVENT1) to exit the suspend mode by issuing a bus acknowledge signal (ACK) and removing the block on the central processing unit clock signal.