Patents Represented by Attorney, Agent or Law Firm Amin, Eschweiler & Turocy, LLP
  • Patent number: 6901405
    Abstract: The invention provides a database schema for representing a workflow process definition (e.g., a schedule). The database schema may also include one or more bindings associated with the schedule, as well as persisted state information and data. The invention further includes a method for storing schedule information in a storage medium, as well as a computer-readable medium having a data structure stored thereon. The storage of schedule-related information provides for ease of version control, and ease of distribution, for example, where several engines point to the same database as a single source of transaction processing or workflow schedule definitions. The definitional database schema may be advantageously employed to reconstruct the schedule definition language solely from information in a database. In addition, the schema may be used for storing instances of running schedules and data associated therewith. This allows ease of schedule state and data monitoring using existing database query tools.
    Type: Grant
    Filed: December 20, 2000
    Date of Patent: May 31, 2005
    Assignee: Microsoft Corporation
    Inventors: Donald J. McCrady, Amit Mital, A. S. Sivakumar
  • Patent number: 6270579
    Abstract: A system and method is provided that facilitates the application of a uniform layer of developer material on a photoresist material layer. The system includes a multiple tip nozzle and a movement system that moves the nozzle to an operating position above a central region of a photoresist material layer located on a substrate, and applies a volume of developer as the nozzle scan moves across a predetermined path. The movement system moves the nozzle in two dimensions by providing an arm that has a first arm member that is pivotable about a first rotational axis and a second arm member that is pivotable about a second rotational axis or is movable along a translational axis. The system also provides a measurement system that measures the thickness uniformity of the developed photoresist material layer disposed on a test wafer. The thickness uniformity data is used to reconfigure the predetermined path of the nozzle as the developer is applied.
    Type: Grant
    Filed: October 29, 1999
    Date of Patent: August 7, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ramkumar Subramanian, Khoi A. Phan, Bharath Rangarajan, Bhanwar Singh, Michael K. Templeton, Sanjay K. Yedur
  • Patent number: 6221768
    Abstract: A method for fabricating a first memory cell and a second memory cell electrically isolated from each other. The method including forming a first polysilicon (poly I) layer on an oxide coated substrate and masking the poly I layer to pattern the first memory cell and the second memory cell and an unmasked portion therebetween. The unmasked portion of the poly I layer is transformed into an insulator such that the insulator electrically isolates the poly I layer (e.g., floating gate) of the first memory cell from the poly I layer (e.g., floating gate) of the second memory cell.
    Type: Grant
    Filed: February 25, 1999
    Date of Patent: April 24, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Kathleen R. Early
  • Patent number: 6204138
    Abstract: A method of forming a MOSFET device is provided. First lightly doped regions are formed, the first lightly doped regions including LDD extension regions of the device. Second very lightly doped regions are formed at least partially below the first lightly doped regions, respectively, the second very lightly doped regions having a dopant concentration less than the first lightly doped regions, and the second very lightly doped regions being implanted at a higher energy level than the first lightly doped regions.
    Type: Grant
    Filed: March 2, 1999
    Date of Patent: March 20, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Srinath Krishnan, Witold P. Maszara, Ming-Ren Lin
  • Patent number: 6196734
    Abstract: A system for regulating temperature of a developer is provided. The system includes a plurality of optical fibers, each optical fiber directing radiation to respective portions of the developer. Radiation reflected from the respective portions are collected by a measuring system which processes the collected radiation. The reflected radiation are indicative of the temperature of the respective portions of the developer. The measuring system provides developer temperature related data to a processor which determines the temperature of the respective portions of the developer. The system also includes a plurality of heating devices; each heating device corresponds to a respective portion of the developer and provides for the heating thereof. The processor selectively controls the heating devices so as to regulate temperature of the respective portions of the developer.
    Type: Grant
    Filed: October 5, 1999
    Date of Patent: March 6, 2001
    Assignee: Advanced Micro Devices
    Inventors: Michael K. Templeton, Bharath Rangarajan
  • Patent number: 6190062
    Abstract: One aspect of the present invention relates to a method of inspecting a patterned substrate using an SEM, involving the steps of evaluating the patterned substrate to determine if charges exist thereon; introducing the patterned substrate having charges thereon into a processing chamber of the SEM; inspecting the patterned resist using an electron beam generated by the SEM; and introducing a cleaner containing ozone into the processing chamber of the SEM.
    Type: Grant
    Filed: April 26, 2000
    Date of Patent: February 20, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ramkumar Subramanian, Khoi A. Phan, Bharath Rangarajan, Bhanwar Singh, Bryan K. Choo, Sanjay K. Yedur
  • Patent number: 6187483
    Abstract: A method (200) of determining an optimal mask fabrication process includes fabricating (202) a first mask pattern (220) on a mask using a first mask fabrication process and a second mask pattern (222) on a mask using a second mask fabrication process, wherein each mask pattern approximates an ideal pattern. The method (200) further includes performing a mathematical transform on the first and second mask patterns (230), wherein the mathematical transform provides a representation of the first and second mask patterns as sums of functions.
    Type: Grant
    Filed: May 28, 1999
    Date of Patent: February 13, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Luigi Capodieci, Christopher A. Spence
  • Patent number: 6187666
    Abstract: The present invention relates to a method for fabricating interconnecting lines and vias in a layer of insulating material. A via is formed in the layer of insulating material. A protective material is formed so as to be conformal to at least edges and sidewalls of the via, the protective material facilitating shielding of at least the edges and sidewalls of the via from a trench etch step. The trench etch step is performed to form a trench opening in the insulating material. The via and trench are filled with a conductive metal.
    Type: Grant
    Filed: June 8, 1999
    Date of Patent: February 13, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Bhanwar Singh, Michael K. Templeton, Bharath Rangarajan, Christopher F. Lyons, Sanjay K. Yedur, Ramkumar Subramanian
  • Patent number: 6182463
    Abstract: A portable evaporative cooling system includes a fan for generating a path of air, a water pump for dispersing water in the path of air generated by the fan, and a water cooler for storing the water. The water cooler has an opening to permit the water pump to draw water therefrom. Support structure supports the fan and water pump and is sized and dimensioned to cooperatively engage the water cooler. The pump pumps the liquid from the cooler in a substantially non-pulsating manner, thereby providing a substantially continuous misting.
    Type: Grant
    Filed: September 20, 1999
    Date of Patent: February 6, 2001
    Inventors: Christopher J. Strussion, Thomas Strussion
  • Patent number: 6184128
    Abstract: In one embodiment, the present invention relates to a dual damascene method involving the steps of providing a substrate having a first low k material layer; forming a first hard mask layer over the first low k material layer; patterning a first opening having a first width in the first hard mask layer using a first photoresist thereby exposing a portion of the first low k material layer; removing the first photoresist; depositing a second low k material layer over the patterned first hard mask layer and the exposed portion of the first low k material layer; forming a second hard mask layer over the second low k material layer; patterning a second opening having a width larger than the first width in the second hard mask layer using a second photoresist thereby exposing a portion of the second low k material layer; anisotropically etching the exposed portions of the first and second low k material layers; and removing the second photoresist, wherein and at least one of the first photoresist and the second pho
    Type: Grant
    Filed: January 31, 2000
    Date of Patent: February 6, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Fei Wang, Christopher F. Lyons, Khanh B. Nguyen, Scott A. Bell, Harry J. Levinson, Chih Yuh Yang
  • Patent number: 6180454
    Abstract: In one embodiment, the present invention relates to a method of forming a flash memory device involving the steps of forming a gate oxide layer on a substrate; forming a first poly layer over the gate oxide layer; forming an insulating layer over the first poly layer, the insulating layer comprising a first oxide layer over the first poly layer, a nitride layer over the first oxide layer, and a second oxide layer over the nitride layer; forming a second poly layer over the insulating layer; forming a tungsten silicide layer over the second poly layer; etching a portion of the tungsten silicide layer and the second poly layer, wherein in the etched portion at least about 20% of the second poly is not etched, thereby partially defining at least one stacked gate structure; etching at least a portion of the insulating layer and the unetched portion of the second poly layer thereby defining at least one select gate transistor structure; forming an interlayer dielectric layer over the select gate transistor structu
    Type: Grant
    Filed: October 29, 1999
    Date of Patent: January 30, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kent Kuohua Chang, John Jianshi Wang, Wei-Wen Ou
  • Patent number: 6179566
    Abstract: The invention includes a blower wheel assembly and method characterized by a steel hub with protruding lugs that mate with a corresponding array of holes in a backplate of the assembly. The lugs are riveted or otherwise deformed to upset the lug material, thereby permanently and securely attaching the hub to the backplate. The lugs may be formed on the hub by a machining process. The holes in the backplate may have stress relief portions to avoid stress concentrations in corners of the holes.
    Type: Grant
    Filed: May 21, 1999
    Date of Patent: January 30, 2001
    Assignee: Beckett Air Incorporated
    Inventors: Joseph H. Andulics, Gregory R. Nagy
  • Patent number: 6177802
    Abstract: A system for detecting defects in an interlayer dielectric (ILD) interposed between first and second conductive lines lying adjacent each other along a first plane is provided. A processor controls general operations of the system. A voltage source adapted to apply a bias voltage between the first and second conductive lines is employed to induce a leakage current across the ILD. A light source for illuminating at least a portion of the ILD is used to enhance the leakage current. A magnetic field source applies a magnetic field in a direction orthogonal to the leakage current. The magnetic field deflects carriers in a direction substantially perpendicular to the first plane. A voltage monitor measures a voltage generated across third and fourth conductive lines, the third and fourth conductive lines lying adjacent each other along a second plane which is substantially perpendicular to the first plane. The voltage monitor is operatively coupled to the processor.
    Type: Grant
    Filed: August 10, 1998
    Date of Patent: January 23, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sunil N. Shabde, Yowjuang William Liu, Ting Yiu Tsui
  • Patent number: 6178256
    Abstract: A method (200) of characterizing a lithographic printer includes the steps of printing a first and second pattern (202, 228) on substrates (214) using a reticle (220) having a first and second orientation. The method (200) further includes measuring a critical dimension of the first and second pattens at two points (230, 234) and determining an imaging system component of the critical dimension of the patterns at the two points (236). The method (200) may be further expanded to encompass substantially all the points within the image field.
    Type: Grant
    Filed: December 1, 1998
    Date of Patent: January 23, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Khanh B. Nguyen, Paul W. Ackmann, Stuart Brown
  • Patent number: 6173378
    Abstract: A method (320) of implementing a set of ordering rules for executing requests for access to a system memory (14) includes the steps of identifying a request status (322) for a new request for access to the system memory (14) and assigning a tag to the new access request (324) based on the status of the new request. A control circuit (106) inserts the new access request (340) into one of a read buffer (302) or a write buffer (304) at a specified location within one or the read or write buffers (302, 304) based on the status of the new access request. When the new access request is enqueued (342) and sent to an arbitration circuit (306), the requests are executed in an order with another access request (344) from the other of the read or write buffer based on the request status and the tag of the new request.
    Type: Grant
    Filed: September 11, 1998
    Date of Patent: January 9, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ranjit J. Rozario, Sridhar P. Subramanian, Ravikrishna Cherukuri
  • Patent number: 6172478
    Abstract: A power distribution system is provided for distributing power in a portable device being coupable to a charging system and including a main battery power and a bridge battery power. The charging system is coupled to a power bus through a diode. The main battery power system and the bridge battery system are also both coupled to the power bus through diodes. The predetermined voltage level is set with respect to the charging system, the main battery and the bridge battery, such that if all three are coupled to the bus, the recharging system both powers the unit and recharges the main battery. If the recharging system is removed, the main battery power system powers the portable device, and if the main battery power system is removed the bridge battery will provide power to the portable device.
    Type: Grant
    Filed: February 23, 2000
    Date of Patent: January 9, 2001
    Assignee: Telxon Corporation
    Inventors: Lee Edward Leppo, Martin M. Weiss, Prashant A. Solanki
  • Patent number: 6166411
    Abstract: In one embodiment, the present invention relates to a method of forming a silicon-on-insulator substrate involving providing a metal wafer; forming a low melting point oxide layer over the metal wafer; forming a first insulation layer over the low melting point oxide layer to provide a first structure; providing a second structure comprising a silicon layer and a second insulation layer; bonding the first structure and the second structure together so that the first insulation layer is adjacent the second insulation layer forming a buried insulation layer; and removing a portion of the silicon layer thereby providing the silicon-on-insulator substrate comprising a silicon device layer, the buried insulation layer, the low melting point oxide layer, and the metal wafer.
    Type: Grant
    Filed: October 25, 1999
    Date of Patent: December 26, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Matthew Buynoski
  • Patent number: 6165695
    Abstract: A method of forming a via structure is provided. In the method, a dielectric layer is formed on an anti-reflective coating (ARC) layer covering a first metal layer; and an amorphous silicon layer is formed on the dielectric layer. An ultra-thin photoresist layer is formed on the amorphous silicon layer, and the ultra-thin photoresist layer is patterned with short wavelength radiation to define a pattern for a via. The patterned ultra-thin photoresist layer is used as a mask during a first etch step to transfer the via pattern to the amorphous silicon layer. The first etch step includes an etch chemistry that is selective to the amorphous silicon layer over the ultra-thin photoresist layer and the dielectric layer. The amorphous silicon layer is employed as a hard mask during a second etch step to form a contact hole corresponding to the via pattern by etching portions of the dielectric layer.
    Type: Grant
    Filed: December 1, 1998
    Date of Patent: December 26, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Chih Yuh Yang, Christopher F. Lyons, Harry J. Levinson, Khanh B. Nguyen, Fei Wang, Scott A. Bell
  • Patent number: 6166439
    Abstract: A semiconductor device which includes a substrate and a conductive pattern formed on the substrate. The conductive pattern includes at least two conductive lines adjacent one another. A low dielectric constant (LDC) material is dispersed between the at least two conductive lines. The LDC material includes a polymeric material including a polymer having a first and second end. The first end includes a functional group adapted to substantially bond to an insulating layer covering at least a portion of the substrate. The second end includes a functional group adapted to substantially bond to a dielectric material deposited over the LDC material. The polymeric material also includes air pockets therein which facilitate mitigation of capacitive crosstalk between the at least two conductive lines.
    Type: Grant
    Filed: December 30, 1997
    Date of Patent: December 26, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventor: William P. Cox
  • Patent number: 6162587
    Abstract: A method of forming a via structure is provided. In the method, a dielectric layer is formed on an anti-reflective coating (ARC) layer covering a first metal layer; and a transition metal layer is formed on the dielectric layer. An ultra-thin photoresist layer is formed on the transition metal layer, and the ultra-thin photoresist layer is patterned with short wavelength radiation to define a pattern for a via. The patterned ultra-thin photoresist layer is used as a mask during a first etch step to transfer the via pattern to the transition metal layer. The first etch step includes an etch chemistry that is selective to the transition metal layer over the ultra-thin photoresist layer and the dielectric layer. The transition metal layer is employed as a hard mask during a second etch step to form a contact hole corresponding to the via pattern by etching portions of the dielectric layer.
    Type: Grant
    Filed: December 1, 1998
    Date of Patent: December 19, 2000
    Assignee: Advanced Micro Devices
    Inventors: Chih Yuh Yang, Christopher F. Lyons, Harry J. Levinson, Khanh B. Nguyen, Fei Wang, Scott A. Bell