Abstract: A method of fabricating a capacitor in a semiconductor device is provided. The method includes steps of depositing a metal layer for forming a lower electrode on a semiconductor substrate; forming, using an oxidation rate differential, an uneven structure in correspondence with a grain boundary of the metal layer; forming a dielectric layer on the lower electrode having the uneven structure; and forming an upper electrode on the dielectric layer.

Abstract: In a method for forming a semiconductor device, a device isolation layer is formed in a capacitor region of a silicon substrate, and a bottom electrode and a dielectric layer are formed on the device isolation layer. Insulation sidewalls are formed on both sides of the bottom electrode. A top electrode is formed on the dielectric layer, and simultaneously a gate electrode is formed in a transistor region of the silicon substrate. Source/drain impurity regions are formed in the silicon substrate at both sides of the gate electrode.

Abstract: Disclosed is a non-volatile (e.g., NOR type flash) memory cell array and a method for manufacturing the same. The memory cell array includes a plurality of isolation layers on a semiconductor substrate, parallel to a bit line and defining an active device area, a plurality of common source areas in the semiconductor substrate, separated from each other by the isolation layers such that the common source areas connect memory cells adjacent to each other in a bit line direction, a common source line on the semiconductor substrate, connected to each source area and extending in a word-line direction, an insulating spacer along a first sidewall of the common source line, a gate at a second sidewall of the insulating spacer including a tunnel oxide layer, a first electrode, an inter-electrode dielectric layer, and a second electrode, and a drain area in the semiconductor substrate on an opposite side of the gate from the common source area.

Abstract: The present invention provides a method of forming metal lines in a semiconductor device having advantages of preventing an “explosion” phenomenon during a dual damascene process so as to improve the yield of the device. An exemplary embodiment of the present invention includes removing etching residues by wet cleaning the semiconductor substrate after forming the via hole, dry cleaning the semiconductor substrate after the wet cleaning, and forming a second metal line that is electrically connected with the first metal line through the via hole.

Abstract: Disclosed are a CMOS image sensor and a manufacturing method thereof. The present CMOS image sensor comprises: first, second, and third photo diodes and a plurality of transistors spaced at a predetermined distance in a semiconductor substrate; a diffusion blocking layer on substantially an entire surface of the substrate, including an opening therein exposing at least one of the photo diodes; an interlevel dielectric layer over the entire surface of the substrate, covering the diffusion blocking layer; first, second and third color filter layers over the interlevel dielectric layer, respectively corresponding to the first, second and third photo diodes, and a plurality of microlenses over the color filter layers, corresponding to each color filter layer.

Abstract: Disclosed are a MOS transistor having a low resistance ohmic contact characteristic and a manufacturing method thereof capable of improving a drive current of the MOS transistor. A gate oxide layer, a gate electrode, and a spacer are formed on a silicon substrate, and a silicon carbide layer is deposited thereon. A photolithography process is performed, and the silicon carbide layer is etched except for predetermined portions corresponding to source-drain regions and the gate electrode. Then, a metal layer is formed on the resulting structure after performing a source-drain ion implantation process. The metal layer is heated to form a salicide layer on the gate electrode and the source-drain diffusion regions. Then, the unreacted metal layer is removed, thereby forming the MOS transistor.

Abstract: Disclosed are an MIM (Metal-Insulator-Metal) capacitor and a method of manufacturing the same. The MIM capacitor includes: a lower metal layer and a lower metal interconnection on a substrate; a barrier metal layer on the lower metal layer; an insulating layer on the barrier metal layer; an upper metal layer on the insulating layer; an interlayer dielectric layer having a via hole on the lower metal interconnection; and a plug in the via hole.

Abstract: Disclosed are: (i) a method for fabricating self-aligned contact hole in a semiconductor device, and (ii) a semiconductor device having a self-aligned contact. The method comprises the steps of: (a) forming an oxide layer covering a gate structure on a semiconductor substrate, the gate structure including a gate oxide pattern, a gate electrode pattern, a hard-mask nitride pattern, and a spacer nitride on sidewalls thereof; (b) forming a mask pattern on the oxide layer; (c) forming a contact trench by removing a portion of the oxide layer, exposed by the mask pattern, to a predetermined depth; (d) forming a buffer layer on the oxide layer, including in the contact trench; (e) etching a portion of the buffer layer at a bottom of the contact trench to expose a portion of the oxide layer; and (f) forming a contact hole by etching the exposed oxide layer using a remaining buffer layer as an etching mask.

Abstract: Compositions, inks and methods for forming a patterned silicon-containing film and patterned structures including such a film. The composition generally includes (a) passivated semiconductor nanoparticles and (b) first and second cyclic Group IVA compounds in which the cyclic species predominantly contains Si and/or Ge atoms. The ink generally includes the composition and a solvent in which the composition is soluble. The method generally includes the steps of (1) printing the composition or ink on a substrate to form a pattern, and (2) curing the patterned composition or ink. In an alternative embodiment, the method includes the steps of (i) curing either a semiconductor nanoparticle composition or at least one cyclic Group IVA compound to form a thin film, (ii) coating the thin film with the other, and (iii) curing the coated thin film to form a semiconducting thin film.

Abstract: Methods of fabricating semiconductor devices are disclosed. An illustrated example method protects spacers and active areas by performing impurity ion implantation on an oxide layer prior to etching the oxide layer. The illustrated method includes forming a gate on a semiconductor substrate, forming a spacer on a sidewall of the gate, forming an oxide layer over the substrate, forming a mask on the oxide layer to cover a non-salicide area, implanting impurity ions into a portion of the oxide layer which is not covered by the mask, removing the portion of the oxide layer which is implanted with impurity ions, performing salicidation on the substrate, and removing the mask.

Abstract: Disclosed is a method for forming a gate dielectric in a semiconductor device. The present method includes forming a first dielectric layer on a semiconductor substrate; removing a portion of the first dielectric layer to expose a portion of the substrate; forming a nitride layer on the exposed portion of the substrate and the first dielectric layer; forming a transition metal layer on the nitride layer; and oxidizing the transition metal layer to form a transition metal oxide layer.

Abstract: An improved bipolar junction transistor and a method for manufacturing the same are provided. The bipolar junction transistor includes: a buried layer and a high concentration N-type collector region in a P-type semiconductor substrate; a low concentration P-type base region in the semiconductor substrate above the buried layer; a first high concentration P-type base region along an edge of the low concentration P-type base region; a second high concentration P-type base region at a center of the low concentration P-type base region; a high concentration N-type emitter region between the first and second high concentration base regions; and insulating layer spacers between the high concentration base regions and the high concentration emitter regions. In the bipolar junction transistor, the emitter-base distance can be reduced using a trench and an insulating layer spacer. This may improve base voltage and high-speed response characteristics.

Abstract: A semiconductor device and a method for fabricating the same may improve the isolation characteristics without deterioration of the junction diode characteristics and an increase in a threshold voltage of a MOS transistor. The device includes a semiconductor substrate; an STI layer in a predetermined portion of the semiconductor substrate, dividing the semiconductor substrate into an active region and a field region; and a field channel stop ion implantation layer in the semiconductor substrate under the STI layer.

Abstract: A method and computer program for simulating a semiconductor integrated circuit is disclosed, in which a voltage coefficient of resistance according to a variation of width or length of a resistor device of the integrated circuit may be accurately applied to a model in a manner of including the length and width in variables for measuring the resistance of the resistor device and by which efficiency of a circuit design is considerably enhanced. The method generally includes the steps of measuring a plurality of resistances of a plurality resistors having different length (L) and width (W) from each other while varying a voltage applied to the resistors respectively, calculating a voltage coefficient resist (VCR) of the resistors using the measured resistances, the VCR expressed as a linear function of voltage, and calculating resistance of a certain resistor device having a specific length and width using the VCR.

Abstract: Disclosed are a mask of a semiconductor device and a method for forming a pattern thereof, which is capable of correcting a line width bias between a long line width and a short line width when a mask of a semiconductor transistor is formed. The mask may include a plurality of rectangular light shielding patterns formed on a mask disc on which gate line and contact holes are formed; and a connection pattern composed of a plurality of division patterns for selectively connecting the plurality of rectangular light shielding patterns one another. The plurality of rectangular light shielding patterns overlap with the contact hole mask and are formed on both sides of the connection pattern. The connection pattern is divided into 3 to 7 division patterns.

Abstract: Disclosed are a CMOS image sensor and a manufacturing method thereof.

Abstract: Disclosed are a gate structure in a trench region of a semiconductor device and method for manufacturing the same. The semiconductor device includes a pair of drift regions formed in a semiconductor substrate; a trench region formed between the pair of drift regions; an oxide layer spacer on sidewalls of the trench region; a gate formed in the trench region; and a source and a drain formed in the pair of the drift regions, respectively.

Abstract: A memory controller. A first counter is triggered by rising edges of a data strobe signal and generates a first count value. A second counter is triggered by falling edges of the data strobe signal and generates a second count value. A third counter is triggered by rising edges of an internal clock and generates a third count value. A first buffer uses the first count value as a write address for sequential storage of the data corresponding to the rising edges of the data strobe signal, and sequential outputs the data corresponding to the third count value after a first predetermined period. A second buffer uses the second count value as the write address for sequential storage of the data corresponding to the falling edges of the data strobe signal, and sequential outputs the data corresponding to the third count value after the first predetermined period.

Abstract: A first electrode layer having protrusions and depressions on its surface are formed on a lower insulating layer on a semiconductor substrate, and a sacrificial layer is formed on the first electrode layer with a material that is reflowable when heated. After reflowing the sacrificial layer by heat treatment, the reflowed sacrificial layer and first electrode layer are etched so that the protrusions of the first electrode layer are curved, and a dielectric layer and a second electrode layer are sequentially formed on the first electrode layer. When manufactured using the above method, a thin film capacitor may have higher capacitance without increasing the area of the electrode.

Abstract: A method for manufacturing structures of a CMOS image sensor. The method comprises the steps of depositing a gate insulating layer and a conductive layer on a semiconductor substrate; depositing an ion implantation barrier layer on the conductive layer; patterning the deposited gate insulating layer, conductive layer and ion implantation barrier layer to form a patterned, composite gate insulating layer, gate electrode and ion implantation barrier structure; forming a second photosensitive layer pattern to define a photodiode region; and implanting low-concentration dopant ions into the substrate using the second photosensitive layer pattern as an ion implantation mask to form a low-concentration dopant region within the photodiode region.