Abstract: Disclosed are a semiconductor device having a vertical trench gate structure to improve the integration degree and a method of manufacturing the same. The semiconductor device includes an epitaxial layer having a second conductive type on a first conductive type substrate having an active region and an isolation region, a trench in the isolation region, a first conductive type first region in the epitaxial layer at opposite side portions of the trench, an isolation layer at a predetermined depth in the trench, a gate insulation layer along upper side portions of the trench, a gate electrode in an upper portion of the trench, a body region in the active region, a source electrode on the body region, a source region in an upper portion of the body region at opposite side portions of the gate electrode, and a drain electrode at a rear surface of the substrate.

Abstract: A nonvolatile memory cell is disclosed, having first and second semiconductor islands at the same horizontal level and spaced a predetermined distance apart, the first semiconductor island providing a control gate and the second semiconductor island providing source and drain terminals; a gate dielectric layer on at least part of the first semiconductor island; a tunneling dielectric layer on at least part of the second semiconductor island; a floating gate on at least part of the gate dielectric layer and the tunneling dielectric layer; and a metal layer in electrical contact with the control gate and the source and drain terminals. In one advantageous embodiment, the nonvolatile memory cell may be manufactured using an “all-printed” process technology.

Abstract: A semiconductor device fabricating method may include forming an insulating layer on a semiconductor substrate; forming a through hole with a first depth in the insulating layer and the semiconductor substrate; forming a metal layer thereon, thereby forming a through electrode in the through hole; and exposing the through electrode by polishing the bottom surface of the semiconductor substrate.

Abstract: An example disclosed semiconductor device includes a semiconductor substrate, a lower interlayer insulating layer formed on the substrate, a lower wire formed on the lower interlayer insulating layer, and an upper interlayer insulating layer which is formed on the lower interlayer insulating layer and has a via hole to expose the lower wire. The lower wire includes a metal layer pattern and a conductive layer pattern, and the metal layer pattern has a protruding portion and the conductive layer pattern is formed on the upper part of the protruding portion of the metal layer pattern and has a hole to expose the protruding portion.

Abstract: Disclosed is a method for manufacturing a semiconductor device including a low-voltage MOS transistor and a high-voltage MOS transistor.

Abstract: A method for manufacturing a semiconductor device, including etching exposed areas of a substrate using patterned nitride and insulating layers as an etch mask to form a trench in the substrate; forming a buffer layer in the trench; forming a stress-inducing layer by implanting ions into a region of the substrate around the trench using the patterned nitride and insulating layers as an ion implant mask; forming a device isolation region by filling the trench with an trench insulating layer; and removing the patterned nitride and insulating layers.

Abstract: Disclosed is a varactor and/or variable capacitor. The varactor/variable capacitor includes a plurality of first conductive-type wells vertically formed on a substrate, a plurality of second conductive-type ion implantation areas formed in the first conductive-type wells, at least one second conductive-type plug electrically connected to the second conductive-type ion implantation areas, an isolation layer formed at sides of an uppermost second conductive-type ion implantation area, and a first conductive-type ion implantation area in an uppermost first conductive-type well electrically disconnected from the uppermost second conductive-type ion implantation area by the isolation area.

Abstract: An electronic device, including a substrate, a plurality of first semiconductor islands on the substrate, a plurality of second semiconductor islands on the substrate, a first dielectric film on the first subset of the semiconductor islands, second dielectric film on the second semiconductor islands, and a metal layer in electrical contact with the first and second semiconductor islands. The first semiconductor islands and the first dielectric film contain a first diffusible dopant, and the second semiconductor islands and the second dielectric layer film contain a second diffusible dopant different from the first diffusible dopant. The present electronic device can be manufactured using printing technologies, thereby enabling high-throughput, low-cost manufacturing of electrical circuits on a wide variety of substrates.

Abstract: A method for fabricating a semiconductor device employing a selectivity poly deposition is disclosed. The disclosed method comprises depositing selectivity poly on a gate poly and source/drain regions of the silicon substrate, and forming salicide regions on the gate and active regions from the deposited selectivity poly. Accordingly, the present invention employing selectivity poly deposition can reduce or minimize contact surface resistance and improve the electrical characteristics of the semiconductor device by reducing the surface resistance in a miniature semiconductor device. In addition, because the size of the gate electrode is getting small, the present invention can be used as an essential part of the future generations of nano-scale technology. Moreover, mass semiconductor production systems can promptly employ the present invention with existing equipment.

Abstract: Disclosed is an image sensor. The image sensor includes a lower structure having a photodiode and an interconnection, a passivation layer on the lower structure, a thermo-setting resin layer on the passivation layer, a color filter array on the thermo-setting resin layer, a micro-lens array on the color filter array, and a Low Temperature Oxide (LTO) layer on the micro-lens array.

Abstract: Thin film transistors (TFT) and methods for making same. The TFTs generally comprise: (a) a semiconductor layer comprising source and drain terminals and a channel region therebetween; (b) a gate electrode comprising a gate and a gate dielectric layer between the gate and the channel region; (c) a first dielectric layer adjacent to the gate electrode and in contact with the source and drain terminals, the first dielectric layer comprising a material which comprises a dopant therein; and (d) an electrically functional source/drain extensions in the channel region, adjacent to the source and drain terminals, comprising a material which comprises the same dopant as the first dielectric layer.

Abstract: Provided is a method for fabricating a semiconductor device. In the method, a poly layer on a semiconductor substrate is etched to a predetermined depth. Ions are implanted into the poly layer at a predetermined angle. The poly layer is etched again to expose a portion of the semiconductor substrate. Therefore, stress is applied to the poly gate instead of the barrier layer, so that the barrier layer is not opened during contact etching because effects of the barrier layer thickness can be solved. Also, stress is applied to a poly gate directly contacting a channel region of the semiconductor substrate to allow tensile force caused by the stress of the poly gate to directly induce tensile force to the channel region, and thus increase mobility, so that device characteristics can be remarkably enhanced.

Abstract: Disclosed is a method of manufacturing a semiconductor device, which includes the steps of: forming a high-voltage well region (e.g., by implanting impurity ions into a semiconductor substrate and then annealing); forming an isolation layer on the semiconductor substrate; implanting impurity ions into the high-voltage well region, thereby forming a low-voltage well region within the high-voltage well region; forming a gate electrode on the semiconductor substrate; and implanting impurity ions using the gate electrode as a mask, thereby forming source/drain regions within the low-voltage well region.

Abstract: Disclosed are a flash memory device having a silicon-oxide-nitride-oxide-silicon (SONOS) structure and a method of manufacturing the same. The flash memory device includes source and drain diffusion regions separated from each other on opposite sides of a trench in an active region of a semiconductor substrate, a control gate inside the trench and protruding upward from the substrate, a charge storage layer between the control gate and an inner wall of the trench, and a pair of insulating spacers formed on opposite sidewalls of the control gate with the charge storage layer therebetween. Here, the charge storage layer has an oxide-nitride-oxide (ONO) structure. Further, the depth of the trench from the surface of the substrate is greater than that of each of the source and drain diffusion regions.

Abstract: Provided are a SONGS type nonvolatile or flash memory device and related programming/erasing methods. The device has a deep well region of a first conductive type that isolates a well region of a second conductive type from a substrate to enhance programming and erasing operation characteristics. In the erasing method, first electrons are erased by one of Hot Hole Injection (e.g., gate-to-drain Hot Hole Injection) or tunneling in a first step, and second electrons that are not erased in the first step are erased by the other of tunneling (e.g., gate-to-body tunneling) or HHI in a second step. Preferably, a time gap intervenes between the first and second steps.

Abstract: A method for forming a dielectric layer having a low dielectric constant and a method for forming copper wiring using the same are provided. In the method for forming a dielectric, an etch stop layer and a first dielectric are sequentially formed on a semiconductor substrate. Next, the first dielectric is selectively etched to form a pattern, and a second dielectric is formed thereon. Here, the second dielectric may be formed using a plasma enhanced chemical deposition method to have pores or voids therein. Then, the dielectric is planarized and a damascene copper wiring is formed. Since the dielectric includes pores or voids, it may have a very low dielectric constant, which results in an improvement in RC delay.

Abstract: A CMOS image sensor and manufacturing method thereof are disclosed. The present CMOS image sensor comprises: a semiconductor substrate including an active region having a photo diode region and a transistor region; a gate on the active region, comprising a gate insulating layer and a gate electrode thereon; a first source/drain diffusion region in the transistor region at one side of the gate electrode, including a first conductivity type dopant; a second photo diode diffusion region in the region at the other side of the gate electrode, the second diffusion region including a first conductivity type dopant; insulating sidewalls on sides of the gate electrode; and a third diffusion region over or in the second diffusion region, extending below one of the insulating sidewalls (e.g., closest to the photo diode region), and including a second conductivity type dopant.

Abstract: Radio frequency identification (RFID) tags and processes for manufacturing the same. The RFID device generally includes (1) a metal antenna and/or inductor; (2) a dielectric layer thereon, to support and insulate integrated circuitry from the metal antenna and/or inductor; (3) a plurality of diodes and a plurality of transistors on the dielectric layer, the diodes having at least one layer in common with the transistors; and (4) a plurality of capacitors in electrical communication with the metal antenna and/or inductor and at least some of the diodes, the plurality of capacitors having at least one layer in common with the plurality of diodes and/or with contacts to the diodes and transistors. The method preferably integrates liquid silicon-containing ink deposition into a cost effective, integrated manufacturing process for the manufacture of RFID circuits. Furthermore, the present RFID tags generally provide higher performance (e.g.

Abstract: Provided is a method for manufacturing a semiconductor device. An insulation layer is formed on a bottom structure of a semiconductor substrate. Then, a trench and a via hole are formed by selectively etching the insulation layer, and a copper layer is deposited to fill the via hole and the trench. Next, a copper line is formed by a CMP (chemical mechanical polishing) process to planarize the copper layer, and a plasma process is performed to form a plasma-treated surface layer of the semiconductor substrate. The plasma-treated surface layer is then removed.

Abstract: The disclosure concerns a capacitor including a trench; an insulation layer; a first polysilicon layer; a first patterned dielectric layer; a second polysilicon layer patterned into a plurality of vertical bars in the trench; a second dielectric layer along surfaces of the first dielectric layer and the second patterned polysilicon layer; and a third polysilicon layer on the second dielectric layer.