Abstract: A phase/frequency detector, such as may be used in a phase-lock loop (PLL), having reduced jitter at high frequencies by reducing or eliminating the dead zone. The detector generates two output signals (UP and DOWN) wherein one of the output signals (depending upon which input signal arrives first) has a pulse width which is equal to a time delay between the input signals. There is a dead zone associated with very small phase differences between the input signals, and the dead zone is reduced by increasing the durations of two output pulses, using several delay elements which operate on signals that are derived from the reference and feedback inputs. The circuit may be tuned to reduce the dead zone to less than one picosecond, making it particularly useful for very high speed (greater than one gigahertz) clock circuits. The phase/frequency detector uses self-resetting, complementary metal-oxide semiconducting (SRCMOS) gates.

Abstract: A browser background extension method and system for a Web browser such that a link access can be backgrounded during slow link access time periods in a computer network having a client connectable to one or more servers, the client having an interface for displaying a first hypertext document with a hypertext link to a second hypertext document located at a server. Initially, an access parameter is associated with the hypertext link. Next, the hypertext link to the second hypertext document is selected, in response to user input. Thereafter, an access time period is invoked in an active mode of a Web browser such that the hypertext link accesses the second hypertext document in response to the selection. Next, if the access time period proceeds at a rate of access slower than a desired rate of access, the link access is terminated in the active mode of the Web browser and continues thereafter in a background mode on a scheduled or opportunistic basis, in response to a subsequent user input.

Abstract: A dialog for entry of uniform resource locators is provided with options, selected by actuation of a radio button, for entering blocks containing a resource identifier, a domain identifier, and a filename extension. The block text is visually distinguished from text entered by single characters from a physical or virtual keyboard. Once entered, the blocks are treated in a unitary manner for the purposes of deletion or substitution, with backspaces or deletes removing the entire block add selection of alternative options replacing the entire block. Character strings entered manually may be compared to the text blocks associated with the options provided and, when a match is identified, replaced with the block form to facilitate form checking of the composed uniform resource locator before returning it to the underlying application.

Abstract: A database synchronization system for synchronizing a plurality of local databases in a plurality of distributed computing systems is disclosed. The plurality of distributed computing systems form a distributed computing environment (DCE). The synchronization system includes a system server, a registry database, coupled to the system server, a local area network (LAN) synchronization server, coupled to the system server, a LAN server synchronization library, coupled to the system server, and a LAN server, coupled to the LAN synchronization server and selected ones of the plurality distributed computing systems forming a LAN. Synchronization between the LAN and the DCE registry occurs when registry modifications in the registry database affecting at least one of the plurality of local LAN databases invokes the LAN server synchronization library to synchronize the affected database. The synchronization system utilizes a registry database coupled to each of the local databases.

Abstract: A method and system for increased instruction dispatch efficiency in a superscalar processor system having an instruction queue for receiving a group of instructions in an application specified sequential order and an instruction dispatch unit for dispatching instructions from an associated instruction buffer to multiple execution units on an opportunistic basis. The dispatch status of instructions within the associated instruction buffer is periodically determined and, in response to a dispatch of the instructions at the beginning of the instruction buffer, the remaining instructions are shifted within the instruction buffer in the application specified sequential order and a partial group of instructions are loaded into the instruction buffer from the instruction queue utilizing a selectively controlled multiplex circuit. In this manner additional instructions may be dispatched to available execution units without requiring a previous group of instructions to be dispatched completely.

Abstract: A method of providing programmable associativity in a cache used by a processor of a computer system is disclosed. A congruence class of a memory block is defined using a first mapping function, providing a first associativity level of the cache. A logic unit connected to the cache monitors cache misses as the cache uses the first associativity level, and selects other associativity levels based on the cache misses, using other mapping functions. The logic unit has incorporated therein means for selecting the other associativity levels based on a rate of the cache misses in a particular congruence class. The congruence class may be defined by associating the memory block with a particular set of cache blocks in the cache, based on a first portion of an address of the memory block, and the other mapping functions may be implemented by dividing the particular set into subsets and selecting a subset for the memory block based on a second portion of the address.

Abstract: A monitor within an integrated circuit is disclosed for providing a signal which is proportional to an integrated circuits operating environment. A differential gain cell within the integrated circuit is biased with a bias circuit. A first environment sensitive circuit provides a signal to the first input of the differential gain cell and a second environment sensitive circuit provides a signal with a known relationship to the first environment sensitive signal to the second input of the differential gain cell. The signal produced by the second environment sensitive circuit has a known operational relationship with the signal produced by the first environment sensitive circuit such that changes in the integrated circuit operating environment produce a deviation between the two signals. The differential gain cell in response to the signal received on its first input and second input produces a signal which is responsive to the operating environment of the integrated circuit.

Abstract: A user friendly method for regulating the media environment of a television viewer by controlling content displayed on the television. The method controls content in response to a viewer's profile, accumulated viewing time and at least one content classification source. A viewer's profile is provided by a user which determines guidelines for an individual viewer. Content classification values for television are received and stored in response to a viewer's request for viewing a program. The content classification values correspond to television program availability and values attributed to viewing time. The content classification values are categorized into desirable content and undesirable content. The viewer profile data associates a viewer with a content classification value. Thereafter, the quantity of time a viewer spends viewing desirable content and the quantity of time a viewer spends viewing undesirable content is determined.

Abstract: A method and system in a data processing system of permitting concurrent processing of multiple conditional branch instructions are disclosed. A condition register is established within the processing system. First and second conditional branch instructions are dispatched during a single cycle of the processing system. Prior to speculatively executing the first conditional branch instruction, a first copy of the condition register is stored. Prior to speculatively executing the second conditional branch instruction, a second copy of the condition register is stored. Multiple copies of the condition register are concurrently maintained so that the first and second conditional branch instructions may be concurrently processed during a single cycle of the processing system.

Abstract: In response to dispatching a condition register modifying instruction to an execution unit, a condition register rename buffer is associated with such a condition register modifying instruction. The instruction is then executed in the execution unit. Following the execution of the condition register modifying instruction, condition register data is set in the condition register rename buffer to reflect the result of such instruction execution. Additionally, an indicator is set to indicate the condition register data is valid. At the time for completing the condition register modifying instruction, the condition register data is transferred from the condition register rename buffer to the architected condition register, thereby permitting condition register modifying instructions to be dispatched, executed, and finished before the condition register is available to complete each condition register modifying instruction.

Abstract: A method and system for reducing power consumption of a non-blocking cache memory within a data processing system is disclosed. In accordance with a method and system of the present disclosure, a detection unit, having several index-matching bits, is associated with the cache memory within the data processing system. A determination is made as to whether or not there is a match in the cache memory, in response to an occurrence of a cache request while the cache memory is performing a linefill operation. In response to a determination that there is not a match for the cache request in the cache memory, another determination is made as to whether or not there is a match for the cache request with a block of information within the ongoing linefill operation.

Abstract: A method of improving operation of a cache used by a processor of a computer system by introducing a level of randomness into a replacement algorithm used by the cache in order to lessen "strides" within the cache is disclosed. Different levels of randomness may be introduced into the replacement algorithm at different times to optimize the cache for different procedures running on the processor. The level of randomness can be selectively introduced by using a basic replacement algorithm to select a subset of a congruence class, and one or more random bits are then used to select a specific cache block within the subset for eviction. The basic replacement algorithm can be a least recently used algorithm. There may be three levels of randomness for a 4-way set associative cache, and there may be four levels of randomness for an 8-way set associative cache.

Abstract: Provided is a mechanical structure, for an information handling unit in which are included one or more exchangeable electric components, whose interior is enclosed by a box. The box has: an exchange opening formed for a replacement of an exchangeable electric component; and a lid for engaging the exchange opening and for contacting the exchangeable electric component. According to the present invention, the heat releasing effect can be enhanced with no deterioration of the ease with which a heat generating component can be exchanged. In addition, the present invention can be embodied as a relatively simple mechanical structure, and manufacturing costs can be reduced.

Abstract: A board-handling mechanism for more easily installing and removing boards from motherboards and/or other mountings within system enclosures does not require the removal of the enclosure. The mechanism provides leverage to positively seat and unseat circuit boards mounted into system connectors on the motherboard or other locations within system enclosures. A cable loop connector is provided within the enclosure opposite the opening for engaging the I/O connector on the forward edge of the daughterboard. The cable loop connector is biased to an upper position so that the daughterboard will first seat in the cable loop connector before being lowered and engaged to the motherboard connector.

Abstract: An interface cable which allows access to an operational Peripheral Component Interconnect (PCI) bus compatible circuit board is disclosed. A flat flexible cable (30,72) secures a plurality of connectors (50,32,36,38) at substantially equal intervals. The connectors on the flat cable are adapted to receive a connection (62,63,64,66,68) on a first edge of the PCI compatible circuit board (82,90). When the PCI compatible circuit board is plugged into the flat flexible cable, a second edge of the PCI compatible circuit board which is opposite the first edge is free to move laterally, away from neighboring circuit boards in response to a flexing of the flat flexible cable. Open space is created adjacent to the PCI compatible circuit board allowing sufficient access to surfaces of the functioning PCI compatible circuit board for testing purpose.

Abstract: A system and method are provided for distributing clock signals within integrated circuitry. The system includes a number of cells for the integrated circuitry such that the cells include substantially horizontal regions within which are disposed substantially horizontal lines representative of a first clock. The cells also include substantially vertical regions within which are disposed vertical lines representative of a second clock. The cells are disposed in substantially horizontal layers. The vertical regions, including the vertical lines representative of a second clock are substantially vertically aligned. The cells include circuitry disposed within each cell such that a first portion of such circuitry includes signal wiring, and a second portion of such circuitry includes clock wiring, and such that the disposition of said circuitry minimizes a cumulative length of signal wiring and clock wiring.

Abstract: A high-speed carry-lookahead binary adder is disclosed. The binary adder includes multiple rows of carry-lookahead circuits, a half-sum module, and a sum/carry module. A first carry-lookahead circuit row includes multiple four-bit group generate circuits and multiple four-bit group propagate circuits. Each of the four-bit group generate circuits produces a generate signal for a corresponding bit location. Each of the four-bit group propagate circuits produces a propagate signal for a corresponding bit location. The half-sum module is utilized to generate a half-sum signal. By utilizing the half-sum signal, the generate signals, and the propagate signals, the sum/carry module generates sum signals and a carry signal.

Abstract: A computer, and particularly a mobile client computer system, in which flexibility in use of the system is enhanced by a capability of receiving and dynamically recognizing a variety of what are here called docking options. Docking options are peripheral devices, such as radio transceivers, which can be selectively connected to and used with a mobile client system. A docked option is identified by an exchange of signals between the system and the option, accomplished through a plurality of input/output ports which together define an interface to the option.

Abstract: A method of improving memory latency associated with a read-type operation in a multiprocessor computer system is disclosed. After a value (data or instruction) is loaded from system memory into a cache, the cache is marked as containing an exclusively held, unmodified copy of the value and, when a requesting processing unit issues a message indicating that it desires to read the value, and the cache transmits a response indicating that the cache can source the value. The response is transmitted in response to the cache snooping the message from an interconnect which is connected to the requesting processing unit. The response is detected by system logic and forwarded from the system logic to the requesting processing unit. The cache then sources the value to an interconnect which is connected to the requesting processing unit. The system memory detects the message and would normally source the value, but the response informs the memory device that the value is to be sourced by the cache instead.

Abstract: A high-level (L2) cache and a efficient method for writing directory entries into an array of directory entries are disclosed. The high-level (L2) cache operates differently depending upon whether a MESI (Modified, Exclusive, Shared, Invalid) state of a cache line in Invalid or Modified when the cache line's low-level (L1) Inclusive bit is set. Initially, the high-level (L2) cache retrieves a directory entry from the array of directory entries. This directory entry is placed into an n-position priority queue. Associated with the n-position priority queue is a set of priority indicators. These priority indicators are updated when a directory entry is placed into the n-position priority queue to indicate which order the various directory entries were placed into the n-position priority queue. If the directory entry is waiting for results to be received from the system bus, the directory entry will remain in the queue until such results are received.