Abstract: An apparatus includes a sawtooth generator configured to generate a sawtooth voltage, where the sawtooth generator is configured to repeatedly reset the sawtooth voltage using a clock signal. The apparatus also includes a pulse width modulation (PWM) generator configured to generate a PWM signal using the sawtooth voltage, the PWM signal comprising multiple PWM pulses, where an output voltage is based on the PWM signal. The apparatus further includes a transient detector configured to detect a transient associated with the output voltage and to cause the sawtooth generator to asynchronously reset the sawtooth voltage in response to the detected transient. The resetting of the sawtooth voltage may cause the sawtooth generator to lengthen one or more of the PWM pulses in the PWM signal and/or generate one or more additional PWM pulses in the PWM signal. This can help to increase a duty cycle of the PWM signal.

Abstract: A method may include receiving an input from an optimization control that indicates a value along a scale, wherein the value is indicative of a design tradeoff between at least optimization for a first parameter of an electrical design and an optimization for a second parameter of the electrical design, wherein the value places an emphasis on the first parameter and an emphasis on the second parameter such that when the value on the scale is closer to the first parameter a larger emphasis is placed on the first parameter of the electrical design and when the value on the scale is closer to the second parameter a larger emphasis is placed on the second parameter of the electrical design. The method may further include choosing components for the electrical design based on the value indicated using the optimization control, the emphases affecting the components selected for the electrical design.

Abstract: A rail-to-rail buffer receiving a differential input signal and generating a differential output signal includes first and second amplifier circuits configured in a pseudo differential buffer structure and first and second comparators coupled to compare the respective part of the differential input signal and a first voltage and to generate select signals. Each of the first and second amplifier circuits includes first and second complementary differential input stages and the first and second comparators generate respective select signals to turn on only one of the first or the second differential input stage in each amplifier circuit depending on a value of the respective part of the differential input signal. In operation, the first and second complementary differential input stages of each amplifier circuit not being turned on at the same time.

Abstract: An apparatus includes multiple switching regulators configured to generate at least one regulated output signal. The apparatus also includes a combination unit configured to blank the switching regulators in response to a switching event associated with one or more of the switching regulators. Each switching regulator could include a one shot timer configured to generate a first signal having pulses that identify switching events associated with that switching regulator. The combination unit may be configured to combine the first signals to generate at least one second signal, which can be provided to blanking inputs of the switching regulators. The combination unit could include one or more logical OR gates configured to combine the pulses in the first signals. The one shot timer in each switching regulator could generate a pulse in the first signal in response to each rising and falling edge of a control signal in that switching regulator.

Abstract: A method for providing feed forward compensation in a drive signal for a rapid resonant frequency change due to a rapid LASER intensity change upon a micro-electro-mechanical system (MEMS) mirror and/or a surrounding MEMS structure in a MEMS scanner causing a mirror temperature change is provided. The method includes determining an intensity factor for at least one laser beam projected onto the MEMS scanner and adjusting a drive frequency of the drive signal based on the intensity factor. The intensity could represent a single intensity factor for multiple laser beams projected onto the MEMS scanner. The method could also include delaying the adjustment of the drive frequency to allow the resonant frequency change to take affect in the MEMS scanner. Delaying the adjustment could include delaying delivery of the intensity factor such that the intensity factor is provided coincident with the resonant frequency change of the MEMS scanner.

Abstract: A method for calibrating a fixed gain amplifier configured as a front-end amplification stage of an analog-to-digital converter including sampling a calibration voltage with normal and inversed polarity and with the fixed gain amplifier bypassed and with the fixed gain amplifier connected. An actual gain value of the fixed gain amplifier is computed from offset corrected digital output codes generated from converting the calibration voltage. A gain correction value for the fixed gain amplifier can then be computed based on the ratio of the actual gain to the ideal gain. In another embodiment, a method for calibrating an analog-to-digital converter including a fixed gain amplifier, an input buffer and a modulator generates an offset correction value using normal and polarity inversed input samples. The offset correct value provides correction for at least offset errors in the fixed gain amplifier, the input buffer and the modulator.

Abstract: Bandgap voltage reference circuitry capable of operating at very low power supply voltages. The current source for driving the core bandgap voltage reference is implemented with insulated gate field effect transistors having low threshold voltages. Voltage clamp circuitry protects the transistors from power supply voltage variations rising above a predetermined clamp voltage. An output amplifier with output biasing circuitry having a circuit structure similar to that of the core bandgap voltage reference ensures that the bandgap reaches the intended steady state of operation.

Abstract: A fixed point finite impulse response (FIR) filter comprising: 1) an input stage for receiving an input signal as a sequence of input samples comprising: i) delay elements connected in series for receiving and shifting N sequential input samples; ii) multipliers, each multiplier receiving a selected one of the N sequential input samples from the delay elements and multiplying the selected input sample by a corresponding coefficient to produce an intermediate product; and iii) a summer for receiving and adding N intermediate products from the multipliers to produce an output sum signal comprising a sequence of output sum samples; and 2) an output stage for truncating k least significant bits (LSBs) from each of the output sum samples, wherein k is a variable number.

Abstract: A fixed point finite impulse response (FIR) filter comprising: 1) an input stage for receiving an input signal as a sequence of input samples comprising: i) delay elements connected in series for receiving and shifting N sequential input samples; ii) multipliers, each multiplier receiving a selected one of the N sequential input samples from the delay elements and multiplying the selected input sample by a corresponding coefficient to produce an intermediate product; and iii) a summer for receiving and adding N intermediate products from the multipliers to produce an output sum signal comprising a sequence of output sum samples; and 2) an output stage for truncating k least significant bits (LSBs) from each of the output sum samples, wherein k is a variable number.

Abstract: A fixed point finite impulse response (FIR) filter comprising: 1) an input stage for receiving an input signal as a sequence of input samples comprising: i) delay elements connected in series for receiving and shifting N sequential input samples; ii) multipliers, each multiplier receiving a selected one of the N sequential input samples from the delay elements and multiplying the selected input sample by a corresponding coefficient to produce an intermediate product; and iii) a summer for receiving and adding N intermediate products from the multipliers to produce an output sum signal comprising a sequence of output sum samples; and 2) an output stage for truncating k least significant bits (LSBs) from each of the output sum samples, wherein k is a variable number.

Abstract: A power supply controller controls the power supply voltage provided to a multi-gain step RF power amplifier to increase the efficiency of the RF power amplifier when the different gains of the RF power amplifier are selected and, thereby, reduce the power consumed by the multi-gain step RF power amplifier.

Abstract: A method of generating a spread spectrum clock signal for a line imaging device including receiving a line length value of the line imaging device, receiving a first clock signal indicative of a system timing signal in the line imaging device, generating a spreading waveform having a frequency as a function of the line length value and having a total number of clock cycles matching the line length value, and modulating the first clock signal using said spreading waveform to generate the spread spectrum clock signal where the spread spectrum clock signal is used for driving the imaging, data sampling and digitizing, and data transfer operation of the line imaging device. The spread spectrum clock has the same clock frequency variation for each scan line of the line imaging device.

Abstract: An amplifier includes an input stage, a comparator coupled to an output of the differential input stage, and a trimming controller coupled to an output of the comparator. The input stage includes a plurality of trim devices coupled in parallel with a first input device. The trimming controller is adapted to configure the trim devices based on an output of the comparator. The trim devices may selectively control a total effective device area of the first input device. Each of the trim devices, when enabled, may add a specified area to the total effective device area of the first input device. The input stage may also include a second plurality of trim devices coupled in parallel with a second input device.

Abstract: A method for generating a drive signal for a micro-electro-mechanical system (MEMS) scanner is provided. The method includes generating the drive signal for the MEMS scanner using a direct digital synthesis, numerically-controlled oscillator. For a particular embodiment, the drive signal is generated by receiving a summation of (i) an initial control word and (ii) an accumulated correction signal generated based on a comparison of a horizontal drive signal for the MEMS scanner and a horizontal sensor signal received from the MEMS scanner. The summation is added to a phase accumulator output, an address is extracted from the phase accumulator output, and a digital lookup table output is addressed based on the extracted address. The digital lookup table output is converted into an analog signal with a digital-to-analog converter, the analog signal is filtered to generate the drive signal, and the horizontal drive signal is generated based on the drive signal.

Abstract: A technique for invoking a low power operational mode in response to a halt instruction is used in a computer system that includes a processor coupled to external logic. The processor includes at least (i) a pipeline subcircuit to execute programmed instructions, including halt instructions, (ii) an interrupt handling subcircuit to handle interrupts generated by external interrupt logic, and (iii) clock generator circuitry that supplies clock signals to the pipeline and interrupt handling subcircuits. In response to execution of a halt instruction, the processor (i) stops the clock generator circuitry from supplying clock signals to the pipeline subcircuit, but not to the interrupt handling subcircuit, and (ii) generates an acknowledgement signal to the external logic indicating that the clock signals to the pipeline subcircuit are being stopped, thereby entering the low power operational mode.

Abstract: A microprocessor includes an execution unit for processing a stream of instructions wherein one or more of the instructions reference the eight logical x86 general purpose registers as source and destination registers for operands for the instructions. The microprocessor further includes a register file with a plurality of physical registers in excess of the eight x86 general purpose registers. The physical registers in the register file are mapped to the logical x86 general purpose registers such that one of the physical registers may contain one or more logical source or destination registers of the x86 general purpose registers for an instruction. The register file drives the entire bits of the physical register which contains the destination register for the instruction onto an internal bus. The bits are stored in a latching circuit in the register file. The execution unit performs the instruction and returns the resulting operand to be stored in the logical destination register.

Abstract: An integrated circuit is reprogrammable in metal using (a) a set of spare devices, and (b) separate arrays of spare rows and columns. The spare rows are formed in the top metal layer, and the spare columns are formed in the next to the top metal layer (for example, metal layers 4 and 5 of a 5 level metal process). Use of arrays of spare rows/columns facilitates silicon debug of the integrated circuit using FIB (focused ion beam) reprogramming without requiring FIB connections of more than 500 .mu.m.

Abstract: A write-back coherency system is used, in an exemplary embodiment, to implement write-back caching in an x86 processor installed in a multi-master computer system that does not support a write-back protocol for maintaining coherency between an internal cache and main memory during DMA operations. The write-back coherency system interrupts the normal bus arbitration operation to allow export of dirty data. In response to an arbitration-request (such as HOLD), if the internal cache contains dirty data, the processor is inhibited from providing arbitration-acknowledge (such as HLDA) until the dirty data is exported (the cache is dynamically switched to write-through mode to prevent data in the cache from being made dirty while the bus is arbitrated away). While the requesting bus master is accessing memory, bus snooping is performed and invalidation logic invalidates at least those cache locations corresponding to locations in memory that are affected by the requesting bus master.

Abstract: An NDIRTY cache line lookahead technique is used to expedite cache flush and export operations by providing a mechanism to avoid scanning at least some cache lines that do not contain dirty data (and therefore will not have to be exported). The exemplary cache organization uses one-line lookahead where each cache line but the last has associated with it an NDIRTY bit that indicates whether the next cache line contains dirty data. For cache flush and export operations, when a cache line (N) is read to check for dirty data that must be exported, the NDIRTY bit for that cache line is also tested to determine whether the next cache line (N+1) contains dirty data--if the NDIRTY bit is clear, indicating that the next cache line is clean, then that line is skipped and the scan proceeds with the line after that (N+2). This exemplary one-line lookahead implementation is readily extendible to N-line lookahead.

Abstract: A system and method for virtualizing external pins and their internal functions within a microprocessor employing an operating system independent interrupt and N subhandlers to virtual the equivalent functions of the pins ordinarily performed by extrinsic circuitry internal to the microprocessor.