Abstract: An arithmetic circuit 10 for performing prescaled division uses a rectangular multiplier 16 and accumulator 30 operable to calculate a short reciprocal and scaled dividend and divisor to enable the sequential iterative calculation of large radix quotient digits. Each quotient digit can be calculated using a single pass through the rectangular multiplier 16 and accumulator 30 and can be accumulated to form a full precision quotient in a quotient register 36.

Abstract: A superscalar superpipelined microprocessor having a write buffer located between the core and cache is disclosed. The write buffer is controlled to store the results of write operations to memory until such time as the cache becomes available, such as when no high-priority reads are to performed. The write buffer includes multiple entries that are split into two circular buffer sections for facilitating the interaction with the two pipelines of the core; cross-dependency tables are provided for each write buffer entry to ensure that the data is written from the write buffer to memory in program order, considering the possibility of prior data present in the opposite section. Non-cacheable reads from memory are also ordered in program order with the writing of data from the write buffer. Features for handling speculative execution, detecting and handling data dependencies and exceptions, and performing special write functions (misaligned writes and gathered writes) are also disclosed.

Abstract: An integrated circuit extraction tool includes an elongated base having a first end and second end. A first set of teeth are provided on the first end and a second set of teeth are provided on the second end. The first set of teeth are spaced at a first spacing distance and the second set of teeth are spaced at a second spacing distance. In the preferred embodiment, the first set of teeth are spaced to correspond with the spacing between pins of a integrated circuit to be extracted and the second set of teeth are spaced at a distance to correspond to the spacing between base portions of a socket's connectors. One or both of the ends may be angled at ninety degrees to allow integrated circuit removal with minimal clearance.

Abstract: A fully differential voltage controlled oscillator having a large common mode rejection ratio is disclosed with a first and a second phase detector disposed between the output of a differential comparator and the input of a differential triangle wave generator to insure 180 degree out of phase operation.

Abstract: A scan test architecture includes first and second serial scan paths for transferring test data to and from an integrated circuit's logic. A first clock controls transfer of information on the first scan path and a second clock controls transfer of data on the second scan path. The first and second clocks are alternately enabled by a control signal initiated under program control of the external test system.

Abstract: A coprocessor 18 comprises a bus controller 24 which further comprises a primary bus controller 28 and a secondary bus controller 30 that drive a floating point processor core 26. The primary bus controller 28 comprises a memory mapped bus interface 32 for processing memory mapped format instructions and an I/O bus interface 34 for processing conventional I/O format instructions. The primary bus controller 28 remains essentially transparent for execution of I/O format instructions and translates memory mapped format instructions into sequential bus cycles compatible to an I/O bus interface for processing conventional I/O format instructions, and for execution by the floating point processor core.

Abstract: A data compression/decompression processor (a single-chip VLSI data compression/decompression engine) for use in applications including but not limited to data storage and communications. The processor is highly versatile such that it can be used on a host bus or housed in host adapters, so that all devices such as magnetic disks, tape drives, optical drives and the like connected to it can have substantial expanded capacity and/or higher data transfer rate. The processor employs an advanced adaptive data compression algorithm with string-matching and link-list techniques so that it is completely adaptive, and a dictionary is constructed on the fly. No prior knowledge of the statistics of the characters in the data is needed. During decompression, the dictionary is reconstructed at the same time as the decoding occurs. The compression converges very quickly and the compression ratio approaches the theoretical limit. The processor is also insensitive to error propagation.

Abstract: Test circuitry for a counter of n number of bits is described. The circuitry includes that which divides the counter into s number of segments when the counter is being tested in a test mode. The invention also includes circuitry for detecting when each segment nears the last count and overriding test mode to reenable a between-segment clock path between the segments before the last count to permit the last count to ripple through the counter to test connections between the segments on the next clock cycle. Previous test implementations did not test the interface between segments because of the prohibitive cost in tester time. In one embodiment, assuming equal numbers of b bits per segment, to fully test a counter using previous techniques, 2.sup.(n-b) +2.sup.b clock cycles would be required. In this technique, only (s-2)+2.sup.b clock cycles are required.

Abstract: Rotate circuitry operable to perform rotate operations on various size operands including preconditioning circuitry (10) for duplicating an operand a predetermined number of times to form a preconditioned word. The rotate operation is performed by shifter (22) which shifts the preconditioned word by a specified number of bits. For rotate through carry operations, Cy bit of the carry flag is inserted in the preconditioned word prior to shifting.

Abstract: A microprocessor has a plurality of input/output pins and processing coupled to the input/output pins. Circuitry is provided for selectively decoupling the processing circuitry with one or more of the input/output pins such that pins associated with enhanced features may be decoupled to provide compatibility with a desired microprocessor architecture.

Abstract: An integrated circuit, such as a microprocessor or math coprocessor, having a clock generator circuit for generating a high frequency internal clock signal based on an external input signal is disclosed. A clock generator circuit comprises circuitry for detecting an active edge of an input signal, circuitry for generating a plurality of clock edges responsive to the detection of the clock signal and circuitry for inhibiting the edge generating circuitry after generation of a predetermined number of clock edges. The factor by which the input clock signal is multiplied may be set by the circuit designer, or programmably set, without impact on the circuit design. Hence, a single circuit may be used to generate clocks of various frequencies. Further, the duty cycle of the generated clock is independent of the input clock signal.

Abstract: A carry skip adder uses independent paths for propagating a skip carry bit and a carry-in bit. Propagation of the carry-in bit is inhibited during a first portion of the clock cycle to prevent spurious carry-in signals from affecting the operation. During this period, other logic functions may be performed, including calculation of the propagation bits and generate bits for each adder block.

Abstract: A foveal vision evaluation instrument and procedure enables a precise evaluation of the visual function of the fovea centralis (macula) area of the retina. A foveal profile is developed to document the presence and state of foveal degeneration manifested by foveal segmentation and incremental changes and abnormalities in foveal vision, such as are caused by age related macular degeneration.Beam source optics 10, beam polarization optics 20 and image selection system 30 provide a polarized projection beam PPB that transmits an image array obtained by directing one component of polarized projection beam PPB through an image transparency IT. Image element blanking optics 40 enables the individual elements of the image array to be selectively blanked using a multi-cell electro-optic shutter 45.

Abstract: An integrated custom underwater diving system including backpack, weight system, bouyancy compensator, and equipment bag. The backpack has adjustable shoulder supports for conforming to the shape of the shoulders and torso of a diver and an integral weight system having a quick-release mechanism. The equipment bag has a plurality of compartments for storing and safely transporting diving equipment, the back and ends of which are provided with a semi-rigid sheath for protecting the contents of the bag during shipping, and compartments along the sides thereof for receiving diving fins which provide protection along the sides of the bag during shipment. The backpack is designed for removably mounting on the front of the equipment bag such that the backpack provides protection to the front of the bag during shipping and handling. The equipment bag is also provided with straps which allow the bag to be carried on the backpack to and from dive sites.

Abstract: The disclosed bookholder incorporates a viewing window with either an integral or detachable magnification element that permits magnified viewing of the pages held beneath the viewing window.

Abstract: A time slot interchange switch matrix incorporates processor-controlled diagnostic functions to provide programmable on-line/off-line diagnostic monitoring. The switch matrix output can be tri-stated during program-selected time slots while remaining electrically connected to the PCM buses, allowing redundant switch matrices to share on-line time slot interchange switching in any programmable manner. Inject and monitor circuitry enables the switching function of the on-line switch matrix to be tested time slot by time slot under program control using unused time slots. Parity checking, including verification of check circuitry, is provided for input PCM data, control memory addressing output, and data memory output through the tri-state output drivers. In addition to on-line inject and monitor testing, the off-line switch matrix selectively monitors the output of the on-line matrix to confirm that it is driving the PCM buses.

Abstract: The disclosed calibrated ASV measurement apparatus provides accurate measurements of the ASV (apparent surface voltage) on a photoconductive imaging medium using a relatively low cost, commercially available ASV probe. To obtain accurate ASV measurements, the probe sensitivity (relating probe voltgage output to sensed potential) is periodically recalibrated to compensate for changes in environmental and electrical conditions. The calibration function is implemented using a calibration target mounted directly to the housing of the probe's sensing head so as to occupy a portion of the probe's sensing field. During periodic calibration intervals, when the ASV probe is responsive only to potentials on the calibration target, known potentials are applied to the calibration target, and an indication of a change in probe sensitivity with respect to the calibration target is calculated and used to recalibrate the value for probe sensitivity used in ASV measurement.

Abstract: An angle servo preamplifier for use in the tracking antenna servo drive sem of a precision tracking radar system. The angle servo preamplifier processes tracking error signals indicative of tracking antenna pointing errors with respect to a target. The preamplifier is comprised of an input differential amplifier stage, a phase control stage, a sample and hold stage and a power amplifier stage. In addition, interfacing circuitry is included for coupling the preamplifier to the azimuth/secant correction system of the tracking radar system. The sample and hold stage includes "deglitching" circuitry for suppressing sampling/switching transients. And, to accommodate a bipolar tracking error signal while utilizing a single voltage supply, the power amplifier stage performs d.c. level translation.

Abstract: A system for measuring the transfer immitances, impedance and admittance, a linear electrical network having one or more ports. The system utilizes clamp-on ferromagnetic cores to electromagnetically couple the transfer immitance measuring system to the electrical network without having to interrupt the normal on-line operation of the electrical network. A high frequency injection network, which includes a high frequency signal generator and a multichannel amplifier, injects a high frequency signal into each of the ports of the electrical network. High frequency voltage and current measuring networks are electromagnetically coupled to each of the ports of the electrical network to measure the high frequency component of the port voltage and the port current.

Abstract: Methods and apparatus for treating water/wastewater to remove grit, susped and colloidal solids of organic and inorganic nature, microorganisms and surfactants. Dense suspended solids (grit) are first removed by a centrifugation process. The influent water/wastewater is then passed through coagulation and flocculation chambers, an upflow clarifier and a high-rate settling chamber for final sedimentation. Next, the influent passes through a foam filter to remove colloidal particles. The water/wastewater under treatment is then pressurized and saturated with air and subsequently depressurized, causing the dissolved gas to bubble out of solution floating out suspended contaminants. At this point, ozone is introduced into the influent to create a thicker, more dense foam by oxidizing organic matter and for disinfection purposes. The foam floated to the surface of the influent is scraped off and furnishes the foam for the foam filter.