Abstract: A data processing device is composed of four data processing modules (100, 102, 104, 106) which include mutually corresponding processing means (12, 14, 16, 18) and storage modules (28, 30, 32, 34) which are connected thereto, which data processing system includes an interconnection network (82, 84, 86, 88) which is fed by the respective data processing modules in order to apply bytewise generated processing results from any data processing module to any other data processing module. Each data processing module comprises an input decoder (54, 56, 59, 60) for receiving such intercommunicated processing result and therefrom reconstructing a correct bytewise processing result from mutually incongruent processing results so received even in case of failure of one data processing module for feeding to the local processing means.

Abstract: A description is given of a data processing network that is constructed as a product network of two or more factor networks. At least one of the factor networks is a chordal ring of at least five stations, or a generalized chordal ring. A generalized chordal ring is formed by dividing each of the stations in a chordal ring (124, 130, 136) into a number of sub-stations. The sub-stations within a station constitute a homogeneous network. The external connections of a station are divided over the relevant sub-stations. In this way an optimum value for the degree (G) and diameter (D) of the network can be chosen on the basis of a selection strategy.

Abstract: Large-scale time-division switching arrangements often consist of a central switching network and a series of so-called concentrators. For establishing an H1 switching a series of wideband concentrators are connected to a central wideband switching network if the wideband concentrators are of a modular structure and communicate through an internal bus system and an interface circuit with the central wideband switching network connected thereto, a distribution switching in the direction of the subscriber station and a testing of the concentrators while in operation can be effected in a simple way.

Abstract: In a method of aligning objects and in particular, of aligning optically readable disc-shaped information carrier. The objects are preferably optically scanned line-by-line in a direction transverse to their direction of movement. A reference picture line with an optically characteristic picture content is detected to allow alignment relative to known positions. To detect the reference picture line, the picture contents of all the picture lines are compared with each other and the corresponding correlation coefficients are determined. The reference picture line is that picture line whose picture content correlates least with the picture content of any other picture line.

Abstract: A system for transmitting an n-level data signal (d.sub.k) at a given symbol rate 1/T comprises a data transmitter (1), a transmission channel (2) and a data receiver (3) with an equalizer (30) of the decision feedback type. By arranging this equalizer (30) for forming an estimate (c.sub.k) of a virtual m-level data signal (c.sub.k) instead of the output signal (b.sub.k) of the data transmitter (1) error propagation in the equalizer (30) is considerably reduced without thereby appreciably adding to the implementation-complexity of the system.

Abstract: A modified Booth multiplier for multiplying an m-bit number X by an n-bit number Y comprises a Booth encoder for converter the number Y in groups of 3 bits which overlap by 1 bit into a series Y' of multiplication values whose number is equal to or substantially equal to half the number of bits of Y. There is also provided a multiplex circuit for forming partial products from the number X and said series Y' and a matrix configuration of full adders for adding the partial products in incremental positions. The design is such that the constituent components and the operation of the modified Booth multiplier can be tested by means of a very small number of test patterns which are generated in the Booth multiplier after application of a specific series of X,Y-values.

Abstract: A method of transmitting at least two measured values by means of light pulses which are passed by an optical transmitter through an optical transmission path to an optical receiver and whose relative separation in time is proportional to the measured value. The energy consumption for the optical transmission of the measured values is reduced by transmitting needle pulses cyclically, one after another in the same order of succession, in that per measured value an optical measuring pulse is transmitted, whose separation in time from the optical measuring pulse associated with a preceding measured value is proportional the magnitude of the measured value, and in that for each group of measured values an optical identification pulse is transmitted, whose distance in time from a preceding measuring pulse is smaller than the smallest possible distance in time between two successive optical measuring pulses.

Abstract: In sorting an input file on the basis of parameter values of the objects, monotonically varying chains of the objects are formed first. In an inspection phase these chains are selected from which the selection objects will be found as k firsts of the selection objects in the output file, as well as the following selection object. Next, all the objects which on the basis of the parameter value need not function later than the (k+1).sup.th selection object are incorporated in a sub-file, transported to a direct sorting machine and, if necessary, the chain formation is then repeated.

Abstract: An arrangement for cancelling the composite echo signal formed by, for example, a linear component and a variable-phase component, comprises a linear echo canceller and a variable phase echo canceller, the difference circuits of these echo cancellers being arranged in cascade. The adjustable signal processing arrangements of each echo canceller are controlled for minimizing a predetermined function (mean square value or time average of this means square value), either of a residual echo signal appearing at the output of the difference circuit of this echo canceller itself or of a residual echo signal appearing at the output of the cascade arrangement of the difference circuits. In all cases the signal at the output of the linear echo canceller contains only a residual variable-phase signal which can be compensated for by the variable-phase echo canceller.

Abstract: This encoding arrangement has an input (12) for receiving a sequence of samples to be encoded, an output for supplying encoded samples, processing circuits, more specifically:a differential circuit (20) for producing differential samples between the samples to be encoded and prediction samples,a prediction circuit (22) to produce prediction samples from the encoded samples.It is characterized in that the processing circuits are separated into encoding units (E1, E2, E3 and E4) for each effecting a processing operation on each sample to be encoded and that an interleaving member (60) is provided to convert the sequence of samples to be encoded into a sequence of interleaved samples so as to ensure that all the processing operations to be effected on a sample are indeed effected.

Abstract: The transmitter (DTR) and the receiver (DRC) of a system for transmitting data signals at a given symbol rate 1/T comprise discrete-time smearing filters (SM and DSM) for combatting the effect of additive pulse-like disturbances (p'(t)) in the transmission channel (TCH). In many cases these disturbances (p'(t)) turn out to have a pronounced bandwidth-limited nature. By utilizing this feature the implementation of the smearing filters (SM and DSM) is simplfied and/or their performance level is improved in that the non-zero values of their impulse responses s(i) and d(j) only occur at the points of grids of the indices i and j recurring with a period of L, where L is an integer greater than 1 and where L is determined substantially by the ratio L.sub.0 of the symbol rate 1/T to twice the highest significant frequency f.sub.m of these disturbances (p'(t)).

Abstract: The transmission restoration for faulty operating paths is generally constituted by a direct transmission restoration or a centrally controlled transmission rerouting. In the substitute direct transmission rerouting, N restoration links are permanently assigned to M operating paths, so that when faults affect more than N operating paths, M-N operating paths do not have the possibility to switch to the restoration link. With the centrally controlled transmission rerouting the employment of the restoration link requires reporting this fault to the supervising station as well as transmitting the control message from the supervising station to the switching matrices. The time required thereto generally causes all connections through the faulty operating path to be broken.

Abstract: The device comprises an input terminal (1) for receiving an electric signal and an output terminal (2) for supplying the binary digital signal. The input terminal (1) is coupled to the output terminal (2) via an equalizing unit (3) and a limiter circuit (7). The output (5) of the equalizing unit (3) is coupled to a first point of constant potential (16) via a clipper circuit (20). The output (8) of the limiter circuit (7) is coupled to the input (6) via an impedance (23). Further, the input (6) is coupled to a second point of constant potential (earth) via an integrating element (24). FIG. 1.

Abstract: The invention relates to a method of taking measurements along an optical transmission path by means of an optical sensor. The optical sensor includes an optical converter whose optical attenuation properties can be influenced according to the value to be measured and through which a first beam portion of a high-frequency amplitude-modulated optical transmission beam is passed. A second beam portion of this transmission beam is conveyed via a delay element. The second beam portion is applied together with the first beam portion outputted by the optical converter, via the transmission path as a receive beam to the receiver arrangement. In this way the modulation change produced by the sensor is processed and evaluated as an information about the measure value. Measuring a value at the transmitter end is possible with any optical transmission path of an undefined length, without recalibration of the receiver arrangement, because the optical transmitter beam is additionally subjected to low-frequency modulation.

Abstract: Circuit arrangement for synchronizing the units in the switching exchanges and repeaters of a time-division multiplex transmission system. In time-division multiplex transmission systems a central control device (first unit) is frequently employed to process messages to be transmitted. For a regular mode of operation, the second units provided for the different functions require a plurality of clocks which are phase-synchronized with the clocks of the first unit. For this purpose either a plurality of clock lines between the first unit and the peripherals (second units) are provided or clocks are transmitted through two clock lines at the highest and lowest clock rates and synchronized with the frequency divider arranged in the peripherals (second units) in a master-slave relationship.

Abstract: A control arrangement for controlling and coordinating the required switching operations in a switching network is designed among others to search idle switching time slots which can be used for a requested four-wire communication connection. Thereto a recording memory is used for continuously recording for each time switch the idle-busy condition of switching time slots. During the search for idle switching time slots for a four-wire communication connection which has to be established via separate time switches at the input of the network, at least one pair of idle locations in the recording file which can be suitable for a four-wire communication connection that has to be established via one and the same time switch is skipped and reserved before a pair of idle locations in this recording file representative of the searched switching time slots for the requested connection that has to be established via separate time switches, is seized.

Abstract: A random access memory (1) is described in which one address of a row of addresses is activatable. There is also realized a block addressing mode in which all addresses between a selectable first address and a selectable second address are activated. To this end there are provided two address registers (4, 5) and a logic tree structure (8) which consists of modules. At each level of the tree structure a module receives a part of the information from the two address registers in order to determine, possibly co-controlled by information received from a higher level of the tree, whether one or both limit addresses are situated within the address range covered by the module and, if the answer is negative, to determine whether all addresses of this address range must be activated or remain deactivated.

Abstract: Arrangement for receiving numerical data transmitted in the form of multiplexed packets in the video channel of a television transmission system, particularly comprising a circuit for recognizing data whose output signal (V) is used to authorize the transfer of the data signal (D) from a demodulator to a demultiplexer by means of an switching circuit (16a). The circuit (160) for recognizing the data comprises a D flip-flop (31) receiving the data signal (D), an exclusive-OR gate (33) whose inputs receive the data signal (D) and the output signal (D') of the D flip-flop (31) and which supplies from its output a signal (DX) applied to the input of a synchronous control module (32) which stores a given sequence of successive states of its input (36) during the opening period of a time window generated by a window generator (34) and which supplies the recognition signal (V) for authorizing the transfer when the said sequence of successive states is essentially a sequence of high states.

Abstract: In a data processing device which consists of a plurality of parallel-operating modules, each of the four modules is provided with its own clock circuit. Synchronization is realized at the level of the cycle of the high frequency oscillation. This is realized in that each of the clock circuits includes a two-out-of-three majority decision device which is fed by the output clock signals of the other three clock circuits. The majority decision may have a simple logic structure and is connected to the actual clock function generator in order to reduce, using a readjustment circuit, the deviation between the clock function signal and the majority signal by a factor substantially smaller than one for each transition of the majority signal.

Abstract: The described circuit arrangement for converting a data signal having a constant bit rate and code words of different length into an output signal consisting of code words of constant length but with a variable bit rate while using a buffer memory comprises a first encoder which recognizes code words of the data signal and converts them into code words of equal length, said code words being written in the buffer memory, read out from this memory by a second encoder and being converted into code words of the output signal. The construction of the first encoder is characterized in that a first EPROM and a comparator are connected to the parallel outputs of a shift register through which the data signal with its bit clock is shifted. The output data of the first EPROM and of the comparator are transferred to an intermediate memory and simultaneously applied to the address inputs of a second EPROM.