Abstract: An improved real-time debugger accommodates high level language computer programs containing dynamic local data and process context switches. Information thus acquired is used to deduce the stack frame pointer. Inputs and outputs of a target processor are tapped to capture key instructions, particularly indicating context switches. A local tag memory in the debugger stores images of stack frames during context switches.

Abstract: Device for optical heterodyne detection of an optical signal beam and an optical transmission system provided with such a device. An optical heterodyne detection device is described in which with the aid of three controllable elements (A, B and C), to influence the state of polarization and having a limited control range, such as Faraday rotators or birefringent electro-optical crystals, the state of polarization of radiation originating from a local oscillator (30) is made to correspond to the signal beam transmitted through a long-distance transmission fibre (10).

Abstract: A method of, and system for, data transmission over a time division duplex channel in which at least one duplex voice channel constituted by a pair of non-adjacent time slots (or physical channels) in a succession of time frames is allocated for effecting a data transaction between a first and a second station, one of said pair of time slots (or physical channels) being normally designated for unidirectional transmission of data in a first direction between the first and second stations and the other of the pair of time slots (or physical channels) being normally designated for unidirectional transmission of data in a second direction, opposite to the first direction.

Abstract: An improved magnetic core for focussing electrons leaving the accelerating anode of an X-ray tube has rounded poles. Non-magnetic sealing material is placed between the poles and the magnetic core is sealed to the accelerating anode and to the target asesmbly, so that no separate drift tube is needed.

Abstract: An interface for a connection network between individual stations and a physical medium used for the message traffic between these stations, where signals supplied via the physical medium are converted into a bit stream by means of a demodulator, such a bit stream being converted into signals to be transmitted via the physical medium by means of a modulator, a protocol control unit is connected thereto and communicates, via a communication memory bus, with a communication memory a first part of which is reserved for the communication software which is stored as the primary program.

Abstract: A system for providing testing capability of individual submodules on an integrated circuit module. A test bus having a plurality of conductors is connected to selected internal ports of said submodules through three-way analog switches. Each three-way analog switch provides the capability to observe and control an internal port through combination of the ON/OFF status of two transmission gates. Test patterns for controlling the transmission gates may be provided by onboard D flip-flops which are externally programmed to control or observe ports of an individual submodule.

Abstract: In the ISDN system complex line adapting circuits are provided on the two sides of the transmission line and they handle an extensive protocol. These circuits are divided into two sub-circuits connected to one another over fixed interfaces. The sub-circuit which is located nearest to the transmission line, however, is to have a considerably varying structure depending on the transmitting medium. For a modular structure it is now proposed to subdivide this sub-circuit into two partial circuits interconnected over a newly created simple binary interface. Thus, only the partial circuit which is located nearest to the transmission line needs to be specifically designed for the transmitting medium, for example, glass fibre lines, whereas the protocol management is performed in the other partial circuit, which always has the same structure irrespective of the transmitting medium.

Abstract: Electronic telephone set, comprising a transmission circuit arranged for being coupled to a telecommunication network and for receiving and transmitting speech signals, a keyboard means comprising a first matrix with respective numbers of intersecting first and second conductors and at the intersections of the first and second conductors key switches coupled to the respective first and second conductors for producing dial information and status information and including a second matrix with one intersecting first and second conductor or a plurality thereof respectively, and having setting circuits conducting current in one and the same direction coupled to the respective first and second conductors at selected intersections of the latter first and second conductors, whereas all second conductors of the second matrix are arranged common to those of the first matrix, and including a control circuit arranged for generating dialling signals compatible with the telecommunication network in response to the dialling

Abstract: A configuration space is used for path planning and for controlling the motion of an object. The configuration space includes states which contain cost to goal and direction arrow values. These values indicate a path or absence of a path from the states to at least one goal state. The configuration space is differentially updated after a cost to goal or direction arrow value is changed.

Abstract: An arrangement of data cells which stores at least one matrix of data words which are arranged in rows and columns, the matrix being distributed in the arrangement in order to deliver/receive, via a single bus, permuted data words which correspond either to a row or to a column of the matrix. Each data cell is connected to the single bus via series-connected switches which are associated with a respective addressing mode, the switches which address a same word of a same mode being directly controlled by a same selection signal.Circulation members enable the original order of the data on the bus to be restored. An arrangement of this kind is used in a layered neural network system for executing the error backpropagation algorithm.Application: Calculator, microprocessors, processor, neural network system.Reference: FIG. 4.

Abstract: A data processing system includes a microcomputer (1) provided with an address latch (5). The microcomputer is provided with a watch-dog arrangement which comprises the usual clocked counter (17) an output (Qn) of which is coupled to a reset input (RST) of the microcomputer. In order to increase the number of malfunctions to which the watch-dog responds the microcomputer is arranged to repeatedly generate reset signals each in the form of a complete byte X or Y which alternate. These are applied to an input (30) of a comparator (10) which compares them with identical bytes fed to a further input 31 via a switched multiplexer (13), the comparator output (37) being connected to a reset input (RS) of the counter. Each time this occurs the microcomputer strobes the watch-dog by applying its address to a further input (46, 22).

Abstract: The invention relates to a switching network for a communication system, comprising m/1 stages and in which cells are transmitted in accordance with a time-division multiple access method and the switching is effected on the basis of the routing information contained in the header. The arriving cells are temporarily stored in a buffer until a free frame is available. The queues built up in the buffers of the m/1 stages are to be processed in the most fair manner. For this purpose it is proposed to assign a memory to each m/1 stage of each auxiliary line (Zl . . . Zm), to which memory are applied the results of the comparisons between routing information and address of the trunk line (A) and to determine for the decision circuits the order in which the cells stored in the buffers (B) are read out.

Abstract: The device includes a parent microcontroller in a bond-out version and a derivative microcontroller in a non-bond-out version, in order to emulate the derivative microcontroller. To this end, the parent microcontroller is connected to an external program memory by means of memory connection pins. The derivative microcontroller comprises an additional functional processing facility, an internal program memory and a processor element. Upon emulation the derivative microcontroller receives an emulation control signal. Communication means between the processor and the internal program memory on the one side and the additional functional process facility on the other side are thus deactivated. Finally, the two microcontrollers are interconnected and connected to an external program memory in such a manner that a series of standard pins and the processor of the parent microcontroller are activated, and the external processing section of the derivative microcontroller and said external program memory are activated.

Abstract: An improved bus system of a type suitable for connecting various consumer devices in the home. The system eliminates the need for either a central control device or a list of interconnections between the consumer devices. Instead a local interconnection table is stored in each device. The invention also uses an automatic priority system to prevent a user from inadvertently destroying earlier established signal paths.

Abstract: Microcontrollers generally comprise, in addition to the actual processor, a program memory which is constructed as a read-only memory. In order to enable testing of the contents of the program memory without making these contents also available to the environment of the microcontroller, the reference data of the program are externally supplied and the comparison is performed inside the microcontroller. In accordance with the invention this test is preferably performed as a small test program which is preferably stored in an additional read-only memory in the microcontroller which operates in the test mode and which performs this test. Consequently, except for the memory for the test program, this test program requires hardly any additional hardware.

Abstract: A communication system is described comprising different buses which are interconnected via one or more gate connecting elements. There is a transmitter station transmitting a frame that comprises a target address field and one or more destination address fields. If the send and receiver stations are connected to the same bus, the contents of the target address field are sufficient to define the receiver station. In other cases the target address field defines a gate connecting element, whereas the latter fills the the target address field with the contents of one of the other fields. In this way receiver station addresses, which have already been defined on a previous bus, can again be used on the next bus. Furthermore, in a short-frame format, receiver stations on the same bus as the transmitter station can be addressed with very low overhead.

Abstract: Ghosts in a video signal containing a predetermined reference signal are adaptively cancelled with a sparse transversal filter having fewer multipliers than delay taps. A reference signal identical to the reference signal in the video signal is generated and filtered with the sparse transversal filter. The filtered reference signal and the generated reference signal are subtracted from the part of the video signal containing the predetermined reference signal and the result of the subtraction is compared with a threshold value. The filter multipliers are connected to the delay taps in correspondence to the results of the subtraction which exceed the threshold value, and the multiplier values are adjusted to minimize the result of the subtraction.

Abstract: A digital cordless telephone system which comprises a primary station (PS) controlled by a system controller (14 or 15) and a plurality of secondary stations (SS) capable of communicating with the primary station by way of a time division duplex radio link, the primary and/or secondary station having means to generate a beacon signal which is receivable by a secondary station outside the range of normal speech communication and the beacon signal comprising a low bit rate signal which is transmitted at a power comparable to the digitized speech signal. In one embodiment the beacon signal is recovered using a narrowband filter and a demodulator. In another embodiment direct sequence spread spectrum techniques are used to send the beacon signal and a correlator/matching circuit is used to recover the low bit rate data representative of the beacon signal.

Abstract: Apparatus for rearranging signal channels of a multi-loop TDM transmission system, each loop having a plurality of high rate channels CI in successive base frames, portions of successive base frames forming a plurality of low rate channels CS. The system capacity can thereby readily be expanded by including additional loops. In order to rearrange a plurality p of asynchronous TDM signals into the correct channels to constitute a plurality of synchronous outgoing TDM signals, the apparatus includes respective units SRI for providing synchronization and rearrangement of the signals in the high rate (CI) channels. The p outputs of the SRI units are connected to p respective inputs of an interloop switching unit CII for switching the CI channels, and also to p respective inputs of an interloop switching unit RCIS which rearranges and switches the CS channels.

Abstract: A method and apparatus for a time division multiplex transmission of data packets from a plurality of access units in a communications network having a pair of oppositely directed unidirectional buses between which the access units are coupled, each access unit transmitting its data packets in empty time slots on a first of such buses. A queue is formed in each access unit of the data packets therein, and each time a further data packet is added to such queue a request flag is transmitted on the second bus. A count is kept of the number of request flags passing the access unit on the second bus, and such further data packet is assigned a priority value corresponding to the number of request flags existing at the time the further data packet is added to the queue.