Abstract: An apparatus is provided for reducing read latency for an I/O device residing on a first bus having a first, short read latency timeout period. The apparatus includes a I/O bridge on a second bus having a second, longer read latency timeout compared to that of first bus which modifies read transactions into two separate transactions. A first transaction is a write transaction to the same address requested by the read transaction. This transaction forces a write-back if the address hits in a CPU's write-back cache. Thereafter the read transaction is performed after a predetermined period of time following initiation of the write transaction. This removes the possibility of a device on the first bus having a short read latency timeout period from exceeding it's read latency timeout limit.

Abstract: A memory of a computer system is sized and configured after the memory has been loaded with data. The sizing and configuration of the memory causes the data to become scattered among memory chips on a single memory module or among two or more memory modules. To gather the data, gather code loads itself into the instruction cache of the computer system and while executing from the instruction cache configures the memory and gathers the data in the memory such that it is again located at the same address it held before the configuration occurred.

Abstract: A method of testing a circuit design is provided which allows for the comparison output of an abstract reference model of the circuit and the circuit itself to the same set of input stimuli. The circuit under test may operate in a manner which produces unpredictable events, results, or data. Due to the nature of the reference model, unpredictable results, data, or events are not allowed to occur. Thus to compare the outputs of the two as a means of verifying the circuit design, the testing method allows for a comparison analysis of the outputs despite the possibility of unpredictable data and events occurring on the circuit and not the model.

Abstract: A computer system for executing a binary image conversion system which converts instructions from a instruction set of a first, non native computer system to a second, different, native computer system, includes an run-time system which in response to a non-native image of an application program written for a non-native instruction set provides an native instruction or a native instruction routine. The run-time system collects profile data in response to execution of the native instructions to determine execution characteristics of the non-native instruction. Thereafter, the non-native instructions and the profile statistics are fed to a binary translator operating in a background mode and which is responsive to the profile data generated by the run-time system to form a translated native image. The run-time system and the binary translator are under the control of a server process.

Abstract: A method and apparatus for performing division in accordance with certain bandwidth requirements particular to an implementation is described. A pseudo pipelined approach for performing division using the SRT non-restoring division algorithm is described which uses a minor clock and a major clock cycle time. The number of stages in the division pipeline is a function of the parameters bandwidth requirements of the system. The pseudo pipeline division technique iterates for several minor cycles rather than having individual hardware associated with each minor cycle in the division pipeline. High division bandwidth requirements are provided while minimizing the amount of hardware and the area occupied by the associated hardware.

Abstract: A method and apparatus for configuring a computer system is presented. Underlying system software communicates information to a configuration utility. The information identifies a particular operating system that executes in the computer system. Using this information, the configuration utility formulates configuration filenames and retrieves data from the configuration files describing system resources, system device requirements, and operating system constraints. The configuration utility performs the system configuration by allocating system resources to system devices in accordance with the operating system constraints and system device requirements.

Abstract: A method executed in a computer system for detecting and handling an invalid use of a data structure is described. The method includes the steps of providing a data structure associated with a first computing environment. The data structure includes a field having a value stored therein identifying an inaccessible address in a second computing environment. This field is used in detecting an invalid use of the data structure in the second computing environment by a computer program attempting to access memory using said inaccessible address indicated by said value contained in the first field. Additionally a preferred data structure is described as are alternative embodiments of detecting an invalid use of a data structure.

Abstract: A computer system with multiple execution boxes operates by assigning serial numbers to each instruction in a set of linearly dependent computer instructions and then rearranging those instructions into a set of instructions which are no longer linearly dependent. The original serial numbers assigned to each instruction are retained with the instructions after rearrangement. The serial numbers allow reconstruction of the original set of instructions from the rearranged set of instructions. Once rearranged, additional information is added to subsets of the rearranged set of instructions. The additional information allows several instructions to be executed in parallel while producing the same results as would have been produce had the instructions been executed one at a time by a sequential processor.

Abstract: A method and apparatus for determining when an Input/Output (I/O) module should prefetch cache lines of data from main memory. Following a request for data from a peripheral, connected to an I/O bus which supports a flexible protocol allowing peripherals with various capabilities to operate, the I/O module will request a cache line of data from main memory containing a beginning portion of the requested data. The I/O module may then prefetch consecutive cache lines containing requested data according to the operating parameters of the peripheral requesting the data and the requested data. The I/O module may prefetch in such way that neither system bus bandwidth nor I/O bus bandwidth is wasted.

Abstract: Disclosed is a semiconductor package and method in which a semiconductor chip is mounted within the opening of a lead frame by bonding wires extending between the active front side of the chip and bonding pads of the lead frame, and the lead frame/chip assembly is encased within a plastic molded body, with the inactive back side of the chip exposed and facing outside the package.

Abstract: A method in accordance with the invention involves the normalization of a C language-type data structure received by a process in a distributed computing environment (DCE) to ensure that padding bits are consistently used. The method steps may advantageously be performed by a client process prior to and subsequent to a remote procedure call (RPC) to ensure that the padding bits are not undesirably changed as a result of the RPC. The method steps can also be performed by a server process to ensure that the structures it receives in RPCs are consistent in their use of padding bits. Normalization of the data structure permits a memcmp( ) or similar comparison function to be used to compare data structures without the risk that dissimilar padding bits will result in a false negative from the comparison.

Abstract: A jacketing system automatically interfaces dissimilar program units during program execution on a computer system. Means are provided for detecting a call for execution of a second program unit having a second call standard form a first program unit having a first call standard during execution of the first program unit on the computer system. A procedure descriptor is used in the code for the first program unit and it includes a signature that defines the call standard for each incoming call to the first program unit. A bound procedure descriptor is also used in the code for each outgoing call from the first program unit and it includes a signature that defines the call standard for the target program unit. Jacketing routines are driven by the descriptors in jacketing calls between the two program units.

Abstract: A method and apparatus for controlling the providing of conditioned AC power, with the conditioned AC power being capable of being provided on a continuous basis. Unconditioned AC voltage is received by transverters. The transverters convert the unconditioned AC voltage into a transverter AC output voltage. The transverter AC output voltage is monitored by current and voltage sensors. A transverter control signal is developed in response to changes in the current and voltage sensing in comparison with a reference signal. The transverter control signal then regulates conversion of the transverter AC output voltage into the desired conditioned AC output voltage. In multi-phase AC voltage systems conditioned AC voltages for each phase are provided.

Abstract: A commander module including means for determining whether control of a system bus is required, means for requesting control of the system bus, prior to determining whether such control is required, and means, responsive to the determining means, for indicating that control of the system bus is required. A computer system including the system bus and at least two such commander modules coupled to the system bus and including means for arbitrating for control of the system bus including means for granting control of the system bus to one of the commander modules indicating that control of the system bus is required and having the highest arbitration priority among those commander modules also indicating that control of the system bus is required.

Abstract: Techniques used in testing software are described. A test generator produces a source program used to test two or more compilers using a differential testing technique. The test generator includes a grammar with added semantic constraints to minimize the generation of non-conforming source programs. The source program is a conforming source program conforming to constraints included in a programming language standard. By using properties of a conforming source code, a differential testing technique is described in which a test failure indicates that one or more of the compilers is not processing the source program correctly in accordance with the programming language standard. If a test failure is detected, the source program causing the test failure is reduced using various reduction and simplification techniques.

Abstract: A distributed computer system employs a license management system to account for software product usage. A management policy having a variety of alternative styles and contexts is provided. Each licensed program upon start-up makes a call to a license server to check on whether usage is permitted, and the license server checks a database of the licenses, called product use authorizations, that it administers. If the particular use requested is permitted, a grant is returned to the requesting user node. The product use authorization is structured to define a license management policy allowing a variety of license alternatives by values called "style", "context", "duration" and "usage requirements determination method". The license administration may be delegated by the license server to a subsection of the organization, by creating another license management facility duplicating the main facility.

Abstract: A method of forming cobalt silicide on source/drain regions and polysilicon gate areas of an MOS integrated circuit uses an improved technique to prevent unwanted oxidation of cobalt or growth of silicide on other areas of device. A thin titanium nitride (or titanium tungsten) film is deposited on top of a cobalt film following the steps of patterning the polysilicon gate, source/drain implant and sidewall oxide spacer deposition and etch. The titanium nitride film allows formation of defect-free cobalt silicide during an elevated-temperature anneal. Without the titanium nitride film, the cobalt is likely to oxidize and/or form cobalt silicide in unwanted regions of the device, which can cause device failure.

Abstract: A computer system with multiple execution units operates by treating a logical program as a tree structure with segments which include several computer instructions. Segments of the tree structure are connected by nodes which represent decisional instructions in the logical program. Serial numbers are assigned to each instruction within each of the tree structure. The instructions and then rearranged into a set of instructions which are no longer linearly dependent. The original serial numbers assigned to each instruction are retained with the instructions after rearrangement. During rearrangement, path information is added to each instruction to indicate its commit point. The serial numbers and path information allow reconstruction of the original set of instructions from the rearranged set of instructions. The path codes represent a path through the tree structure to a particular one of the segments in which all of the instructions in the associated subset will be committed in logical terms.

Abstract: In a computer system, an improved technique detects and executes cross-domain calls in an application program. The invention determines whether a branch target address falls within a reference address range within a first domain. If it does, the invention executes the call by determining a called address in a second domain corresponding to the target address in the first domain, e.g., by mathematically manipulating the target address. The invention then accesses the called address and executes the code stored therein. The invention may be used in detecting and executing cross-domain calls from an application program executing by interpretation in an emulated computer system having a first architecture (e.g., "CISC"), where the calls seek execution of specified system services functions executable directly in a computer system having a second, different architecture (e.g., "RISC"). The invention also may be used in a computer system having multiple processors of heterogeneous architectures.