Abstract: A method and system for analyzing a substrate including the step of scanning the substrate to produce an intensity signal which represents the topography of the wafer to a first order. Other contributions to the signal intensity may be chemical composition and electrical state of the scanned features on the substrate. The scanned signal is compared and correlated to a reference signal to assess the substrate. The present invention is also directed to a method of manufacturing a wafer using the method and system and improving the manufacturing quality of product.

Abstract: A gate or capacitor insulator structure using a first grown oxide layer, a high-k dielectric material on the grown oxide layer, and a deposited oxide layer on the high-k dielectric material. The deposited oxide layer is preferably a densified deposited oxide layer. A conducting layer, such as a gate or capacitor plate, may overlay the densified oxide layer.

Abstract: A method for making an oxide layer on a silicon substrate produces an oxide layer including graded portions with greatly reduced stress. The method includes growing a first oxide portion over a substrate by upwardly ramping the substrate to a first temperature lower than a SiO2 viscoelastic temperature. Thereafter a second oxide portion is grown between the first oxide portion and the silicon substrate by exposing the silicon substrate to an oxidizing ambient at a second temperature higher than the SiO2 viscoelastic temperature. The second oxide portion may have a thickness in a range of about 25 to 50% of a total thickness of the graded oxide layer.

Abstract: A method of manufacturing a semiconductor device employing a polishing pad conditioner that directs a fluid stream at a polishing pad to remove accumulated material from the pad. The fluid stream may contact a large area of the polishing pad or a smaller area where the fluid stream is moved to condition different areas of the polishing pad. The fluid stream may include abrasive particles to promote the removal of the accumulated materials. The velocity of the fluid stream may be increased or decreased to promote removal of the accumulated materials. In yet another embodiment, the present invention is directed to a process for manufacturing an integrated circuit using a CMP process where the pad has been conditioned using the fluid stream. The present invention is also directed to a chemical mechanical planarization system including a pad conditioner.

Abstract: A method of forming low stack height transistors having controllable linewidth in an integrated circuit without channeling is disclosed. A disposable hardmask of doped glass is utilized to define the gate and subsequently protect the gate (and the underlying substrate) during ion implantation which forms the source and drains. A variety of silicided and non-silicided) structures may be formed.

Abstract: An integrated circuit with a buried layer for increasing the Q of an inductor formed in the integrated circuit. The substrate includes a highly doped buried preserving device and latchup characteristics. The inductor may also include an increased thickness conductive layer in the inductor to further increase Q. The present invention is also directed to a low loss interconnect.

Abstract: A method for forming tungsten plugs and layers is disclosed. A thin layer of polysilicon or amorphous silicon is formed within a contact opening. The silicon is exposed to WF6, thereby forming a tungsten plug.

Abstract: A process for forming a dual damascene structure. The process includes forming a stack including insulating layers and a stop layer where two masks are formed above the stack. One of the masks is used to form via or contact openings in the insulating layers and the second mask is used to form grooves for interconnections in the insulating layers. In an alternative embodiment, the grooves are formed before the via or contact openings.

Abstract: The invention includes a process for copper metallization of an integrated circuit, comprising the steps of forming tantalum on a substrate, forming tantalum nitride over the tantalum, forming titanium nitride over the tantalum nitride, forming copper over the titanium nitride and integrated circuits made thereby. The invention is particularly useful in forming damascene structures with large aspect ratios.

Abstract: The present invention relates to a conductive plug capacitor and method of making for use in multi-level integrated circuit structures. In one embodiment, a tungsten plug is formed in a window in a dielectric layer and thereafter a cavity is formed in the plug. This cavity in the plug may serve as the lower electrode for the capacitor, with a layer of dielectric deposited in the cavity and a top metal electrode deposited on the dielectric layer. An alternative embodiment makes use of not only the inner cavity surfaces of the cavity in the tungsten plug, but also the outer sidewalls of the tungsten plug. To this end, after formation of the tungsten plug heading the cavity formed therein, a partial etchback of the dielectric layer in which the tungsten plug is formed is effective. The capacitor dielectric is then deposited on the sidewalls, the top surface and the interior of the cavity of the tungsten plug thereby increasing the area and thereby the over capacitance.

Abstract: A method of manufacturing an integrated circuit using an imaging system having a mask and an energy source that produces an exposure field. A substrate is moved across the exposure field while changing the depth of focus of the imaging system relative to the substrate. The depth of focus may be changed by moving the substrate, the mask, or both, relative to each other changes the depth of focus. The depth of focus may be oscillated according to a periodic waveform where the waveform is equal to the time for a typical point on the substrate to pass through the exposure field.

Abstract: The present invention provides a method for fabricating a capacitor, comprising the steps of forming a trench in a substrate, forming a layer of a first material selected from the group consisting of titanium and titanium nitride in the trench, filling the trench with a conductive material to form a conductive plug, planarizing the substrate, patterning the substrate to partially expose the first material and to create a top portion and a bottom portion to the plug, wherein the bottom portion is in the substrate, and removing the first material from the top portion of the plug.

Abstract: An improved method of integrated circuit fabrication is described with a photolithographic step involving pattern decomposition. A desired final pattern is decomposed into two or more component patterns for photoresist imaging, leading to improvements in image fidelity.

Abstract: A method of depositing aluminum or other metals so that vias are more completely filled is disclosed. The wafer or substrate is preheated to a temperature of approximately 200.degree. C. Then the wafer is placed in an ambient of approximately 350.degree. C. while metal deposition commences. The resulting metal layer has a gradually increasing grain size and exhibits improved via filling. Also disclosed is a method and apparatus (involving cooling of support structures) for deposition of an antireflective coating to prevent rainbowing or spiking of the coating into the underlying metal.

Abstract: A process for fabricating novel dual-polysilicon structures comprises forming trenches of differing depths in a field oxide that overlies a substrate. Utilizing an ion implantation barrier in the trenches, ion implantation is performed to create self-aligned structures. Importantly, polysilicon is formed in the trenches in a single deposition.

Abstract: A polishing process to planarize a layer formed on a substrate and to reduce the variations in the thickness of that layer from substrate to substrate. The polishing process is implemented by polishing a substrate using a stable pad material. A stable pad material is formed from a polishing material that has substantially the same or similar density, hardness, and compressibility as polyurethane but is a material other than or substantially other than polyurethane. In an alternative embodiment, the material for the polishing pad may be selected for its compression, high tensile strength, wear resistance and/or resistance to water, diluted acids, and alkalis. In a further alternative embodiment, the material forming the polishing pad may be selected from the group comprising hydrogenated nitrile compounds, fluoroelastomers, or perfluoroelastomers.

Abstract: Microwave radiation, perhaps with microwave absorbing materials, is utilized to provide heating of partially formed integrated circuits in a variety of circumstances.

Abstract: A controller for residential telephone wiring. Apparatus associated with the controller provides multiple communication channels on ordinary residential telephone wiring. The controller (1) routes incoming calls to a selected telephonic device within the residence, (2) routes outgoing calls to a free external line servicing the residence, and (3) routes calls within the residence from one telephonic device to another.

Abstract: Crochralski wafers are desirably thermally processed at an elevated temperature prior to integrated circuit fabrication. The thermal processing reduces the number of oxygen nucleation centers and prevents subsequent oxygen precipitation from interfering with iron contamination measurements.

Abstract: A method of manufacturing integrated circuits using a carrier fixture. The carrier fixture does not include transport channels or openings for directing a slurry to a substrate being polished and, as a result, damage to the substrate is reduced because the edges adjacent to the substrate are eliminated. The present invention further provides a carrier fixture having an inner support coupled to a ring member that contacts a substrate during the CMP process. The present invention also provides a carrier fixture having inner and outer supports coupled to a ring member.