Abstract: A method and apparatus for the manufacture of integrated circuits including the placement of a single tube for introduction of dopant gases into a process chamber is disclosed.

Abstract: A system for deriving multiple channels from four-wire residential telephone wiring. The invention provides two voice channels and two, or more, data channels on common residential telephone wiring. The voice channels occupy a normal telephone bandwidth, in the range of approximately zero Hz to 3500 Hz. Within this channel placement, ordinary telephonic devices can use the channels, without a requirement of frequency-shifting. Above these voice-channel frequencies, data channels are provided, for internal communication within the residence.

Abstract: A method for fabricating a multi-level integrated circuit is disclosed which utilizes a grid pattern from which portions corresponding to the metal layer are selectively removed to form a mask which is subsequently used to deposit dummy features in the open areas between metal lines, thereby to allow the deposition of a substantially planar dielectric surface over the metal layers and dummy features.

Abstract: The quartz shadow ring of a conventional plasma etching apparatus is desirably coated with material which inhibits the liberation of oxygen into the plasma. Investigation has shown that the liberated oxygen degrades etching uniformity across the wafer.

Abstract: A carrier fixture that does not include transport channels or openings for directing a slurry to a substrate being polished. The carrier fixture may have an inner support coupled to a ring member that contacts a substrate during polishing. The carrier fixture may also have outer supports coupled to the ring member. The carrier fixture is used to manufacture integrated circuits.

Abstract: A novel process for forming a window, illustratively, an emitter window BiCMOS process is disclosed. An anisotropic etch followed by an isotropic etch to open the window is disclosed. The isotropic etch prevents contamination of the substrate by the anisotropic etching process.

Abstract: Semiconductor integrated circuit processing is facilitated by an etch process illustratively applied to polysilicon and silicon nitride removal. The etch process illustratively comprises of the use of phosphoric acid with metal-containing additives to bring about an enhanced silicon etch rate effect.

Abstract: Gate oxides having different thicknesses are grown on a semiconductor layer by the process which comprises forming a semiconductor layer on a substrate, growing an oxide layer on the semiconductor layer, exposing a selected area of the oxide layer, amorphizing the semiconductor layer underlying the exposed oxide layer, removing the oxide layer to expose the semiconductor layer having both amorphized and non-amorphized regions and growing gate oxide on the amorphized and non-amorphized regions of the semiconductor layer. Gate oxide grown on the amorphized regions will be thicker than gate oxide grown on the non-amorphized regions.The process of the invention obviates the need for special integrated circuit manufacturing design modifications and can be utilized to fabricate a wide variety of devices, in particular, MOS-type devices.

Abstract: A method of fabricating an integrated circuit device is described in which fluorine ions are implanted into the patterned photoresist and the exposed polysilicon layer prior to etching the polysilicon. The ion implantation minimizes the chemical reaction between the photoresist and etchant, thereby significantly reducing the formation of polysilicon etch delta, and also significantly reducing etch delta variation due to pattern density variations.

Abstract: An update block for an adaptive RAM-based equalizer filter configuration includes a multiplier, an adder, and a plurality of delay units. The multiplier, adder, and delay units are coupled in an manner so as to have the capability to perform full-rate equalizer filter coefficient adaptation. In accordance with another embodiment of the invention, a method of updating a coefficient signal for an adaptive RAM-based equalizer filter configuration is provided. The method selectively variably delays an error signal sample produced by the adaptive RAM-based equalizer filter configuration and an equalizer filter input signal sample and computes with selectively variably error signal sample and the selectively variably delayed equalizer filter input signal sample. Finally, the coefficient signal is updated by adding the product to the coefficient signal.

Abstract: Briefly, in accordance with one embodiment of the invention, a method of compensating for Doppler error in a wireless communications system employing Viterbi decoding comprises the steps of: for each signal sample in a first predetermined-sized grouping of received signal samples, performing a parallel Viterbi update and short symbol decode; and for a second predetermined-sized grouping, forming by pipeline processing an estimate of the Doppler error in accordance with the parallel short traceback decoding performed for the first grouping, and adjusting each signal sample in the second grouping in accordance with the estimated Doppler error.Briefly, in accordance with another embodiment of the invention, a Viterbi traceback reconstructed signal sample index comprises: a state counter, a traceback shift register (TBSR); a signal reconstruction table; and a comparator coupled in a configuration so as to provide the sign bit to the TBSR from a comparison of binary digital signals.

Abstract: A novel capacitor design for use in semiconductor integrated circuits is disclosed. The capacitor includes a metal-dielectric-metal stack formed within a window and upon a conductive substrate. Contact to the top plate of the capacitor is through a window within a window, while contact to the bottom plate is achieved by a guard ring which contacts the conductive substrate.

Abstract: Undesirable counter doping of n.sup.+ /p.sup.+ gates illustratively through cross diffusion through an overlying silicide is inhibited by insertion of layers of titanium nitride and titanium, tungsten or tantalum between the polysilicon gates and an overlying silicide.

Abstract: Illustratively, the present invention includes a method of integrated circuit manufacturing which includes forming a raised topological feature upon a first substrate. A portion of the raised feature is removed, thereby exposing a cross sectional view of the raised feature with the substrate remaining substantially undamaged. The cross sectional view has a critical dimension. The critical dimension of the cross sectional view is measured using a first measuring instrument. Then the critical dimension is measured using a second measuring instrument. The measurements of the first and second measuring instruments are correlated. Then, using the second measuring instrument, raised features via plurality of second substrates are measured.