Abstract: A semiconductor component having a semiconductor chip mounted on a packaging substrate and a method for manufacturing the semiconductor component that uses batch processing steps for fabricating the packaging substrate. A heatsink is formed using an injection molding process. The heatsink has a front surface for mating with a semiconductor chip and a leadframe assembly. The heatsink also has a back surface from which a plurality of fins extend. The leadframe assembly includes a leadframe having leadframe leads extending from opposing sides of the leadframe to a central area of the leadframe. A liquid crystal polymer is disposed in a ring-shaped pattern on the leadframe leads. The liquid crystal polymer is partially cured. The leadframe assembly is mounted on the front surface of the heatsink and the liquid crystal polymer is further cured to form a packaging assembly, which is then singulated into packaging substrates.

Abstract: The invention relates to discrete, spaced-apart ferroelectric polymer memory device embodiments. The ferroelectric polymer memory device is fabricated by spin-on polymer processing and etching using photolithographic technology. The size of the discrete, spaced-apart ferroelectric polymer structures may be tied to a specific photolithography minimum feature dimension. The invention also relates to a process for making embodiments of a polymer memory device that includes discrete, spaced-apart ferroelectric polymer structures. The discrete, spaced-apart ferroelectric polymer structures may have a minimum feature that is tied to the current photolithography that may reduce the voltage and increase the switching speed.

Abstract: Briefly, in accordance with an embodiment of the invention, a method and system to store cache metadata from a higher latency media in a lower latency media is provided.

Abstract: In an aspect, an apparatus is provided that sets and reprograms the state of programmable devices. In an aspect, a method is provided such that an adhesive is formed on a dielectric and on an electrode, the adhesive is patterned exposing the electrode, and a programmable material is formed on the adhesive and on the electrode. In an aspect, a method is provided such that an adhesive is formed on a dielectric, an opening is formed through the dielectric exposing a contact formed on a substrate, and a programmable material is formed on the adhesive and on a portion of the contact. A conductor is formed on the programmable material and the contact transmits to a signal line.

Abstract: Briefly, in accordance with an embodiment of the invention, an apparatus and method to provide refreshing of a memory cell of a phase change memory device is provided. The method includes determining whether a storage level of a phase change memory cell is within a predetermined margin from a resistance threshold. In response to the determination, the cell is selectively written. The apparatus includes a circuit to: determine whether a storage level of a phase change memory cell is within a predefined margin from a resistance threshold level; and in response to the determination, selectively write to the cell.

Abstract: One embodiment of the invention relates to a polymer memory device and a method of making it. The polymer memory device may include a composite or single layer of a ferroelectric polymer memory that addresses surface engineering needs according to various embodiments. The ferroelectric polymer memory structure may include crystalline ferroelectric polymer layers such as single and co-polymer compositions. The structure may include spin-on and/or Langmuir-Blodgett deposited compositions. One embodiment of the invention relates to a method making embodiments of the polymer memory device. One embodiment of the invention relates to a memory system that allows the polymer memory device to interface with various existing hosts.

Abstract: A cell in a structural phase-change memory is programmed by raising cell voltage and cell current to programming threshold levels, and then lowering these to quiescent levels below their programming levels. A precharge pulse is then applied which raises the bitline voltage of the selected cell and does not raise the cell voltage and cell current to their programming levels. Then, the cell current is raised to a read level which is below the programming threshold level, and the bitline voltage is compared to a reference voltage while the cell current is at the read level.

Abstract: A method comprising forming as stacked materials on a substrate, a volume of programmable material and a signal line, conformably forming a first dielectric material on the stacked materials, forming a second dielectric material on the first material, etching an opening in the second dielectric material with an etchant that, between the first dielectric material and the second dielectric material, favors removal of the second dielectric material, and forming a contact in the opening to the stacked materials. An apparatus comprising a contact point formed on a substrate, a volume of programmable material formed on the contact point, a signal line formed on the volume of programmable material, a first dielectric material conformally formed on the signal line, a different second dielectric material formed on the first dielectric material, and a contact formed through the first dielectric material and the second dielectric material to the signal line.

Abstract: The present invention is a method and apparatus for data communication between controllable devices, and more particularly, between a first programmable device (21) and at least one second programmable device (31) coupled to a processor. In one embodiment in accordance with the present invention, the second programmable device (31) includes an addressable memory location and an output, and is adapted to receive data from a processor. In this embodiment, the first programmable device (21) is programmed to decode at least one addressable memory location from the processor and enabled to transmit each address to each second programmable device (31) in a first simultaneous write operation. The first programmable device (21) then selects at least one of the second programmable devices (31) to output a signal (33) corresponding to the data in a second write operation.

Abstract: A three-dimensional (3D) memory device having polysilicon diode isolation elements for chalcogenide memory cells and method for fabricating the same are described. The memory device includes a plurality of stacked memory cells to form a three-dimensional (3D) memory array. The memory device also includes a polysilicon diode isolation element to select a chalcogenide memory cell. The memory device is fabricated by forming a plurality of chalcogenide memory cells on a base insulator. The memory device is also fabricated by forming a polysilicon diode isolation element to select a chalcogenide memory cell.

Abstract: The invention relates to a phase-change memory device. The device includes a double-trench isolation structure around the diode stack that communicates to the lower electrode. The present invention also relates to a method of making a phase-change memory device. The method includes forming two orthogonal and intersecting isolation trenches around a memory cell structure diode stack.

Abstract: A pickup tool (30) has reflective surfaces (42, 44, 46, 48) attached thereto. The pickup tool (30) picks up an object (38) and moves the object (38) over a light source (51). The reflective surfaces (42, 44, 46, 48) reflect a light beam (61) emitted from the light source (51), generating deflected light beams (63, 65, 67, 69) which back light the object (38). The deflected light beams (63, 65, 67, 69) form silhouette images of the object (38) in cameras (52, 54, 56, 58). A visual inspection of the object (38) is performed by analyzing the images.

Abstract: A digital-to-analog conversion circuit including a plurality of unit current output cells (1) arranged in a matrix. Each of the current output cells (1) includes a unit current source (11) having a power supply input and a current output, and a selecting switch (12) connected to the current output and having two switching output terminals. The circuit further includes at least one ½ and/or ¼ weighted current output cell (2) disposed on a row in the matrix, and at least one ½ and/or ¼ supplementary current source (8) disposed on a desired row so that the total current consumption of the unit, weighted and supplementary current sources on each row is substantially the same. A decoder responds to a digital signal to control the switching of the selecting switches one by one as the digital signal gradually increases.

Abstract: An alarm circuit (10) includes a sensor (11), a comparator (13), a control circuit (16), and a transducer (19). The control circuit (16) controls the transducer (19) and has three modes of operation: standby mode, alarm mode, and silence mode. The comparator (13) compares the voltage of an input signal from the sensor (11) to a first threshold level during the standby mode of operation. The control circuit (16) enables the transducer (19) and transitions to the alarm mode of operation after the voltage of the input signal exceeds the first threshold level. The control circuit (16) disables the transducer (19) for a predetermined time period and transitions to the silence mode of operation after a silence signal is received by the control circuit (16). The input signal is compared to both the first threshold level and a second threshold level during the silence mode.

Abstract: An integrated smart power circuit including a power semiconductor device fabricated on a conducting substrate with a source positioned adjacent the upper surface of the substrate, a control terminal between the upper and lower surfaces, and a drain positioned adjacent the lower surface of the substrate. A high resistance layer is formed on a portion of the upper surface of the substrate, either directly overlying or adjacent to the power device, and doped semiconductor material is positioned on the high resistance layer. Control circuitry is formed in the doped semiconductor material. The high resistance layer can be conveniently formed by growing a layer of AlAs and growing doped layers on the AlAs. The AlAs can be easily oxidized thereafter.

Abstract: A method forms a plastic package (28) for a sensing die (10) having a pressure sensitive diaphragm (22), wherein the diaphragm (22) has a first surface (24) and a second surface (26) disposed opposite the first surface (24). According to this method, the sensing die (10) is mounted overlying a hole (18) in a die bond pad (16), which is used to support the sensing die (10) in the package (28). Next, the sensing die (10) is enclosed within a mold (12,14), and a molding material is introduced into the mold's interior to form the package (28) around the sensing die (10). During molding, the pressures on the first and second surfaces (24,26) of the diaphragm (22) are sufficiently equal to substantially prevent damage to the sensing die (10).

Abstract: A mold compound made from a polymer resin and an isorefringent, transparent filler is used to form optical electronic components (10, 20, 30). The mold compound can be used to form a lens (13) on a display device (10), to form the outer housing (21) of a waveguide (20), or to form a dome (34) that reflects light from a light emitting device (32) to a light detecting device (33).

Abstract: A non-volatile memory cell (81) includes a drain-side select transistor (86), a source-side select transistor (87), and a storage transistor (88). The drain-side select transistor (86) is adjacent to the drain of the storage transistor (88) to prevent drain-disturb events. The source-side select transistor (87) is adjacent to the source of the storage transistor (88) to prevent source-disturb events. The select gate (152) of the drain-side select transistor (86), the select gate (143) of the source-side select transistor (87), and the floating gate (147) of the storage transistor (88) are formed on a dielectric layer (123) having a uniform thickness.

Abstract: A circuit (70) includes a reset stage (72) and a Phase-Locked Loop (PLL) device (73). The PLL device (73) includes a phase detector (74), a charge pump (75), a filter (76), and a Voltage-Controlled Oscillator (77). The reset stage (72) receives a reference signal and is connected to the phase detector (74). The phase detector (74) receives the reference signal and a feedback signal. When the reference signal switches from a first clock signal to a second clock signal, the reset stage (72) places the phase detector (74) in an inactive state until the reset stage (72) detects a falling edge in the reference signal.

Abstract: An electrostatic discharge (ESD) protection circuit (20) includes an active load circuit (22) connected to a Laterally Diffused Metal Oxide Semiconductor (LDMOS) transistor (21) having a Lightly Doped Drain (LDD). The active load circuit includes a current limiting circuit (26) and a load transistor (27). The ESD protection circuit (20) operates to protect a power transistor (16) from damage due to an electrostatic charge. During an ESD event, the LDMOS transistor (21) enters avalanche breakdown after the voltage of the electrostatic charge exceeds the breakdown voltage of the LDMOS transistor (21). The ESD protection circuit (20) provides a low resistance path during an ESD event to dissipate the electrostatic charge.