Abstract: A Phase-Locked Loop (PLL) system (30) and a method for modifying the output transition time of the PLL system (30). The PLL system has an input stage (36) connected to a PLL (37). The input stage (36) includes a phase detector stage (47), a phase difference threshold stage (48), and a phase difference modification stage (49). The input stage (36) receives a reference input signal and a feedback input signal and determines the phase difference between these two input signals. If the phase difference is greater than a predetermined value, then the input stage (36) decreases the phase difference between the reference input signal and the feedback input signal. If the phase difference is less than the predetermined value, then the phase difference between the reference input signal and the feedback input signal is not modified.

Abstract: A flexible shelf (12) and a method for coupling a semiconductor chip (33) to a leadframe (23) using the flexible shelf (12). The flexible shelf (12) has a mounting portion (16), a flexible portion (17), and a leadframe support portion (18). The flexible shelf (12) is used in a wire bonding support assembly (10) to provide support for the leadframe (23) during wire bonding. The flexible portion (17) of the flexible shelf (12) flexes to increase thermal conductivity between a heater block (29) and the leadframe (23) during wire bonding.

Abstract: An electronic component (10) is formed by encasing individual components within a glass tube (20). The individual components can include a semiconductor die (11), leads (12,13), and dumets (16,17). The glass tube (20) is transparent and melts at a temperature less than other commercially available materials.

Abstract: The occurrence of invalid data transitions on an output data bus (17) are reduced with an improved data sensing circuit (20). In a single block memory application, a self-controlled sense amplifier (21) eliminates the need for external timing control signals by triggering off the rail-to-rail voltage swings of a complementary bit line pair (BIT, BITB) of a memory array coupled to the inputs of the amplifier (21). Triggering off the bit lines (BIT, BITB) ensures that the amplifier (21) is not activated until valid data appears at its input, thereby preventing glitches on the output data bus (17) due to the amplifier (21) or associated latch (13). In a multiblock memory application, the data sensing circuit is further improved by eliminating invalid data transitions from appearing on the output data bus (17) through use of feedback.

Abstract: A capacitor (30) compatible with wirebonding processes and a method for manufacturing the capacitor (30). The capacitor (30) includes a first plurality of conductive layers and a second plurality of conductive layers spaced apart by a plurality of dielectric layers. The first plurality of conductive layers is electrically connected to a peripheral contact (74) of the capacitor (30). The second plurality of conductive layers is electrically connected to an interior portion of the capacitor (30). The first plurality of conductive layers is interleaved with the second plurality of conductive layers.

Abstract: A switched capacitor differential comparator (10) for receiving input signals which includes hysteresis circuitry (40, and 42) and a switch (43) responsive to timed clocking pulses occurring during alternating reset and comparison periods for application of a hysteresis current during a reset period of the differential comparator which current is injected into an applicable one of a pair of load devices (22, 24) to produce a hysteresis voltage offset at a selected one of the differential inputs (30, 32) which is stored during the reset period but removed during the next comparison period so that the hysteresis voltage is not canceled but remains superimposed on the stored input signals during the next comparison period to introduce hysteresis to influence the current output decision of the comparator circuit based on the decision of the comparator resulting from the previous comparison period.

Abstract: A sigma-delta modulator (10) and a method for digitizing an analog signal. The sigma-delta modulator includes at least one switch (16) for altering the order of the sigma-delta modulator (10). The order of the sigma-delta modulator (10) is changed based on the communication protocol of the received analog signal. More particularly, the order of the sigma-delta modulator (10) is increased for communication protocols having wide information-bandwidths. Alternatively, the order of the sigma-delta modulator (10) is decreased for communication protocols having narrow information-bandwidths.

Abstract: A sequence generator 10 for a frequency synthesiser 1,2,3,4,5,10 forming part of a direct modulator comprises an input 10a for receiving an input multibit signal X(z), an output 10c for outputting an output digital signal Y(z) and sequence generation means 10b. The sequence generation means is adapted to produce a noise transfer function which has a minimum value both at the frequency corresponding to the dc component of the input signal and at one or more frequencies away from the frequency corresponding to the dc component of the input signal.

Abstract: An input circuit (20) and a method for protecting the input circuit (20) from positive and negative overvoltages. The input circuit (20) includes an N-channel Metal Oxide Semiconductor Field Effect Transistor (MOSFET) (12), a P-channel MOSFET (13), a Zener diode (21), and a diode-connected transistor (22). The P-channel MOSFET (13) protects the N-channel MOSFET (12) from negative overvoltages. The Zener diode (21) and the diode-connected transistor (22) protect the N-channel MOSFET (12) from positive overvoltages. In addition, the Zener diode (21) protects the P-channel MOSFET (13) from positive overvoltages.

Abstract: An overvoltage protection device (40) and a method for increasing the overvoltage current the device can carry. The overvoltage protection device (40) includes a Silicon Controlled Rectifier (SCR) (11) and an SCR enhance circuit (42). The SCR enhance circuit (42) provides the SCR (11) with an additional low resistance path to increase the amount of overvoltage shunt current the SCR (11) carries during an overvoltage event.

Abstract: An amplifier circuit (10) and a method for increasing linearity of the amplifier circuit. The amplifier circuit (10) has a limiter (13) that generates a phase modulated signal (30) in accordance with a phase modulated component (22) of an RF input signal (20). The amplifier circuit (10) also has an envelope detector (16) that generates an envelope signal (40) in accordance with the amplitude modulated component (21) of the RF input signal (20). A delay compensation circuit (17) receives the envelope signal (40) and generates a lead phase envelope signal (50) and an envelope amplifier (18) receives the lead phase envelope signal (50) and generates a bias signal. An RF amplifier (14) amplifies the phase modulated signal (30) in accordance with the bias signal.

Abstract: A protection circuit (20) protects a semiconductor device (10) from damage due to electrostatic charge transferred to a terminal (19) of the semiconductor device. A voltage follower (26) senses a voltage (V.sub.CHARGE) developed by the electrostatic charge to produce a follower voltage. A conduction path (30) is enabled with the follower voltage to discharge the electrostatic charge from the terminal before the voltage rises to a magnitude that damages the integrated circuit.

Abstract: A charge pump (102) and method of charge pumping a low voltage (V.sub.DD)) to generate a higher voltage (V.sub.PP). A primary pump (160, 179, 180) receives complementary clock signals (CLK1, CLK2) that control charging and transfer cycles of the charge pump. During the charging cycle, a capacitor (150) stores a charge developed from the low voltage. On the transfer cycle, the charge is transferred to an output (138, 177, 178) through a switching transistor (152) disposed in a well region (202) to develop the higher voltage. A secondary pump (162, 187, 188) charge pumps the output voltage to generate a more positive bias voltage for biasing the well region to disable a parasitic PNP transistor of the switching transistor.

Abstract: An electric motor (101) is driven with a sequence of drive pulses (V.sub.151, V.sub.153, V.sub.155) applied to its coils (131-135). The drive pulse widths are computed over a series of time periods (T.sub.DRIVE) by a pulse generator (119) to form envelopes approximating the phase voltages (VE.sub.151, VE.sub.153, VE.sub.155) of the coils to produce sinusoidal coil currents (I.sub.131, I.sub.133, I.sub.135). A sensing circuit (137, 123) monitors the phase of the coil current with respect to phase voltage to compute a representative control signal (CONTROL). The phase has one polarity when the motor is delivering power from a battery to a load and the opposite polarity when power is delivered from the load to the battery. When the direction of transferred power changes, the control signal changes and the pulse generator switches on-the-fly to another sequence of drive pulses.

Abstract: In a method for operating a brushless motor with commutated stator excitation and permanent rotor field, the stator is initially energized partly. Depending on the polarity of the back electromagnetic force (EMF) in the non-energized stator coil at a predetermined time point (t(n)+T.sub.OFF) and on the occurrence of a EMF zero-crossing event in a following time frame (T.sub.MONITOR), the next stator commutation (t'(n+1)) is scheduled. Thereby, three cases (i)(ii)(iii) are distinguished and detected events (.tau.(n-1)) in previous commutation cycles (n-1) are taken into account.

Abstract: A method (50) for designing a semiconductor device (10). The method (50) has an annealing step (59). In the annealing step (59), the semiconductor device (10) is annealed in an ambient containing oxygen. The oxygen has a partial pressure of greater than 11.85 Torr. The annealing step (59) results in a reduction of uncontrolled doping from the gate electrode (33) of the semiconductor device (10) to the channel region of the semiconductor device (10).

Abstract: A method for biasing a semiconductor laser (12) at the threshold level of the semiconductor laser (12). The method includes applying pilot tone signals having the same frequency to a bias current and a drive current of the semiconductor laser (12). A lateral detector (13) generates a photocurrent from spontaneous emissions of the semiconductor laser (12). Further, the method includes biasing the semiconductor laser (12) using a pilot tone signal of the photocurrent.

Abstract: In a ball grid array (BGA) station (50) having a robotic arm (60) with a vacuum head (70) containing a predetermined quantity of vacuum apertures (90), a method and apparatus of loading an array of solder balls (14) for solder bumping a carrier (20). Solder balls (14) are supplied into a tub (500) having a head opening (510) for accommodating a vacuum head (70). After the vacuum head (70) is positioned by the robotic arm (60) towards the head opening (510) of the tub (500), suitable fluid pressure (570) is applied to the solder balls (14) within the tub (500) to force the solder balls (14) to float on the gas pressure towards the vacuum apertures (90). The vacuum apertures (90), which are appropriately sized and annularly shaped has at least a partial vacuum (34) applied through the apertures (90) to suck-up a desired quantity of solder balls for eventual placement on the BGA carrier (20).

Abstract: A first pattern of bumps and a second pattern of bumps are formed on a substrate (10) with bumps (14,15). During a transfer process, only the bumps (14) of the first pattern of bumps are transferred to pad extensions (20) of a device (17). The bumps (15) of the second pattern of bumps are not affected by this process and can be later transferred to a second device.

Abstract: An image station (40) includes multiple light sources (43, 45, 47, 49) emitting lights of different colors to illuminate an object (41) from different directions, thereby forming multiple images of the object (41). Dichroic filters (54, 56, 58) separate lights of different colors from each other. Lights of different colors form images of the object (41) in corresponding cameras (53, 55, 57, 59) simultaneously.