Abstract: The device for retaining a slide and a pick to a stringed instrument includes a generally rectangular base having a top surface, and an arm unit extending over the base top surface. The arm unit includes an obliquely oriented slot arranged to accept and retain the pick therein. A gripping member extending from the arm unit forms a slide accepting area between the gripping member and the base top surface. A perimeter wall of the slide is inserted into the slide accepting area allowing the gripping member to apply a compressive force to the slide, retaining the slide to the device.

Abstract: A material system for manufacturing thick film resistors on a ceramic dielectric substrate is disclosed. The system includes the application and fixing of resistor terminations composed of a precious conductor material to a dielectric substrate. Resistor material is deposited over portions of the resistor terminations and to the dielectric substrate intermediate the resistor terminations. Terminal pads, conductor traces and resistor interconnections are printed on the dielectric substrate using a base conductor material. The resistor interconnections are deposited and fixed to the resistor terminations and to portions of the resistor material. The resistor material is trimmed to tolerance by kerfing the resistor material and a dielectric encapsulant is applied substantially over the resistor interconnections and resistor material.

Abstract: The bus extender circuit is a least replaceable unit which interfaces between intermodule subsystems and the microprocessor controller of the system. The bus extender circuits are structured so that the subsystem modules may be placed in different power zones. As a result, one subsystem may be powered down without affecting the other subsystems connected to the microprocessor's bus. In addition, the bus extender circuit converts from Fairchild Advanced Schottky TTL logic to high-speed CMOS logic and vice versa and allows bus interface gate arrays located in each subsystem to interface between the subsystem logic and the microprocessor. This bus extender circuit design eliminates the need for strapping options or DIP switches for address decoding.

Abstract: This circuitry permits equal access to a shared resource by a number of central processing units (CPUs). In a multiple CPU arrangement, common resource contention problems arise, when several CPUs attempt to access the common resource. To resolve these contention problems, this circuitry is an improvement to arbitration ring circuitry. The circuitry of this invention permits each of the CPUs equal access to the common resource during situations in which each CPU is constantly generating requests (high bandwidth utilization) for access to the common resource. This invention is particularly useful for systems in which a large number of CPUs must have their local memory rapidly reloaded from a common memory source. Reloading procedures for large numbers of CPUs rquire up to an hour. By employing the present invention, these reloading times can be cut from one hour to approximately 5 minutes.

Abstract: A laser DC bias controller is disclosed for controlling and monitoring the laser of a fiber-optic transmitter. The arrangement comprises an optical power monitor including a light detector for converting the light output by the laser into photo current. The photo current is converted by the optical power monitor into a voltage representation of the magnitude of the light output by the laser. The voltage representation is output to a DC constant current source which uses the voltage to provide operating current to the laser of sufficient magnitude to keep the laser operating at a set output level. A transmit data detector monitors the incoming data signals to the fiber optic transmitter and outputs to the optical power monitor a current signal which indicates a failure of the data signal. The optical power monitor converts the current signal to a voltage representation which is output to the DC constant current source.

Abstract: A substrate connector guide for installing and electrically connecting an electrical substrate to a carrier substrate. The substrate connector guide includes a plurality of guide rails mounted on the perimeter edge of the electrical substrate and at least a first electrical connector mounted transversely between the guide rails. First and second substrate guides are mounted to the carrier substrate in a spaced and parallel relationship to the other. Each substrate guide includes a channel extending longitudinally along a substrate guide inner side, from an open end to a top guide. The channel is further defined by a top surface and a plurality of drop guides which in turn form a plurality of slots. At least a second electrical connector is mounted and electrically connected to the carrier substrate between the first and second substrate guides.

Abstract: A substrate connector guide for installing and electrically connecting an electrical substrate to a carrier substrate. The substrate connector guide includes a plurality of guide rails mounted on the perimeter edge of the electronical substrate and at least a first electrical connector mounted transversely between the guide rails. First and second substrate guides are mounted to the carrier substate in a spaced and parallel relationship to the other. Each substrate guide includes a channel extending longitudinally along a substrate guide inner side, from an open end to a top guide. The channel is further defined by a top surface and a plurality of drop guides which in turn form a plurality of slots. At least a second electrical connector is mounted and electrically connected to the carrier substrate between the first and second substrate guides.

Abstract: An interface circuit for transmitting data and voice signals between a CENTREX equipped central office exchange and a remotely located attendant console. The interface circuit includes an analog interface arranged to receive analog voice signals from the attendant console and to convert the analog signals into digital signals for transmission to the central office exchange. Alternatively, digital signals received from the central office exchange are converted to analog voice signals and are transmitted to the attendant console. A digital interface connecting the attendant console and the central office exchange includes an interface controller arranged to control the operation of the digital interface.

Abstract: An arrangement for transmitting data messages between a CENTREX equipped central office exchange and a remotely located attendant console. The arrangement includes an operating unit residing in an interface circuit connected between the CENTREX and the attendant console. The operating unit includes sequential memory connected to the CENTREX and to a controller arranged to receive and store data message from the CENTREX. The CENTREX sends a data available signal to the controller signaling that a data message is available for transfer from the sequential memory. In response, the controller sends the CENTREX a sequential memory read control signal signaling that the controller is reading the sequential memory. State machine called by the controller transfers a first byte of the data message from the sequential memory to temporary memory.

Abstract: An arrangement for splicing and aligning two fiber optic cables is disclosed comprising a fixed connector stage and a movable connector stage. The fixed connector stage includes a fiber optic connector having a first fiber optic cable mounted therein. The first fiber optic cable has one of its ends connected to a source of light energy. The movable connector stage also includes a fiber optic connector having a second fiber optic cable housed therein. The two connector stages are located adjacent to the other with the two optical fibers coarsely aligned alog a horizontal axis. An alignment fixture is then mounted to the movable connector stage and an end of the second fiber optic cable connected to a photo-detector device. The light detector is electrically connected to a control device with the control device in turn electrically connected to the alignment fixture.

Abstract: An interface circuit for transmitting data messages between a remotely located attendant console and a CENTREX equipped central office exchange. The interface circuit includes control and sense decoders connected to control and sense fields. Receiving circuit connected to the attendant console receive data messages transmitted from the attendant console. A controller connected to the receiving circuit process the received data messages, storing the data messages in a temporary memory. Sequential memory connected to the temporary memory receive and store in sequential order the data messages after they are processed. The sequential memory further includes memory enabling circuit connected to the control and sense decoder.

Abstract: An interface circuit for transmitting data messages between a CENTREX equipped central office exchange and a remotely located attendant console. The interface circuit includes control and sense decoding circuitry arranged to output control signals to the interface circuit and transfer control signals and data messages to the CENTREX. Sequential memory connected to the control and sense decoding circuitry receives and stores from the CENTREX data messages responsive to an enabling signal from the CENTREX. The control and sense decoding circuitry signals a controller connected to the sequential memory that data messages have been loaded in the sequential memory. The controller then transfers the data messages out of the sequential memory and processes the received data messages, storing the data messages in a temporary memory. The controller transfers the data messages from the temporary memory to sending circuitry which transmits the data messages to the attendant console.

Abstract: An arrangement for initializing an interface circuit connected between a CENTREX equipped central office exchange and a remotely located attendant console. The arrangement includes an operating unit residing in the interface circuit. The operating unit includes a controller connected to memory and to the CENTREX. The controller receives an initialization signal from the CENTREX and returns an initialization in progress signal. Memory verification called next by the controller ascertains if all locations in the memory are operable. The controller sends an error signal to the CENTREX in the event the memory verifications detects an error. Next, interface initialization called by the controller resets and clears a sequential memory and resets and clears a send/receive circuit connected to the controller and the attendant console. Transmission verification called next by the controller checks if the transmit and receive loop between the attendant console and the interface circuit is operable.

Abstract: An arrangement for tranmitting data messages between a remotely located attendant console and a CENTREX equipped central office exchange. The arrangement includes an operating unit residing in an interface circuit connected between the attendant console and the central office exchange. The operating unit of the present invention includes receiving circuitry connected to the attendant console and to a controller. The receiving circuitry is arranged to receive a data message from the attendant console and set a receive signal. A state machine called by the controller transfers the first byte of the data message to a temporary memory and resets the receive signal. The state machine accepts all additional characters from the receiving circuitry storing received characters in the memory until a character sequence is received indicating the end of the data message. When a complete data message is received an analysis is called by the controller which analyzes the received data message.

Abstract: A control circuit for effecting the transfer of data messages between an interface circuit and a CENTREX equipped central office exchange. The central office exchange includes a peripheral processor and the interface circuit includes an input and an output sequential memory for receiving and sending respectively, data messages to the peripheral processor. An input control circuit includes a first gating means having inputs connected to the peripheral processor and which produces an output signal responsive to the simultaneous application of a first and a second control signal. First bistable memory means receives the gating means output signal and further includes a clock input connected to a write select signal from the peripheral processor. Responsive to the write select signal, the gating means output signal is stored in the first bistable memory means. Second bistable memory means connected to the first bistable memory means output includes a clock input connected to a source of clocking signals.

Abstract: An improved loop current supply circuit including a first amplifier connected to a source of bias voltage. The first amplifier is further connected to a subscriber loop circuit through the tip and ring conductors. The first amplifier receives the bias voltage and supplies loop current to the loop circuit. A second amplifier connected to the tip and ring conductors outputs a voltage representative of the amount of current in the subscriber loop. When the output voltage of the second amplifier becomes greater than the bias voltage, a loop voltage network connected to the second amplifier and to the bias voltage source shunts the bias voltage from the first amplifier, decreasing the current in the loop circuit.

Abstract: An improved AC impedance matching arrangement including a first amplifier connected to a subscriber loop through the tip and ring conductors of a subscriber line circuit. The first amplifier is arranged to supply loop current to the subscriber loop through first and second resistors. Each resistor having a set DC value. A second amplifier connected to the tip and ring conductors is arranged to develop and output a signal responsive to AC signals applied to the tip and ring conductors from the subscriber loop. A feedback circuit connected to the second amplifier is arranged to receive the second amplifier output signal and develop and output to the first amplifier an impedance matching signal. The impedance matching signal raises the impedance seen by the tip and ring conductors above the set DC value of the first and second resistors.

Abstract: An arrangement for connecting an array of individual electronic elements into a readily expandable matrix. The arrangement comprises a plurality of matrix slices with each slice including a set number of electronic elements as well as a row and a column buffer. The electronic elements of each matrix slice are diagonally connected to the elements of the adjacent matrix slice.

Abstract: An improved offhook supervision circuit including an amplifier connected to a subscriber loop through the tip and ring conductors of a subscriber line circuit. The amplifier is arranged to develop and output a loop voltage signal representing the level of the DC signals applied to the subscriber loop circuit. A comparator device has a first input connected to the amplifier and is arranged to receive the loop voltage signal output by the amplifier. A second input of the comparator device is connected to a reference voltage device which outputs a predetermined reference signal voltage. Any significant reduction of the DC signal level on the loop circuit will cause the loop signal voltage output by the amplifier to fall below the reference signal voltage. An offhook signal is then output from the comparator device to a control device signaling an offhook condition.

Abstract: An improved ringing generator is disclosed, for producing and transmitting an AC ringing voltage waveform to a subscriber line from a negative and positive DC voltage source. The ringing generator is characterized by a transformer having a primary winding and a secondary winding. The primary winding includes a plurality of taps dividing the primary winding into a plurality of winding segments. The secondary winding is connected to subscriber line via a filter network. Each winding segment is connected to a buffer-driver which has a first lead connected to the DC voltage source and a second lead connected to a source of control signals. Responsive to the control signals a selected pair of buffer-drivers are alternatively enabled connecting for a predetermined time period the associated coupling segments to the DC voltage source thereby, producing a switched ringing voltage waveform which is coupled to the secondary winding.