Abstract: A digital signal processing system includes first and second logical memory mapping units coupled to first and second digital processors respectively and to a data storage unit. The system further includes first and second mapping registers for containing first and second address mapping information coupled to the first and second digital processors respectively. The first and second mapping units are operative to receive (i) first and second logical addresses generated by the first and second digital processors respectively and (ii) first and second address mapping information respectively, and generate first and second physical addresses such that each of the digital processors can independently access any of a plurality of memory locations within the data storage unit.

Abstract: A suspend/resume computer system having a CPU, a non-volatile storage device, volatile registers and memory data, a power management processor, a backup suspend timer and a power supply in circuit communication. The power management processor controls the regulation of power to the CPU by the power supply. The suspend/resume system is controlled by an operating system having power management control. The backup suspend timer executes independently of the power management portion of the operating system. The backup suspend timer causes the system to suspend if the power management portion of the operating system ceases functioning and the system should otherwise be suspended.

Abstract: Advantage is taken of Very Large Scale Integrated (VLSI) circuit design and manufacture to provide, in a digital data handling system handling display signal streams, a video processor which is capable of high performance due to vector processing and asynchronous interrupt service. The VLSI device has a plurality of processors which cooperate for generating video signal streams and at least one and preferably at least two interrupt registers for controlling the operations of instruction data stream execution and interruption.

Abstract: A bridge is provided between an industry standard architecture (ISA) bus and a peripheral controller interconnect (PCI) bus and performs memory cycles on both buses simultaneously when a master on the ISA bus initiates a memory transfer. Data is steered between the ISA and PCI buses when a slave on the PCI bus claims the memory address within a predetermined time period after the memory cycle is initiated on the PCI bus. The ISA bus is isolated from the PCI bus when no slave on the PCI bus claims the memory address. This allows the memory cycle to be completed on the ISA bus, and the memory cycle on the PCI bus is terminated.

Abstract: This disclosure relates to a method and apparatus for measuring the amount of time a personal computer system is powered on. A power on time (POT) routine is performed at a power on of the computer system. This routine sets up a timer to count the number of pre-selected time units (selected by a user) the system is powered on. The power on time count is stored in the PC's non-volatile memory. The routine sets an alarm field of the system's real time clock (RTC) to be activated after the pre-selected time unit has elapsed. A POT interrupt handler routine is installed in a chain for RTC interrupts and is invoked each time the alarm is activated (i.e., at each passage of the pre-selected time unit) while the system is powered on. When invoked, the POT interrupt handler routine increments the POT count and resets the RTC alarm to be activated after another pre-selected time unit has elapsed.

Abstract: An interprocessor interrupt hardware unit ("IIU") for processing interrupts between a remote processor and a host processor on a multiprocessor system. The IIU off loads tasks involved in processing interrupts from the operating kernel of the remote processor. Control blocks of interrupt information and commands are stored in Data Random Access Memory (DRAM) by the remote processor. The remote processor sets up a buffer of control block memory addresses in DRAM for the IIU to access to retrieve the control blocks from DRAM. The IIU retrieves a control block and loads the control block into registers. The IIU then issues an interrupt request to the host processor. The host processor receives the interrupt request and reads the registers to obtain the control block. The host processor clears the interrupt request and indicates to the IIU that the interrupt has been processed. The IIU then notifies the remote processor that the interrupt has been processed.

Abstract: A computer system having at least three states of power management: a normal operating state, a standby state, and a suspend state. The standby state is characterized by devices, such as a video controller and a hard drive, being placed into a low-power mode transparent to the operating system and the applications executing on the computer system. The suspend state is characterized by executing code being interrupted and the state of the computer system being saved to a file on the hard drive in such a manner that system power may be removed after the state of the computer system is saved to the hard drive. Later, after system power is restored, the state of the computer system is resumed by reading from the hard drive and loading it in such a manner that the operating system and application programs are not adversely affected.

Abstract: This invention relates to personal computers, and more particularly to a personal computer using a small computer systems interface (SCSI) controller coupled directly to the local processor bus for controlling data transfer with storage memory devices such as fixed or removable media electromagnetic storage devices. The personal computer system has a high speed local processor data bus, at least one logical processor device coupled directly to the local processor bus and capable of signalling through the local processor bus an occurrence of the transfer of blocks of data, and a storage controller coupled directly to the local processor bus for regulating communications between the processor device and storage memory devices. The storage controller has a FIFO memory for transitory storage of blocks of data being exchanged with the local processor bus and is capable of signalling through the local processor bus the state of the FIFO memory.

Abstract: A lock assembly is disclosed for small computers and similar electronic devices of the type that must be locked yet must permit access for repair even when the proper key is not available to the repair person without requiring that the expensive lock or its mounting be damaged. Further, readily visible evidence of the forced access must be apparent to a casual observer of the computer. Forced entry detection is provided by the instant invention through the use of a fracture ring having support elements seated into recesses in a rebated cover opening which hold the lock assembly in place during normal use but which allow the assembly to become axially misaligned after the lock has been forced. Frangible portions of the lock support hold the lock assembly in both rotational and axial stability which stability is lost when the frangible portions are broken.

Abstract: Disclosed is a dual sensor comprising first and second touchpad sensors having different resolutions and being sandwiched to form a single sensor. Each of the touchpad sensors include a first plurality of electrically conductive strips positioned proximate to a second plurality of electrically conductive strips. The conductive strips in each plurality lie substantially in a single plane and the two pluralities are skewed relative to one-another in plan view. The conductive strips are separated by insulators that extend beyond the surface of the conductors to separate the conductors of one plurality from the conductors of the other plurality until a localized pressure is applied to a region of the pad. Two such touchpad sensors are sandwiched to form the dual sensor of the present invention. The two touchpad sensors are configured and positioned such that a single touch of a finger, stylus, or the like is capable of being detected by both sensors.

Abstract: A personal computer has two possible memory sizes differing by the maximum number SIMMs that can be installed. Each SIMM stores presence detect bits indicating the size and speed of the SIMM. An I/O controller includes a memory detect port which is used to read the presence detect bits from the SIMMs. The controller further includes a logic circuit that is set in accordance with the memory size to selectively control driving the presence detect bits or empty socket bits onto a data bus.

Abstract: A video display, which may be a television receiver with associated set top device, an intelligent television receiver, or a personal computer system enabled for television display, has associated therewith a remote control of the three axis type which controls modification of the visual images displayed.

Abstract: A video display, which may be a television receiver with associated set top device, an intelligent television receiver, or a personal computer system enabled for television display, has associated therewith a remote control which controls modification of the visual images displayed. By use of the remote control, a human observer may cause a processor controlling the video display to execute a control program formulated in a particularly concise language and controlling the display of menus and the like. Menus are displayed as overlays onto a live motion video image.