Abstract: The semiconductor memory has word lines; normal memory cells each having a storage capacitor; normal bit lines connected to the normal memory cells; a reference memory cell having a capacitor storing prescribed data; and a reference bit line connected to the reference memory cell. When a word line is selected, the potential of normal bit lines and of reference bit line changes according to the charge on the storage capacitors and on the reference capacitor. A current mirror circuit is also provided, which has a first transistor drain of which is connected to the reference bit line and second transistors drains of which are respectively connected to normal bit lines, the gates of the first and second transistors being connected in common to the reference bit line. Thus even though the capacitance values of ferroelectric capacitors is scattered, the scattering in bit line potentials during read operations can be prevented.

Abstract: A fixed-logic signal generated inside an integrated circuit is selectively supplied via selectors (Sm+1 to Sn) to input terminals (INm+1 to INn) of a function macro (1) for receiving signals whose logic levels are fixed to “H” or “L” on at least one test pattern. This eliminates any external input terminal for inputting such fixed-logic signal. When the integrated circuit includes function macros, they can be simultaneously tested with this construction.

Abstract: A surface acoustic wave device includes: interdigital transducers; first electrode pads that are connected to the interdigital transducers through wire patterns; and a piezoelectric substrate on which the interdigital transducers, the first electrode pads, and the wire patterns, are formed. In this surface acoustic wave device, at least one of the first electrode pads is not connected to a ground pattern, and the piezoelectric substrate has a conductivity in the range of 10?12/?·cm to 10?6/?·cm.

Abstract: Disclosed is disposable tableware which is completely degradable under environmental conditions without environmental contamination. The disposable tableware is prepared using environmentally friendly, completely degradable materials without additional chemical additives while maintaining the shape and function of general disposable tableware so that it is completely degraded under environmental conditions, thus not causing environmental contamination and problems associated with waste disposal such as separation from other wastes. Also, the present invention discloses a method of manufacturing such disposable tableware. The disposable tableware is prepared by compression-molding a composition including 1–30 wt % of crop residues, 1–30 wt % of corn flour, 1–10 wt % of paper mulberry bark, 1–10 wt % of a moss and 30–96 wt % of a grain flour mixture as the remaining part.

Abstract: A level conversion circuit that prevents the operation speed from decreasing when the power supply voltage decreases while appropriately performing level conversion. The level conversion circuit includes first and second PMOS transistors. A first NMOS transistor is connected to the first PMOS transistor and the second PMOS transistor. A second NMOS transistor is connected to the second PMOS transistor and the first PMOS transistor. A bias circuit, connected to the first and second NMOS transistors, generates a bias potential that is supplied to the first and second NMOS transistors and that is greater than the first voltage by a threshold voltage of the first and second NMOS transistors. The bias circuit further controls current, which determines the bias potential and flows to the bias circuit, in accordance with a control signal having the first voltage.

Abstract: A temperature sensor including two transistors having different emitter current densities and performing temperature detection based on the fact that the difference in voltage between base and emitter changes with temperature. The temperature sensor is provided with a feedback circuit for controlling respective collector voltages and emitter currents such that the collector voltages of both transistors vary according to similar temperature characteristics.

Abstract: A method of monitoring calibration of a spectrophotometric apparatus that includes one or more than one calibration algorithm for one or more than one analyte, involves measuring absorbance of a quality control material with the apparatus to obtain a measurement, calculating one or more than one value from the measurement using the one or more than one calibration algorithm, and comparing the one or more than one value with an assigned value given to the quality control material for each of the one or more than one analyte. The quality control material exhibits an absorbance spectrum having a negative slope for a continuous spectral segment from about 5 nm to about 200 nm in length, and the spectral segment includes a principal calibration wavelength for the one or more than one analyte. A reagentless method for determining the concentration of one or more than one analyte in a sample in a spectrophotometric apparatus having at least one primary calibration algorithm is also disclosed.

Abstract: High-tension cables 7U, 7V, 7W connect an inverter 6 disposed outside an engine compartment with a motor/generator 3 disposed in the engine compartment, the high-tension cables 7U, 7V, 7W are individually passed through metallic protection pipes 30 under a floor of a vehicle, the protection pipes 30 are supported from an underside of the floor, and the high-tension cables 7U, 7V, 7W are passed through a protection tube 20 over a predetermined distance from the motor/generator 3 in the engine compartment.

Abstract: The drain of a power transistor M1 is connected to the non-inverting input terminal of an operational amplifier A and the drain of a transistor M2 is connected to the inverting input terminal of the operational amplifier A to make substantially equal the drain voltages of the power transistor M1 and the transistor M2, of which the gates are connected together and of which the sources are connected together. The drain current of the transistor M2 is outputted via a detection terminal 13 as a current signal proportional to the drain current of the power transistor M1.

Abstract: A memory control unit adjusts and sets the address of an image data area in the memory space of a memory and the address of a window area adjacent to the memory area, using a memory controller. The memory control unit stores data, other than image data that is supplied, at a specified address location and, when a control signal is sent to the memory, reads out the image data, including data stored in the window area, from the memory. The data that is read out from the window area is inserted into a predetermined position during a blanking period.

Abstract: The present invention provides a semiconductor integrated device which can suppress high-frequency noise and which can thus stabilize the output voltage and power supply voltage of the reference voltage generating circuit. This semiconductor integrated device comprises a reference voltage generating circuit, a first bonding pad which is connected to the output of this reference voltage generating circuit, a lead which is connected to this first bonding pad via a first bonding wire, a second bonding pad which is connected to this lead via a second bonding wire, and a circuit which generates high-frequency noise and is connected to this second bonding pad.

Abstract: A timing signal generating circuit receives multiphase input signals and generates a signal having a phase intermediate therebetween, and weighting is applied to the multi-phase input signals by using a variable impedance circuit. The timing signal generating circuit (receiver circuit) can operate with a low supply voltage, is simple in configuration, and can generate timing signals with high accuracy.

Abstract: A timing recovery circuit includes a first oscillating circuit configured to produce a first timing signal, a second oscillating circuit configured to produce a second timing signal, a first decimation circuit coupled to a supply node of a first clock signal and to the first oscillating circuit to produce a second clock signal made by decimating pulses of the first clock signal in response to the first timing signal, and a second decimation circuit coupled to the first decimation circuit and to the second oscillating circuit to produce a third clock signal made by decimating pulses of the second clock signal in response to the second timing signal, wherein one of the first timing signal and the second timing signal has a fixed cycle, and another one has a cycle responsive to feedback control.

Abstract: A copper foil for chip-on-film use, a plasma display panel, or a high-frequency printed circuit board obtained by rolling copper foil to smooth the surface to give a surface area of not more than 1.30 times an ideal smooth surface, the smoothed copper foil having deposited on it fine roughening particles of Cu or alloy particles of Cu and Mo or alloy particles comprising Cu and at least one element selected among a group of Ni, Co, Fe, and Cr or a mixture of this alloy particles and oxide of at least one element selected among a group of V, Mo, and W.

Abstract: A polish method for planarization is disclosed. The method uses a combination of a traditional oxide CMP and HSP-CMP (High Selectivity and Planarization) with a fix abrasive pad to meet the requirements of the CMP process for a device feature dimension under 0.18 micron even to 0.09 micron. By using a first polish step with a conventional polish pad and an oxide polish slurry, the non-uniformity of the over-fill thickness of the STI dielectric layer can be firstly removed and a much more smooth and uniform topography favorable for the HSP-CMP process the fix abrasive polishing pad can be obtained. Then the HSP-CMP process with the fix abrasive polishing pad can be performed to provide a planarized surface with accurate dimension control.

Abstract: A filter circuit includes a plurality of integrator stages, each stage including a voltage-to-current converter to convert an input voltage into a current supplied to an output thereof and a capacitor coupled to the output of the voltage-to-current converter, a voltage charged in the capacitor being supplied to a next stage as an output of each stage, and a capacitor serving as a feed-forward coupling that couples the output of at least one stage of the plurality of integrator stages to a last output node.

Abstract: An in-cylinder pressure detection device which is capable of ensuring stable detection accuracy irrespective of tightening torque applied in mounting the in-cylinder pressure detection device and thermal expansion of component parts of the same. A housing 21 has a top wall 22a and a bottom wall 22b opposed to each other, and is screwed into the body of an internal combustion engine. An inner member 24 extends through the housing 21 such that one end thereof projects into a cylinder C, and has a flange part 24b accommodated in the housing 21. A first piezoelectric element 11c is accommodated in the housing 21 and sandwiched between the bottom wall 22b and the flange part 24b in a preloaded state, for outputting a first detection signal q1 according to the in-cylinder pressure transmitted via the inner member 24.

Abstract: An image sensor for capturing image, has: a plurality of pixels arranged in a matrix each including a photoelectric conversion element for generating current according to received light intensity and a reset transistor for resetting a node of the photoelectric conversion element to a reset potential; and a sample hold circuit for sample holding a pixel potential according to the potential of the node of the pixel. And the sample hold circuit outputs the differential potential, between a first pixel potential at an end of the integration period after a first reset operation of the pixel and a second pixel potential at an end of a reset noise read period after a second reset operation after the integration period, as a pixel signal. Also in the sample hold circuit, when the second pixel potential during the reset noise read period exceeds a predetermined threshold level, the second pixel potential is set to a predetermined reference potential.

Abstract: A semiconductor memory device includes a self-testing circuit and a self-redundancy circuit with simple structures. The self-testing circuit includes a comparison circuit which compares write data with read data with respect to normal memory blocks and redundant memory blocks, and a decision circuit which decides if the semiconductor memory device is good or defective based on the plurality of comparison result signals. A signal transfer and holding circuit is connected between the comparison circuit and the decision circuit to transfer the plurality of comparison result signals to the decision circuit and to supply the plurality of comparison result signals to the self-redundancy circuit as a test result.