Abstract: In a flight management system (FMS) of an aircraft, there is included a speed generator that outputs a speed command for the aircraft in accordance with a preselected mode. The FMS further includes an apparatus performing a method for adjusting the speed to achieve a desired arrival time. The apparatus comprises a unit for generating a speed adjustment coefficient (KSA), a unit for calculating wind forecast error, and a unit for adjusting the command speed outputted from the speed generator. The adjusting unit utilizes the KSA, actual wind speed at the current aircraft position, and wind forecast error at the aircraft position. The speed adjustment compensates for the error in the wind forecast, in order to achieve the desired arrival-time.

Abstract: A dialogue system uses a three wire bus connecting a central station with a plurality of substations with two of the wires carrying an AC supply voltage and a third one of the wires carrying data by means of a closed loop of the AC carrying wires and the third wire. The central station uses a series connection of a data transmitter and a data receiver with the third data wire and each substation includes a data receiver in series with the data wire and a data transmitter between the data wire and both AC wires.

Abstract: A process control system includes a processor which outputs command signals to a plurality of field devices via an interface unit. The interface unit comprises a primary output unit for outputting a first set of the command signals to the field devices in response to a first control signal. The first set of command signals are command signals for normal operation of the process control system. A secondary output unit outputs a second set of the command signals to the field devices in response to a second control signal. The second set of command signals are command signals for a failure mode of operation of the process control system. The second set of command signals are temporarily stored by the secondary output unit in order to respond quickly upon detection of an error.

Abstract: A method by which the each module of a token passing local area network complying with IEEE standard 802.4 determines if the communication cable from which it is receiving signals is faulty and switches to a second, or redundant cable. Each module transmits the same signals over both cables, but can receive signals from only one, its selected cable. In normal operations, all modules receive signals from the same cable. Each of the modules has the capability of detecting faults in its selected cable, and of switching cables so that its second cable becomes its selected cable. Each module also has the capability of initiating the process or re-establising the network whenever a module switches cables in response to detecting a fault. Each module in response to the process of initiating re-establishing the network, switching cables so that all modules are listening to, or receiving signals from the same cable.

Abstract: A process control system includes a primary processor connected to a primary memory via a bus. The primary processor transfers data to be stored to said primary memory. An apparatus of the present invention connected to the bus, collects predetermined data of the data being transferred simultaneously with the transfer of the data to the primary memory. The predetermined data collected by the apparatus is subsequently transferred to a backup processor controller to update the data base of the backup process controller. The apparatus comprises a storage element which stores the data collected. A logic unit controls the operation of the apparatus including the collection of the predetermined data. A control unit of the apparatus transfers the predetermined data stored in the storage element to the backup process controller.

Abstract: A process control system includes a process controller which has a first and second controller, one of the controllers being designated as a primary controller and the other controller being designated as a secondary controller. Each controller has a respective data base. The primary controller performs predefined control functions of the process control system which includes updating the data base associated with the primary controller as a result of performing the predefined control functions. A method for updating the data base associated with the secondary controller comprises the steps of performing the control functions. Results therefrom are utilized to update the data base associated with the primary controller. Simultaneously with updating the data base, predetermined information being stored in the primary data base is collected. At the completion of performing the control functions, the predetermined information which was collected is transferred to the secondary controller.

Abstract: A current source is controlled by the output signal from a digital to analog converter. The output signal from the digital to analog converter is applied to an amplifier unit. The output of the amplifier unit controls current through a pass transistor element, the pass transistor element current being the current applied to the load impedance. A feedback signal is generated by a differential amplifier in response to the current applied to the load impedance. The output signal from the difference amplifier is applied to an input terminal of the digital to analog converter with a polarity resulting in a change in the output signal of the amplifier unit which compensates for any change in the current through the load impedance. A voltage level changing element is included in the pass transistor control terminal to interrupt the current to the load impedance in the event of a degradation in the power supply.

Abstract: An A/D converter circuit generates a precise digital signal which accurately corresponds to an analog input signal. The A/D converter comprises a converter element, having a first and second, input terminal for receiving control signals, and having an output terminal, and further having at least one analog input terminal. The analog input signal is coupled to the analog input terminal, for converting the analog input signal to an uncorrected digital signal. The uncorrected digital signal includes inaccuracies of the parameter differentials of the converter element. A memory unit, stores information defining the actual parameter values of the converter element. A processor, controls the conversion of the analog input signal to the precise digital signal, wherein the actual parameter values are applied to the uncorrected digital signal thereby removing the inaccuracies of the converter element to obtain the precise digital signal.

Abstract: The lubrication insertions system of the present invention inserts lubricating oil into the critical areas of a bearing. The system comprises a delivery element for delivering lubricating oil to a predetermined point relative to the bearing. The bearing, which is rotating, causes the lubricating oil to be slung outward of the spin axis of the bearing. A cage element, having a lip that extends beyond the edge of the bearing, captures the lubricating oil and directs the lubricating oil into the bearing to the outer race of the bearing and to the rolling elements of the bearing, which track the oil to the inner race of the bearing.

Abstract: In order to insure the accuracy of information transmitted over a network, the initiation of the message must be unambiguously identified. In the present invention, the intermessage spacing consists of a series of identical logic signals that exceeds a minimum value distinguishing this interval from a message character. The message character has predefined length, with a start bit position logic signal and a stop bit position logic signal bounding the character that has the same number of predetermined logic signals for every message character. The character has at least one additional non-data bit position that has a first logic signal for the initial character of a message and the complementary logic signal for the remaining characters in the message.

Abstract: In order to prevent `jabber`, the uncontrolled transmission of messages on a communication channel, an antijabber timing unit is frequently used to determine whether a message on the communication channel exceeds the maximum permitted length of time. The present invention provides testing apparatus to determine when the antijabber timing unit is functioning accurately. In addition, protection is provided so that the testing apparatus does not compromise the function of the antijabber timing unit during subsequent message transmission. The antijabber timing unit is also used as part of the enable function for the transmission of messages over a channel to prevent the failure of a single component from resulting in inadvertent transmission of information.

Abstract: In a process control network, apparatus and method for periodic testing of a thermocouple element includes a switching mechanism that inserts a circuit with known parameters in series with the thermocouple. Voltages levels with and without the inserted circuit are compared and used to identify a failed or failing thermocouple.

Abstract: A central processor for a general-purpose digital data processing system. The processor has a pair of caches, an operand cache for operands and an instruction cache for instructions, as well as a plurality of execution units, where each execution unit executes a different set of instructions of the instruction repertoire of the central processor. An instruction fetch unit fetches instructions from the instruction cache and stores them in an instruction stack. The central pipeline unit which has five stages obtains instructions of a given program in program order from the instruction stack of the instruction fetch unit.

Abstract: A device for deciphering encoded information is disclosed which comprises logic elements which combine a key input to implement a predetermined set of boolean transformations thereby yielding a corresponding set of translation terms. The translation terms are subsequently combined with corresponding encoded information to yield deciphered information.

Abstract: An activity detector device detects the presence or absence of information transmission over a serial data link between a computer system and a peripheral device. If a presence of a data signal exists as determined by the activity detector, the data signal is transmitted through to the computer system. If an absence of the data signal exists as determined by the activity detector, the input transmission link is decoupled from the computer system by the activity detector and places an all ones signal on the input line to the computer system consistent with the I/O protocol.

Abstract: The present invention relates to a speech recognition system and the method therefor, which analyzes a sampled clipped speech signal for identifying a spoken utterance. An input signal representative of the spoken utterance is passed through a clipper to generate a clipped input signal. A sampler generates a plurality of discrete binary values, each discrete binary value corresponding to a sample value of the clipped input signal. A processor then analyzes the plurality of sample values thereby identifying the spoken utterance. Analysis includes determining linear prediction coefficients of the autocorrelation function of speech utterences.

Abstract: An optical character recognition system and method therefor is disclosed for reading a machine encoded character font, such as the E13B magnetic ink character (MICR) font. The digitized data of an optical scan band of the document to be read is read by an optical scanner and stored in memory. A two pass operation of the digitized data is then performed by the respective algorithms of the system to locate and recognize the characters read.

Abstract: A long term response enhancement for a digital phase-locked loop is implemented to provide a relatively minor change in the phase of the output signal over a relatively long period of time. The basic digital phase-locked loop determines the average number of pulses from a clock source which occur or are expected to occur between successive occurrences of the input signal to the digital phase-locked loop, and compares the number of pulses counted from the occurrence of the last output signal with the average number of pulses expected to occur between successive input signals, producing an output signal when the two numbers agree.

Abstract: This invention relates to an error detection circuit for detecting errors in a recovered clock signal from a self-clocking digital data signal. A first flip-flop is alternately set and reset by the recovered clock signal and by a clock source of supposedly equal frequency, respectively. The output of the first flip-flop is sensed by a second flip-flop at the end of a predetermined time period, as determined by the clock source, for determining that a transition in the recovered clock source occurred within the predetermined time period. If no transition occurred within the predetermined time period, the second flip-flop outputs an error signal.

Abstract: A memory unit having a multiplicity of storage locations for the temporary storage of series of groups of data signals. When the data groups are being stored in a memory location, index signals are developed that not only identify the location of the stored signal group, but when applied to the memory unit cause the data group to be withdrawn from the memory unit. The memory unit is comprised of a first addressable multiplicity of storage locations; a second addressable multiplicity of storage locations, the contents of the second multiplicity of storage locations adapted for addressing the first multiplicity of storage locations, a counter for addressing the second multiplicity of storage locations; and control logic for controlling the counter and entry and withdrawal of data signals in the first and second multiplicity of storage locations.