Abstract: A collision avoidance apparatus having a voltage source producing a predetermined voltage level. A switching network within the collision avoidance apparatus is capable of alternately applying the predetermined voltage level to the communication medium and of applying the voltage level of the communication medium to a logic network. The logic network indicates if the predetermined voltage level and the voltage level of the communication medium are approximately equal.

Abstract: An electrical connector permits the use of non-noble metals by providing mechanical advantage in obtaining high contact force with low insertion force. A pin is utilized as a cantilever beam to provide high contact force. A carrier, which is activated by insertion by a printed circuit board or the like, includes a lever forming part of the electrical connection. The lever is displaced causing deflection of the pin. The lever has contact points capable of piercing non-metallic oxides, thereby forming good electrical contacts.

Abstract: This invention relates to a real time clock recovery circuit. The clock recovery circuit requires three inputs, a bit serial data received input (BSD), a quarter bit delayed (QBT) and a three quarter bit delayed (TQBT) signal. The three inputs are derived from a single raw input that becomes the received input (BSD) signal. QBT and TQBT are delay line versions of the BSD signal. The three inputs (BSD, QBT and TQBT, and the complement of these signals) are ANDed together to detect low frequencies. The generated signal indicative of the low frequency, QBT and TQBT generate a recovered clock by state sequencing of an R-S latch. The type of bit serial data stream which may be inputted to the circuit of the present invention is double frequency encoded data streams, including Manchester or diphase encoded.

Abstract: A pipelined computer which executes high level language instructions is disclosed. The pipelined computer includes a memory for storing the high level language instructions therein. A plurality of microprogrammed digital computers are coupled in parallel to the memory, and are also intercoupled via an interlocking bus. The microprogrammed computers, in conjunction with the interlocking bus, form a pipeline for executing the high level language instructions. Each of the computers is a separately microprogrammable stage of the pipeline.

Abstract: A basic Schmitt trigger circuit is modified with additional circuit components for a two-input bistable circuit (latch). The latching Schmitt trigger circuit exhibits enhanced operating characteristics, such as fast and reliable switching between stable states. Also the circuit is compatible with design parameters and operating tolerances of integrated circuits. The latching Schmitt trigger circuit enables implementation of a fast reliable arbitration circuit in an integrated circuit version by minimizing the necessary time delay between the end of a resource request signal period and the start of an interrogate signal period.

Abstract: A switching regulated power supply operates over a broad range of input voltage and frequency, and outputs direct current power for computer equipment and the like. The power supply can be paralleled with identical power supplies, thereby satisfying any predetermined power requirement. A charge pump bulk voltage balancing circuit balances voltage on capacitors in an input rectifier and filter circuit. A flux sensing circuit senses magnetizing current in the secondary of a power transformer and the integrated signal is incorporated into pulse duration modulation to achieve dynamic flux balancing of the power transformer through a feedback loop. Output voltage of the power supply connects to a control supply of the power supply, providing power feedback to the control supply to maintain the operating parameters of the power supply as long as the output voltage does not fall below a predetermined level.

Abstract: An electrically configurable decoder including selectively configurable combinations of a plurality of basic decode circuits. The electrically configurable decoder includes a plurality of mode selection inputs, a plurality of address inputs, a plurality of logic level definition inputs, and a plurality of disable inputs. Various combinations of decoding functions are provided by the electrically configurable decoder in response to the mode selection inputs. A plurality of selection circuits selectively decodes various ones of the address inputs and mode selection inputs to produce signals which are applied to decode inputs and enable inputs of the basic decoder circuits. A logical "one" applied to a first one of the logic level definition inputs causes "high" and "low" voltage levels produced at the outputs of a first one of the basic decoder circuits to represent logical "ones" and "zeroes," respectively.