Abstract: An optical assembly comprising an optical cube. A first optical transmitter chip and a first optical receiver chip are mounted on one surface of the optical cube. A first continuous printed circuit board is soldered to electrical surfaces of the first optical transmitter chip and the first optical receiver chip opposite the optical cube. A second optical transmitter chip and a second optical receiver chip are mounted on an opposite surface of the optical cube. A second continuous printed circuit board is soldered to electrical surfaces of the second optical transmitter chip and the second optical receiver chip opposite the optical cube. The first optical transmitter chip is optically aligned with the second optical receiver chip through the optical cube. The second optical transmitter chip is optically aligned with the first optical receiver chip through the optical cube.

Abstract: A storage control and switch unit for transferring data between a host computer and first, second, third and fourth storage media. A first storage controller has an operative serial ATA connection with each of the first and second storage media and an inoperative serial ATA connection to each of the third and fourth storage media. A second storage controller has an operative serial ATA connection with each of the third and fourth storage media and an inoperative serial ATA connection to each of the first and second storage media. First, second, third and fourth switches are logically interposed between the first, second, third and fourth storage media, respectively, and the first and second storage controllers to select which serial ATA connection to each storage media is operative and which is inoperative.

Abstract: A method and apparatus is disclosed wherein a first structure in a memory of a controller for sharing information is defined and a hidden structure containing control information for sharing information with the first defined structure is created. Data is synchronized between controllers so that firmware development is simplified. The user defines a structure and through the use of macro calls makes that structure shared. Lock rules are provided, to perform synchronization and buffer management. Failover and failback are also addressed to provide a comprehensive solution for sharing work and information between controllers. Accordingly, the emulated shared memory mechanism allows a programmer to define a structure that contains information for sharing without having to reinvent firmware when new features are added to a storage controller.

Abstract: A circuit for measuring voltage of a battery or group of batteries whose terminals are not directly accessible. The battery or group of batteries can have three leads. First and second leads are connected to the voltage output of the battery and the third lead is connected to the return of the battery. The three leads may terminate in a three prong plug which may plug into a printed circuit board to form a module. The module can be connected into a rack via an edge connector. A battery voltage measurement circuit can be located on another printed circuit board which is also plugged into the rack. This other printed circuit board may be interconnected to the battery module by wire traces within the rack. Thus, there are one or more first connectors between the first lead of the battery or group of batteries and the charger. There are one or more second connectors between the second lead of the battery or group of batteries and an input of the voltage measurement circuit.

Abstract: Two surfaces are adhesively bonded together by providing on one of the surfaces a central, single point adhesive contact deposit and providing on one of the surfaces, adhesive extending from a central point deposit in a spoke-like array diagonally across substantially the entire surface. Also provided is the article obtained by the above method as well as the assembly used for bonding the two surfaces together. The surfaces are brought together, one on top of the other, with the adhesive located between the surfaces to cause the adhesive to spread out and cover the surfaces to thereby bond them together.

Abstract: Optical cubes and optical cube assemblies for directing optical beams are provided. The optical cubes are optically transparent modules that can be adapted to reflect, transmit, and/or partially reflect and transmit optical beams. The optical cubes may include bi-direction or multi-direction beam directing elements for directing optical beams. The optical cube assemblies may include flexible chip assemblies attached to optical cubes. The chip assemblies may include vertical cavity surface-emitting lasers for emitting optical beams or receivers for receiving optical beams mounted on a flexible and electrical interconnect mounting assembly.

Abstract: A method for fabricating a laminate circuit structure is provided. The method comprises: providing at least two modularized circuitized voltage plane subassemblies wherein each of the subassemblies comprise at least two signal planes having an external and internal surface disposed about an internal voltage plane; providing a dielectric material between the signal and voltage planes; and providing dielectric on each external surface of each signal plane; and providing a non-cured or partially cured curable dielectric composition between the subassemblies wherein the dielectric composition comprises, dielectric material that is of the same material as the dielectric material used in said subassemblies, aligning the subassemblies, and then laminating to cause bonding of the subassemblies.

Abstract: A heat sink for a transceiver optoelectronic module including dual direct heat paths and a structure which encloses a number of chips having a central web which electrically isolates transmitter and receiver chips from each other. A retainer for an optical coupler having a port into which epoxy is poured. An overmolded base for an optoelectronic module having epoxy flow controller members built thereon. Assembly methods for an optoelectronic module including gap setting and variation of a TAB bonding process.

Abstract: Embedded flush circuitry features are provided by providing a carrier foil having an electrically conductive layer therein and coating the electrically conductive layer with a dielectric material. Circuitry features are formed in the dielectric material and conductive metal is plated to fill the circuitry features.

Abstract: A termination circuit for a differential transmission line. The termination circuit comprises a plurality of resistive sub circuits. Each of the resistive sub circuits comprises a PFET and an NFET in parallel. A first resistor is connected at one end to a drain of the NFET and a source of the PFET, and connected at an opposite end to one line of the differential transmission line. A second resistor is connected at one end to a source of the NFET and a drain of the PFET, and connected an opposite end to another line of the differential transmission line. Optionally, there is another resistor connected between the differential transmission line, whereby the termination resistance is based on this other resistance in parallel with one or more of the resistive sub circuits which are enabled. Means are provided to selectively enable one or more of the resistive sub circuits to yield a desired resistance to terminate the differential transmission line.

Abstract: A method and apparatus for quiescing a system storage device wherein cache lines associated with a system storage device to be quiesced are flushed using a stripe lock mechanism to find and flush cache data associated with the given system storage device. Dirty cache lines are associated with a stripe lock, and that stripe lock will be in the active state or the clearing state. The stripe locks are also maintained on a linked list per a system storage device. In the normal life cycle of a stripe lock, if the partner controller requests a lock over part of the extent of an active lock, the active lock will go to the clearing state. Data in the extent of the now clearing lock is flushed. For performing a quiesce, stripe locks for the given system storage device are set to clearing on a plurality of controllers, thus causing the flush. The quiesce mechanism then only needs to wait until stripe locks have been cleared for the system storage device.

Abstract: A method of pretreating a copper surface for protecting the surface from oxidation, by immersing the surface in a solution containing organic solderabilty preservatives, such as BenzoTriAzole, with the addition of a zinc salt. The method is particularly useful in the manufacturing of electronic Printed Circuit Boards for protecting the copper surfaces during the solder processes when the PCB undergoes high temperature. The addition of the zinc salts also gives the additional advantage of increasing the solderabilty properties of the copper surface (i.e. wettability and adhesion).

Abstract: A mirror table that facilitates selective data coherency between local memory segments and remote memory segments includes a content addressable memory (CAM) and a random access memory (RAM). The CAM stores the addresses of local memory segments that are selected to be mirrored, and provides a segment index when presented with a segment address stored therein. The RAM stores one or more remote segment addresses for the mirrored segments along with additional data, and provides the remote segment addresses along with the additional data when presented with the segment index. A mirror link assembles and transmits an update packet comprising the remote segment addresses, a segment offset, the corresponding data, and the additional data to a remote destination. Each indicated remote address is updated with the corresponding data, thus maintaining data coherency between the selected local and remote memory segments.

Abstract: A chip package comprises a substrate with a composite capacitor/stiffener on the substrate. In one embodiment of the present invention, the substrate comprises a plurality of dielectric layers and a plurality of metallic layers interlaced with the dielectric layers. One of the metallic layers is on a surface of the substrate. Another dielectric layer is adhered onto the one metallic layer. A metallic plate is adhered onto the other dielectric layer, opposite the one metallic layer. The metallic plate is electrically connected to power or ground. The one metallic layer is electrically connected to ground or power, respectively, such that the metallic plate, the other dielectric layer and the one metallic layer form a capacitor. The one metallic layer is joined to a respective one of the plurality of dielectric layers in a same manner as another of the plurality of metallic layers is joined to another, respective one of the plurality of dielectric layers.

Abstract: A web browser loads and displays a web page and reads the html of the web page to identify an entry for a link which is marked for pre-loading. Then, the web browser automatically pre-loads into memory another html and associated graphics files corresponding to this link. This automatic pre-loading occurs without the link being selected by a user of the web browser. If the user subsequently selects the link, then the corresponding html and associated graphics files will be available from local memory so there is little delay in fetching the html and associated graphics files.

Abstract: A method and an article made by a method for embedding optical fibers into an organic laminate structure. The optical fiber cabling, along with its cladding, is placed upon a first laminate layer that includes a composite made of silica fillers and a frictionless material such as polytetrafluoroethylene (PTFE). Then a second layer of PTFE material with silica fillers and copper sheeting is placed on top of the PTFE with silica fillers composite. The PTFE material with silica fillers flows about the optical fibers at a temperature approximately fifty degrees above the PTFE with silica fillers material's melting point. This procedure completely encases the optical fibers within an opaque sheath.

Abstract: A method and system for flexibly and efficiently assigning channel path identifiers (CHPIDs) used by operating system software in computer systems to identify the communication path to I/O devices via channels. To avoid wasted CHPIDs, which may be limited in number, CHPIDs are assigned only to channels which are installed on and configured to the computer system. The CHPIDs may be re-assigned concurrently with ongoing system operations via a user interface and/or an imported, pre-defined CHPID mapping.

Abstract: A flexible, compliant layer of a single low modulus material for connecting a chip die directly to a circuit card without encapsulation. The flexible compliant layer provides stress relief caused by CTE thermal mismatch in chip die and circuit card. An array of copper plated vias are formed in said compliant layer with each via terminating on opposing surfaces of the layer in copper pads. Rather than copper, other metals, such as gold or nickel, may also be used. An array of holes may be positioned between said array of vias to provide additional resiliency. The plated vias may be angled with respect to said opposing surfaces to allow additional vertical and horizontal stress relief. Connection of the pads on one surface to high melt C-4 solder balls or columns on a chip die results in solder filled vias. Low melt solder connection of the pads on the other surface to a circuit card allows non-destructive rework of the cards.

Abstract: A storage controller for redundant arrays of independent disks (RAID) comprises a daughter card containing a standardized controller core, which is mated to one of a number of customizable controller interface cards. The controller core card includes high performance elements such as a processor, cache memory, CRC circuitry, a host port, and a storage port. All operational communication with non-core components occurs via the host port and the storage port through the controller interface card. The controller core card monitors and configures communications between the host and the storage array. Each controller interface card is populated with components and connectors particular to the respective application or RAID system. The size and layout of the controller interface card may also be customized to the particular application. Sharing the same controller core card among various RAID controllers lowers the cost and time-to-market for customized RAID systems.

Abstract: Adaptive write policy for handling host write commands to write-back system drives in a dual active controller environment. Method for adaptive write policy in data storage system, where data storage system includes host system connected to primary controller and alternate controller. Controllers are coupled to system drive that includes one or more disk storage devices. Primary is connected to first memory and alternate is connected to second memory. Primary and alternate manage data storage system in dual-active configuration. Primary controller receives host write command from host system and write data request includes host write data. When system drive is configured with write-back policy, primary determines whether host write command encompasses an entire RAID stripe, and if so, primary processes host write command in accordance with write-through policy. Otherwise, primary processes command in accordance with write-back policy.