Abstract: A page mode/nibble mode dynamic random access memory (DRAM) comprising row and column decoders, the column decoder further comprising a column address buffer and a column address buffer counter. The page mode/nibble mode DRAM also comprises a buffer controller means adapted to receive a write enable signal and to determine whether the DRAM should be placed in a page mode or a nibble mode to facilitate the particular memory access requested by a memory controller. An asserted write enable signal, may indicate, for example, a write operation, thereby calling for the page mode/nibble mode DRAM to move into a page mode to effectuate the write operation. The page mode/nibble mode DRAM also utilizes the write enable signal in the conventional manner, to indicate the initiation of a particular type of memory access, namely a write operation or a read operation.

Abstract: A fault tolerant computer system is described in which a direct memory access controller examines the check bit data on every data element that is accessed by the system. The address of any data element that is found to have an error in the check bit data is stored by the direct memory access controller, the check bit data is used by the direct memroy access controller to correct the error, and the corrected data element is rewritten to the original storage address. By the use of this arrangement, the central processing unit or units of the computer system are free to perform other tasks, thus improving system throughput, and preventing the accumulation of data element errors in the memory.

Abstract: A read buffering system employs FIFOs to hold sequential read data for a number of data streams being fetched by a computer. When the system sees a read command from the CPU, it stores an incremented value of the address of the read command in a history buffer and marks the entry as valid. The system detects a stream when a subsequent read command specifies an address that matches the address value stored in the history buffer. Upon detecting a stream, the system fetches data from DRAMs at addresses that follow the address of the subsequent read command, and stores it in a FIFO. However, to reduce unnecessary prefetching, the system looks for a read X, write X, read X+1 (where X and X+1 designate addresses) succession of commands so as to prevent them from creating a stream. This succession occurs often and qualifies as a stream, but is seldom followed by other reads that maintain the stream.

Abstract: A thermosiphon provides cooling for a high powered die. The thermosiphon includes a fuse for accommodating temperature fault conditions. The thermosiphon utilizes a water and alcohol mixture for improved boiling characteristics. Contaminants at the joint betweeen the thermosiphon and the package housing are reduced by the use of a shrink ring seal. Thermal interfaces between the die and the thermosiphon are eliminated by directly coupling the die to the thermosiphon.

Abstract: A backplane wiring scheme is provided for use in a hub of a packet data communications system. Line cards are connected to the backplane wiring arrangement in the hub, where each line card is a coupling to a network segment, a station or a to a bridge to other stations or segments. The connection is usually in either a ring or a bus topology, and increased flexibility, reduced power consumption, and easier implementation are provided by a unique wiring scheme. Each line card has a number of receive ports (e.g., N-1) and has two transmit ports, the transmit ports including a transmit-left port and a transmit-tight port. The receive ports and transmit ports are arranged in a regular linear pattern on an edge of each of said line cards.

Abstract: A work flow description database represents long running work flows as a set of work units, called steps, with information flows therebetween. The description database defines each step's input and output signals, input condition criteria for creating an instance of the step, an application program associated with the step, and criteria for selecting a resource to execute the step. A work flow controller controls the process of executing instances of each defined type of work flow. Execution of a long running work flow begins when a corresponding set of externally generated input event signals are received by the work flow controller. During execution of a work flow, each step of the work flow is instantiated only when a sufficient set of input signals is received to execute that step. At that point an instance of the required type of step is created and then executed by a selected resource.

Abstract: A storage system having a plurality of disks arranged into a RAID array and a logging process and apparatus that identifies corrupt or invalid data and which prevents the corrupt or invalid data from being sent to a user application or used in any computations internal to the functioning of the array. In the preferred embodiment, a plurality of status bits, each having a first and second state are associated with each data block and parity block. If the status bit indicates that the block may contain corrupt or invalid information then that block is not used in regenerating data for an unavailable block or sent to a user application upon a read request.

Abstract: A pipelined processor includes an instruction box including a register mapper, to map register operand fields of a set of instructions and an instruction scheduler, fed by said set of instructions, to reorder the issuance of said set of instructions from said instruction processor. The mapped register operand fields are associated with the corresponding instructions of said reordered set of instructions prior to issuance of the instructions. The processor further includes a branch prediction table which maps a stored pattern of past histories associated with a branch instruction to a more likely prediction direction of the branch instruction. The processor further includes a memory reference tagging store associated with the instruction scheduler so that the scheduler can reorder memory reference instructions without knowing the actual memory location addressed by the memory reference instruction.

Abstract: Multi-processor systems are often implemented using a common system bus as the communication mechanism between CPU, memory, and I/O adapters. It is also common to include features on each CPU module, such as cache memory, that enhance the performance of the execution of instructions in the CPU. Many architectures require that the hardware employ a mechanism by which the data in the individual CPU cache memories is kept consistent with data in main memory and with data in other cache memories. One such method involves each CPU monitoring transactions on the system bus, and taking appropriate action when a transaction appears on the bus which would render data in the CPU's cache incoherent. If the CPU uses queues to hold records of incoming transaction information until it can service them, the bus interface must guarantee that the queued items are processed by the cache in the correct order. If this is not done, certain types of shared data protocols fail to operate correctly.

Abstract: Method and apparatus for automatically closing gaps prior to painting a cel in a vector-based computer-aided drawing system. A drawing is processed, as it is entered by a user, to generate a stored planar map containing geometric and topological characteristics of the drawing. The planar map is searched to identify gaps and updated to store synthesized gap-closing vectors for those gaps smaller than a selectable size. The gaps are closed before the painting of the cel, or coloring of the drawing, so as to prevent unintended spill-over of the color into adjacent regions.

Abstract: An output device is enabled to obtain character descriptions for use in raster scanning characters which belong to a common character font. Character descriptions are stored in an external device which is linked to the output device by a communication channel. Character codes are received at the output device which identify characters to be outputted. A raster image of the characters to be outputted is set up. In the course of setting up the raster image, information corresponding to the character codes is sent from the output device to the external device via the communication channel. In response to the character codes sent from the printer to the external device, corresponding character descriptions are sent from the external device to the output device via the communication channel.

Abstract: A method of forming cobalt silicide on source/drain regions and polysilicon gate areas of an MOS integrated circuit uses an improved technique to prevent unwanted oxidation of cobalt or growth of silicide on other areas of device. A thin titanium nitride (or titanium tungsten) film is deposited on top of a cobalt film following the steps of patterning the polysilicon gate, source/drain implant and sidewall oxide spacer deposition and etch. The titanium nitride film allows formation of defect-free cobalt silicide during an elevated-temperature anneal. Without the titanium nitride film, the cobalt is likely to oxidize and/or form cobalt silicide in unwanted regions of the device, which can cause device failure.

Abstract: A content addressable memory has a pair of single-bit memory cells together storing two bits of information representing either an invalid state, a logic zero state, a logic one state, or a don't care state. Each of the memory cells has a pair of transistors. One of the transistors connects a common node to a respective one of a pair of address lines, and another of the transistors connects the common node to a potential of a predefined logic level. Each of the transistors has a gate receiving a logic level of the bit of information stored in a respective memory cell so that one of the transistors is conductive in response to the logic level of the bit of the information when the other of the transistors is not conductive in response to the logic level of the bit of information. Each of the memory cells also includes a transistor connected to the match line and having a gate connected to the common node.

Abstract: A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. Byte manipulation instructions, included to permit use of previously-established data structures, include the facility for doing in-register byte extract, insert and masking, along with non-aligned load and store instructions. The provision of load/locked and store/conditional instructions permits the implementation of atomic byte writes. By providing a conditional move instruction, many short branches can be eliminated altogether. A conditional move instruction tests a register and moves a second register to a third if the condition is met; this function can be substituted for short branches and thus maintain the sequentiality of the instruction stream.

Abstract: A memory system is provided which can adapt to being coupled to a bus capable of running at different clock speeds. The memory system is responsive to signals provided by a bus speed sensor for modifying the timing of row address strobe (RAS), column address strobe (CAS) and write enable (WE) signals. By modifying the timing of the RAS, CAS, and WE signals, the memory can be operated in systems capable of operating at a variety of bus speeds without suffering latency problems normally associated with changes in bus speed.

Abstract: A method and apparatus for molding a video display screen bezel to a video display device, such as a CRT, is disclosed. The bezel is molded in such a way as to eliminate the need for fasteners between the bezel and the CRT and between the bezel and a housing or some other structural support. The molded bezel also prevents any undesirable shifting of the CRT with respect to the bezel due to accidental dynamic loads. The molding material conforms to the surface of the CRT compensating for any dimensional variations in the CRT while minimizing the size of the bezel. Molded within the bezel is a compensating means which absorbs stresses generated by the molding material both during and following the molding process which might otherwise be exerted on the CRT.

Abstract: A pipelined processor includes an instruction box including a register mapper, to map register operand fields of a set of instructions and an instruction scheduler, fed by said set of instructions, to reorder the issuance of said set of instructions from said instruction processor. The mapped register operand fields are associated with the corresponding instructions of said reordered set of instructions prior to issuance of the instructions. The processor further includes a branch prediction table which maps a stored pattern of past histories associated with a branch instruction to a more likely prediction direction of the branch instruction. The processor further includes a memory reference tagging store associated with the instruction scheduler so that the scheduler can reorder memory reference instructions without knowing the actual memory location addressed by the memory reference instruction.

Abstract: In accordance with principles of the invention, there is provided a new process for semiconductor device fabrication. The disclosed process includes forming field isolation regions on a surface of a silicon wafer, and forming gate oxide regions selectively between the field isolation regions. A gate interconnect material is deposited over the field isolation regions and gate oxide regions. A planar surface is formed on the top of the gate interconnect material. This planarization step may be accomplished by chemical mechanical polishing or some other convenient method such as a resist etch back. After planarization of the gate interconnect material, a uniform thickness photoresist is deposited on the planar surface. A gate interconnect etch pattern is formed on the planar surface using photolithography and the gate interconnect material is etched to match a gate interconnect pattern and the photoresist is removed. Sidewall spacers are provided.

Abstract: In an interactive video-on-demand system, real-time programs are encoded as a transport stream including a plurality of transport stream packets. Some of the transport stream packets include timing signals indicating the real time of the program. The transport stream packets are formatted into transport cells for transport over an asynchronous transfer mode network from a source to a destination. The cells are transported at a transport rate which is determined by a network clock. The transport rate is chosen to deliver the transport stream faster than the real time of the program. While transporting the transport stream, it is determined if the transport stream is being transported ahead of the real time of the program. In this case, idle cells are injected into the transport stream to have the program arrive at the destination in the real time of the program.

Abstract: A semiconductor chip having a number of bonding pads on one face is mounted on a set of matching, mirror-image bonding pads on a packaging substrate, in a flip chip configuration. An alignment template is formed on and permanently secured to the substrate, and takes the form of a frame surrounding the substrate bonding pads. The height of the template is sufficient to receive the edges of the chip and hold the chip in place while the assembly is being transported to the soldering operation. No alignment operation is required, since the chip is merely placed in the receptacle formed by the template. The template is of course aligned with the substrate bonding pads when the template is created. The template can be formed on the substrate using photolithographic techniques, and, preferably, the template itself is formed of a photo-definable material.