Abstract: A fault tolerant computer according to the invention includes a processing unit including a first processor coupled to a first system bus to provide data to a cache and a memory, and a second processor coupled to the first system bus and a second, abbreviated system bus to receive read data from said first system bus. Coupled to said processing unit is an Input/Output device for interfacing to external devices. The processing unit includes a phase detector apparatus for aligning a clock of the processor unit to that of the Input/Output unit to facilitate data transfer. The phase detector apparatus includes a first means for providing a first clocking signal related to the clocking signal of the Input/Output unit, and a second means for providing a second clocking signal related to the clocking signal of the processor unit. The phase detector apparatus further includes means for providing an error signal responsive to an offset between edges of the first and second clocking signals.

Abstract: A method and apparatus in a computer system for handling cache memory victim data for updating main memory. The invention operates in a computer system having one or more processor modules coupled to main memory by a system bus operating in accordance with a SNOOPING bus protocol. Upon a processor executing a READ of one of the cache memory addresses, cache memory data corresponding to the cache memory address being READ is transmitted into the data interface from the cache memory data storage. The cache memory data is received accumulatively by the data interface during the execution of the READ of the cache memory address information. A determination is made as to whether the cache memory data corresponding to the cache memory address being READ is a cache memory victim. If the determination establishes that it is a cache memory victim, the processor issues a command for transmitting cache memory victim data to main memory over the system bus.

Abstract: A silicon capacitive microsensor which is sensitive to acceleration forces includes a silicon capacitive sensing element 10 comprising three silicon layers 12,16,26 having glass dielectric layers 14,24 between each pair of silicon layers with the middle silicon layer 16 consisting of a proof mass 18 suspended between the two glass dielectric layers 14,24 by a silicon hinge 20 which is connected to a slightly thicker silicon support layer 17 around the periphery (FIG. 3 ) between the glass layers 14,24 (FIG. 1 ). Three metallic bond pads 40,42,44 on the surface 45 of the silicon layers 26,16,12, respectively, are soldered to circuit trace pads 108 on a circuit board 100 which has a glass upper layer 104 and a silicon support layer 102. The thermal expansion coefficient between the glass layer 104 and the sensing element 10 are substantially the same, thereby minimizing thermally induced stresses on the sensing element 10 and minimizing inaccuracies associated therewith.

Abstract: An apparatus for dithering an input image to produce an output array for representation on an output device is described. The apparatus includes an input device to store input image pixels having a first plurality of chrominance or luminance levels; a dithering system including a dither template including an M by N matrix of integer threshold values, the uniform distribution of threshold values throughout the dither template possessing homogeneous attributes. The apparatus further includes a normalizer unit for normalizing the threshold values of the dither template for storage in a dither matrix according to the first plurality of chrominance or luminance levels of the input image pixels and a second plurality of chrominance or luminance levels of the output array and a summation unit to add the input image pixel chrominance or luminance values to the normalized threshold values of the dither matrix.

Abstract: A method and system for compiling a source program using smart recompilation. The invention allows fragments to contain "invocation specific" information, which is generated during a code generation phase of compilation. A hint generator attempts to preserve values of the invocation specific information between successive invocations of the compiler.

Abstract: A communications controller coupled to a synchronous network generates local clock reference signals from network clock signals. The network clock signals are used to transport data over the network at a constant rate. The controller receiving a bit stream while generating the local clock reference signals. The bit stream including program clock reference signals, the program clock reference signals being independent of the network clock signals. The program clock reference signals are extracted from the bit stream and compared, after normalization, with the local clock reference signals. If the program clock reference signals are, time-wise, in advance of the local clock reference signals, transport of the bit stream is suspended, otherwise the bit steam is transported over the network. While transport of the bit stream is suspended, data from an alternative bit stream can be transported.

Abstract: An I/O bus interface cell includes a driver circuit having an input terminal fed by a logic signal and an output terminal to produce in response thereto a drive signal having selectable rise and fall time characteristics in accordance with a reference voltage provided to the driver. The I/O cell also includes a receiver circuit having an input terminal coupled to said output terminal of said driver with the receiver disposed to latch an unresolved, unamplified received signal prior to resolving the state of the signal. The I/O cell further includes a termination circuit having a terminal connected to the output of said driver, and having a selectable impedance characteristic at said terminal, with said selectable impedance being in accordance with a reference voltage provided to an input of said termination circuit. Preferably, the I/O cell the driver, receiver and termination circuits are fabricated on a common semiconductor substrate.

Abstract: A flexible software testing tool provides fast and efficient diagnosis of defective computer system devices. The software testing tool includes an action string command qualifier that enables dynamic exercising of target computer devices by specifying certain operations involving those devices. Additional command qualifiers are provided to define the operating conditions of the device interaction paths. The operations specified by the qualifiers typically require interactions between a plurality of devices, thereby creating combinations of device interaction paths within the system to detect intermittent device failures.

Abstract: A high-power-factor power supply has a full-wave rectifier for rectifying an AC line voltage, a power regulator including switch means responsive to a control signal for controlling the application of the rectifier output to a load; and a control circuit for producing a switching control signal. The control signal includes a pair of AC line detectors: a first connected in a closed-loop automatic gain control arrangement, and the other connected in an open-loop arrangement. The control circuit initially produces a CURRENT DEMAND REFERENCE signal that is directly related to the difference between the power supply DC output voltage and a self-generated constant reference, and to the waveform shape of the AC line voltage, and is inversely related to magnitude changes of the AC line voltage. The control signal then produces the switching control signal in response to both the CURRENT DEMAND REFERENCE signal and the current flowing in the power supply.

Abstract: A font server communicates with workstations and printers, i.e., clients, on a network and provides them with font-specific information that allow them to select a licensed font and to specify how to customize the font. The font server responds to a client's printing or display requests regarding a specific font or printing or display features, such as letter height, orientation, writing mode. The font server may customize a font by remapping glyphs, rotating or scaling characters and symbols, or adding special kerning pairs or ligatures. The font server then performs all the necessary rendering calculations and manipulations using the font, and produces the bit maps or outlines required for displaying or printing the desired characters and symbols. The font server translates fonts into a format that is compatible with the client's text processing application and operating system. To minimize traffic on the network, the font server and client use name-identifiers to communicate.

Abstract: A computer communications system has a controller for controlling a master with a circuit timer, the circuit timer is capable of aggregating data produced during a circuit timer interval into a single master message, and the data is produced by a plurality of users, where each user is capable of establishing a plurality of sessions. There is a communication pathway, responsive to expiration of the circuit timer interval, for sending the aggregated data to a slave. Also there is a acknowledgement circuit for the slave to send an acknowledge message to the master upon expiration of a delay ACK time interval, the delay ACK time interval is greater than the circuit timer interval, and the circuit timer is capable of initiating sending of a plurality of master messages during one delay ACK time interval.

Abstract: A MOSFET device is constructed with an integrated Schottky diode clamp connected between the source or drain terminal and the bulk terminal. In an illustrative implementation, one or more MOSFETs are formed in an n-well located in a p-type silicon substrate. Each drain is formed by a p+ region underlying a portion of a metal-silicide layer. In one embodiment, the p+ region underlies an edge of the metal-silicide; in another embodiment, the p+ region underlies opposing edges of the metal-silicide, such that a portion of the metal-silicide contacts the n-well. Each source is formed by a p+ region underlying a layer of metal-silicide. Each gate includes a layer of p+ or n+ polycrystalline silicon clad with a layer of metal-silicide, the gates being separated from the n-well by a layer of oxide. In comparison to p-n junction diodes, the integrated Schottky diodes more effectively limit excess voltages applied to MOSFETs.

Abstract: A method and apparatus for generating glyphs for text elements input to a computer having a memory with at least one look-up table storing glyphs corresponding to such text elements. Each text element is made up of at least one code point, and often of several code points. The system searches the table for a glyph representing an input text element, and if it is not found methodically generates subsets of the text element and searches the table for glyphs representing each of the subsets. Default characters are generated for code points not represented in the table. The system uses a classification for each code point, such as the Unicode classifications, and handles unknown code points in a manner dependent upon their classification. Where a text element includes two characters with an intermediate joining character, and the text element as a whole is not represented in the table, the two characters are output for rendering separately.

Abstract: A transaction description database represents long running computations as a flow or set of computational steps with data arcs therebetween. The description database defines each step's input and output signals, input condition criteria for creating an instance of the step, an application program associated with the step, and criteria for selecting a resource to execute the step. A flow controller controls the process of executing instances of each defined type of long running transaction. Execution of a long running transaction begins when a corresponding set of externally generated input event signals are received by the flow controller. During execution of a long running transaction, each step of the transaction is instantiated only when a sufficient set of input signals is received to execute that step. At that point an instance of the required type of step is created and then executed by a selected resource.

Abstract: A reliable diagnostic system for running power-up diagnostics, displaying power-up diagnostic results, and retaining a power system status history. First, a method of testing a processor module in a computer system is provided. A processor including a serial port reads processor module diagnostic test instructions from a PROM in a serial line controller through the serial port by way of a serial bus in response to power-up reset instructions. Next, a reliable connection of a serial control bus to the modules is provided. Accordingly, backplane connectors are provided including wide signal conducting elements having multiple solder connection points to the modules and backplane. The serial control bus is electrically connected to each module through the multiple connection points of these signal conducting elements. Also, an apparatus and method for indicating module failures in a computer system is provided.

Abstract: Data storage systems using a RAID-4 or RAID-5 organization divide an application I/O request into a number of individual I/O requests, each of which is contained within the boundaries of a single strip. The data blocks of each chunk on a strip responsive to an I/O request can form a complex geometric pattern requiring complicated operations to perform the I/O request. To simplify the necessary operations, each individual I/O request to a strip is divided into at most three requests targeted to data blocks forming a rectangle and each of these rectangles are processed as a unit. If a data block within a rectangle is unavailable, then the request to that rectangle is further subdivided into at most two requests targeted to data blocks forming smaller, non-overlapping rectangles which collectively are the original rectangle.

Abstract: A pipelined processor includes an instruction unit including a register mapper, to map register operand fields of a set of instructions and an instruction scheduler, fed by the set of instructions, to reorder the issuance of the set of instructions from the processor. The mapped register operand fields are associated with the corresponding instructions of the reordered set of instructions prior to issuance of the instructions. The processor further includes a branch prediction table which maps a stored pattern of past histories associated with a branch instruction to a more likely prediction direction of the branch instruction. The processor further includes a memory reference tagging store associated with the instruction scheduler so that the scheduler can reorder memory reference instructions without knowing the actual memory location addressed by the memory reference instruction.

Abstract: Read-write buffer apparatus is provided for reducing the time necessary to resolve read conflicts during normal and block mode read requests. Additionally, the read-write buffer apparatus provides a means for gathering non-sequential write requests in an internal write buffer, thus reducing the frequency of a buffer full condition. The enhanced read-write buffer apparatus minimizes CPU wait states, while increasing the CPU processing rate and improves overall data processing system throughput.

Abstract: A method for arbitrating conflicting requests for a memory transfer in a multiport memory system including first and second memory ports. The method includes the following steps. First, monitoring the volume of memory transfer requests from the first memory port. Second, partially disabling the second memory port if the memory request volume is greater than a first predetermined volume. And third, reenabling the second memory port when the memory request volume becomes less than a second predetermined volume. Apparatus implementing this method which includes an activity detector, coupled to the first memory port, for generating a bistate signal having a first state when the volume of memory requests by the first memory port exceeds a first predetermined volume and a second state otherwise. Circuits are provided for selectively partially disabling memory requests from the second memory port in response to the bistate signal being in the second state.

Abstract: This invention relates to an image processing system which relies upon quantization and dithering techniques to enable an output device, which has a given number of output levels, to accurately reproduce a image which is generated by an input device, which has a greater or equal number of input levels. Generally, neither the number of input nor output levels need to be a power of two. The present invention is implemented in a number of different embodiments. These embodiments generally rely upon an image processor which, depending on the particular implementation, includes memory devices and an adder, a comparator, or a bit shifter. Additional embodiments use an image adjustment system to refine the raw input levels of the input device, in order to create an improved output image. Also, the particular embodiments of the image processors can be used in connection with imaging systems having bi-tonal, monochromatic, or color input and output devices.