Abstract: A method of detecting fractional channels in a telecommunications circuit. A non-idle data rate is measured for each channel in the telecommunications circuit. Channels having matching non-idle data rates are grouped into sets. Non-idle data rates are measured again for the channels within each set. In each set, any channels having non-matching non-idle data rates (with a small predetermined range of permissible variability) are eliminated. The measurement for each set is repeated multiple times. Each remaining set has channels that have substantially identical non-idle data rates over multiple time periods and each remaining set is assumed to constitute a fractional channel. Non-idle data rates are measured by counting non-idle octets over a fixed period of time, or by measuring throughput (non-idle octets per second) or by measuring utilization (throughput/capacity).

Abstract: An alignment and latching apparatus for a drive mechanism for data tape mini-cartridges. The alignment and latching apparatus enables the drive to use a new mini-cartridge while retaining backward compatibility with older smaller mini-cartridges. The mini-cartridges have a plastic top cover and a rigid metal baseplate. For some embodiments, an alignment datum is defined by three reference points on the bottom of the mini-cartridge baseplate. In other embodiments, the alignment datum is split with two reference points on the top of the baseplate and one reference point on bottom of the baseplate. Alignment and latching forces are applied on both the plastic cover and onto the baseplate. In some embodiments, alignment force on the top cover is provided by flat springs. In alternative embodiments, alignment force on the top cover is provided by spring loaded rollers.

Abstract: An automated analysis system that identifies detectability problems, diagnosability problems, and possible ways to change rank order of diagnoses in a diagnostic system and makes the problems and possible improvements visible to test programmers to aid in test improvement. Components that have no coverage and components that have inadequate coverage (according to a heuristic criteria) are identified as potential detectability problems. Components that are exercised by identical operations in all tests are identified as diagnosability problems. If an incorrect diagnosis is made, the automated analysis system identifies failing tests that have no coverage of any component in the true failure cause. In addition, if an incorrect diagnosis is made, the automated analysis system identifies ways of changing the rank order of diagnoses, including coverages that can be reduced and identification of operation violations that can be eliminated or deliberately added.

Abstract: An enclosure having two pieces that are held together with spring clips and having a stand that covers each spring clip. The spring clips provide a high retention force for vibration and shock. The stands cover the spring clips and provide anti-slip feet. In an example embodiment, the enclosure has a hinge surface formed from mating edges of the two pieces on one side with the spring clips holding the two pieces together on an opposite side. For automated assembly, the two pieces are joined at the hinge surfaces and then snapped into the spring clips and stands.

Abstract: A system and method of improving the thermal characteristics of a system having at least two electronic devices (100, 102; 300, 302) connected to a common substrate (104; 304). Thermal characteristics include the amount of heat transferred from one device to another and spatial uniformity of heat transferred from one device to another. Thermal conductive paths between two electronic devices are lengthened by forming an opening (200; 306) through the substrate between the two devices. Heat conduction between the devices is reduced due to increased radiation and convection in the longer thermal conductive paths. The uniformity of heat distribution between the devices is improved due to a narrower range of conducting path lengths. In a specific embodiment, heat conduction is reduced between amplifiers and photosensors used in spectrometers. In the specific embodiment, a temperature sensor (308) is used to further reduce thermal effects.

Abstract: A method for color imaging using a photosensor array having multiple rows of charge-coupled-device cells. The exposure times for each color channel are adjusted to provide improved signal-to-noise. The overall cycle time is determined by the channel having the weakest signal. A sufficient number of shift pulses are added to ensure that the weakest signal can still result in a full scale output. Once the total number of shift pulses per cycle is determined, the exposure times for the remaining channels are determined as a fraction of the weakest signal's required exposure (if possible). Each row has a separate transfer gate control input. The timing of the transfer gate pulses is then determined, preferably centering the exposure times to reduce color misregistration.

Abstract: A signal acquisition and display system that always provides the maximum possible display bandwidth that can be provided by the system without causing the display update rate to be reduced below the maximum determined by the acquisition time window. The optimization does not require analysis of a separate acquisition and does not require a repetitive waveform. The acquisition system alternates between two sections of memory, so that the minimum display update time is the longer of the acquisition time window or the display plot time. The display record length is variable. The display record length is controlled to make the display plot time always equal to or slightly less than the acquisition time window. Therefore, display bandwidth is always at the maximum possible given the acquisition time window and the maximum display update rate determined by the acquisition time window. Display record lengths may be very long compared to typical previous instruments.

Abstract: A graphical display system in which a background graphical image is at least partially visible within a foreground window. Examples of foreground windows include pull-down menus or pop-up dialog boxes. In a specific example embodiment, the background image is digitized waveform data for a digital oscilloscope, and the foreground window is an interactive dialog box for control. Digitized waveforms are at least partially visible in parts of the dialog box. The system has separate memories for the dialog box and the waveform data. A dual-path video controller chip can switch between the two memories for any pixel. The video chip is programmed to switch when the data from the dialog box memory is a particular programmed color. For translucent areas, a checkerboard pattern is defined in the dialog box memory in which alternate pixels in the dialog box memory are the programmed color. As a result, in the translucent areas, digitized waveforms are displayed in half the pixels in a checkerboard pattern.

Abstract: Method for efficiently and flexibly comparing a group of multi-bit binary fields with a multi-bit expected pattern to generate a set of final match results, one final match result for each binary field in the group. Sets of of bit-wise comparator results are generated, one set for each binary field, by comparing each binary field with the expected pattern. Then, sets of bit-wise mask results are generated for each binary field by bit-wise masking each set of bit-wise comparator results with a mask pattern. Then, a set of preliminary match results is generated. Each preliminary match result is equal to the logical AND of all bits making up the bit-wise mask result set for the corresponding binary field. Then, a set of secondary match results is generated by negating all of the preliminary match results if a negate indicator is asserted.

Abstract: Circuitry for detecting signal patterns on a multi-bit bus. First comparison circuitry monitors a first portion of the bus comparing it with a first expected signal pattern, generating a first comparison output. Second comparison circuitry monitors a second portion of the bus comparing it with a second expected signal pattern, generating a second comparison output. Both comparison outputs are applied to an AND gate and a first OR gate. One data input of a multiplexer is coupled to the output of the first OR gate. Another data input is coupled to the output of the AND gate. Another data input is coupled to the first comparison output, and another data input is coupled to the second comparison output.One input of a second OR gate may be coupled to the multiplexer output, and another input coupled to a disable indicator, allowing the multiplexer output to be overridden.

Abstract: A tape drive for a data tape mini-cartridge. Cartridges of interest have an internal capstan for an internal drive belt driven by a drive roller in the tape drive. The tape drive has a drive roller directly on a rotating exterior surface of the motor. In one example embodiment, the motor has an external rotor. In an example embodiment, no part of the motor diameter extends below or above the data cartridge. No intermediate rollers or belts are required. The motor stator is preferably mounted onto a metal support plate for heat conduction from the stator into the support plate. The motor preferably has space between the rotor and the support plate for air to flow into the stator for convection cooling. In addition, the motor rotor preferably includes cooling fins and air flow holes for additional convection cooling. A spring is mounted between the motor support plate and a chassis to provide a force holding the drive roller against the cartridge capstan.

Abstract: A circuit and method for generating write compensated write data signals in magnetic data recording. The circuitry is programmable to enable generation of write compensation meeting a variety of write compensation specifications. In particular, the circuitry can be programmed to generate extra write pulses, to adjust the pulse width and to adjust the pulse spacing within data cells. In an example embodiment, an input waveform drives a reset input on a state machine. An output waveform shape is stored as a pattern of bits in a register. The state of the state machine determines which register bits are selected by a multiplexer for output as a new write compensated write data signal.

Abstract: User-configurable diagnostic hardware contained on-chip with a microprocessor for the purpose of debugging and monitoring the performance of the microprocessor. Method for using the same. A programmable state machine is coupled to on-chip and off-chip input sources. The state machine may be programmed to look for signal patterns presented by the input sources, and to respond to the occurrence of a defined pattern (or sequence of defined patterns) by driving certain control information onto a state machine output bus. On-chip devices coupled to the output bus take user-definable actions as dictated by the bus. The input sources include user-configurable comparators located within the functional blocks of the microprocessor. The comparators are coupled to storage elements within the microprocessor, and are configured to monitor nodes to determine whether the state of the nodes matches the data contained in the storage elements.

Abstract: A buffer, implemented in computer memory, that never wraps data around from the buffer end to the buffer beginning unless the amount of data being transferred exceeds the entire size of the buffer. Eliminating wrapping improves performance by eliminating the need for the reading device to reconstruct a contiguous block of data from multiple reads. In addition, when possible, only the beginning portion of the buffer is used, thereby minimizing the occurrence of virtual memory page faults during buffer use and increasing the probability that pages near the end of the buffer will be freed for uninterrupted use by other processes. In addition to the usual read and write pointers, the buffer in the invention adds two variables, a buffer end pointer and a marker. When necessary, the buffer end pointer indicates the end of a block of data. The marker is used to limit the use of the buffer memory to a few pages at the beginning of the buffer when possible.

Abstract: A magnetic tape drive having a motor with a magnetically shielded cavity or hole in one cover of the motor providing additional room for movement of a magnetic head. The cavity eliminates a mechanical interference problem, enabling direct drive of a roller (puck) combined with short overall drive height. In motors having an internal stator, some of the stator poles are eliminated and a magnetically shielded cavity is provided in the area where the stator poles are eliminated. In motors having an external stator, no stator modification is required and a shielded cavity provides access into an open area of the rotor. In addition, for motors having an external stator and sufficient magnetic shielding, a simple hole in one cover of the motor may be sufficient rather than a magnetically shielded cavity.

Abstract: A multi-level instruction cache memory system for a computer processor. A relatively large cache has both instructions and data. The large cache is the primary source of data for the processor. A smaller cache dedicated to instructions is also provided. The smaller cache is the primary source of instructions for the processor. Instructions are copied from the larger cache to the smaller cache during times when the processor is not accessing data in the larger cache. A prefetch buffer transfers instructions from the larger cache to the smaller cache. If a cache miss occurs for the smaller cache, and the instruction is in the prefetch buffer, the system provides the instruction with no delay relative to a fetch from the smaller instruction cache. If a cache miss occurs for the smaller cache, and the instruction is being fetched from the larger cache, or available in the larger cache, the system provides the instruction with minimal delay relative to a fetch from the smaller instruction cache.

Abstract: A computer memory cache system that includes hardware (called a conflict cache) for short term tolerance and reduction of cache misses and including counters to enable software to detect and remove longer term cache misses through dynamic page remapping. In an example embodiment, when a conflict miss occurs for a low associativity cache, the address of the displaced item is saved in a content addressable memory and the corresponding data is saved in a data RAM. The operating system logically partitions the low associativity cache into bins, where the address range for a bin is a page or multiple pages. Every logical bin in the low associativity cache has a corresponding counter in the conflict cache. Each bin counter counts the number of conflict misses for the corresponding bin. When a bin counter exceeds a predetermined value, the operating system remaps a corresponding page.

Abstract: An associative cache memory for a computer with improved cache hit times. All possible data items are presented to bus driver circuits, thereby deferring data selection as long as possible. Driving and multiplexing are combined. The output of tag comparison directly selects at most one set of driver circuits. As a result, the only processing time in series with tag comparison is driver circuit selection. Since the data selection delay in series with tag comparison delay is reduced, the time delay is reduced for a clock edge for data driving after tag comparison, thereby enabling a faster clock.

Abstract: A driver circuit for capacitively loaded lines. The driver circuit has both precharge/pull-low and hold-high. The capacitively loaded line is precharged during a precharge phase of a clock signal. The driver circuit is active only during a drive phase of a clock signal. The driver has a hold-up transistor that is sufficiently large to suppress noise coupled into the line during the drive phase, but is substantially smaller than what is required to make pull-up time equal to pull-down time. The driver circuit provides the low noise characteristics of push-pull but with less circuit area and line capacitance than typical push-pull driver circuits.