Abstract: An enclosure includes a base having an interior volume and a first cover attachable to the base and adapted to cover a first portion of the interior volume of the base such that, with the first cover attached to the base, a second portion of the interior volume of the base is accessible. The enclosure further includes a second cover attachable to the base and adapted to cover a second portion of the interior volume of the base, wherein the first cover in combination with the second cover covers generally all of the interior volume of the base.

Abstract: A switching I/O node for connection in a multiprocessor computer system. An input/output node switch includes a bridge unit and a packet bus switch unit implemented on an integrated circuit chip. The bridge unit may receive a plurality of peripheral transactions from a peripheral bus and may transmit a plurality of upstream packet transactions corresponding to the plurality of peripheral transactions. The packet bus switch may receive the upstream packet transactions on an internal point-to-point packet bus link and may determine a destination of each of the upstream packet transactions. The packet bus switch may further route selected ones of the upstream packet transactions to a first processor interface coupled to a first point-to-point packet bus link and route others of the upstream packet transactions to a second processor interface coupled to a second point-to-point packet bus link in response to determining the destination each of the upstream packet transactions.

Abstract: A system and apparatus for a compact peripheral component interconnect (CPCI) computer system having exclusive front card access for both active and passive CPCI cards is provided. This system is further comprised of an active backplane with a front and rear side, a plurality of slots, each of these slots comprising of at least one connector and each of these connectors having a column and row arrangement of connector-pins, wherein individual ones of these connector-pins correspond to selected pairs of adjacent slots, and wherein selected adjacent slot pairs are reserved for particular pairs of CPCI cards comprising a single active card and a single passive card.

Abstract: A method for operating a cache having a sleep mode is provided. The cache is located within a memory hierarchy of a computer system, and the method is comprised of receiving a first cache request, and servicing the first cache request. A sleep mode signal is asserted in response to completion of the servicing of the first cache request. Thereafter, a second cache request is received, and the sleep mode signal is deasserted in response to receiving the second cache request. Thereafter, the second cache request is serviced.

Abstract: An apparatus for reordering packet transactions within a peripheral interface circuit. The apparatus includes a source tagging unit and a control unit. The source tagging unit may be configured to generate a plurality of tag values each corresponding to one of a plurality of packet commands. The control unit may include a first storage unit including a first plurality of locations and a second storage unit including a second plurality of locations. Each of the locations corresponds to one of the plurality of tag values. Each of the first plurality of locations may provide an indication of whether a given tag value corresponds to a first packet command in a given data stream. A first given location of the second plurality of locations corresponds to the tag value indicated by the first storage unit and stores a tag value of a second packet command in the given data stream.

Abstract: 1. An electronics assembly comprises: (i) a frame (1); (ii) a plurality of power supply modules (2) for supplying power to electrical circuitry of the assembly, each of which has an input power connector and an output power connector (27); and (iii) a power inlet connection module (26) which is electrically connected to a plurality of the power supply modules; wherein the power inlet connection module (26) is separated from the power supply modules (2) by an internal wall (36) of the frame which has, on one side thereof, at least one location element (50) for locating the power inlet connection module relative to the wall and, on the other side thereof, at least one location element (54) for locating each power supply module that is connected to the power inlet connection module relative to the wall so that the power supply modules are aligned with the power inlet connection module by means of the internal wall.

Abstract: Provided is a computer implemented method, system, and program for enabling communication between one network device that is a member of a first set of network devices that communicate using a first address format and one network device that is a member of a second set of network devices that communicate using a second address format. One frame is received from a first network device in the first set, wherein the frame is part of a first exchange of multiple frames between the first network device and one network device in the second set. A first address in the second address format is allocated to the first network device to use to communicate with the network device of the second set during the first exchange of the frames. One frame is also received from a second network device that is a member of the first set pursuant to a second exchange of multiple frames between the second network device and one network device in the second set.

Abstract: A tunnel device for an input/output node of a computer system. A tunnel device includes a first interface, a second interface and a control unit. The first interface may receive a plurality of data bytes associated with a command packet on a first external input/output bus. The second interface may be coupled to the first interface by an internal data path configured to convey up to a maximum number of data bytes in a given cycle. The control unit may be coupled to control the conveyance of the data bytes from the first interface to the second interface upon the internal data path. The first interface may further align the smaller number of data bytes on a corresponding number of designated bits of the internal data path with no intervening invalid data bytes when conveying a smaller number of data bytes than the maximum number of data bytes.

Abstract: An electronics assembly comprises: (i) a chassis (1); (ii) at least one front panel (40, 42) that is arranged in front of the chassis to obscure the chassis; and (iii) at least one device (60) that is mounted on the chassis and supports the or a front panel. The or each device (60) or the or each panel (40, 42) includes at least one retaining element (62) that extends out of the device or panel and is received in a recess in the or each panel or in the or each device respectively to retain the panel on the chassis. The element is manually retractable into the device or panel to allow the panel to be removed from the chassis. The assembly may include, for example, air filters in the panel(s), and these may be changed quickly so that the assembly does not need to be powered down.

Abstract: A system and method for carrying out a two-dimensional forward and/or inverse discrete cosine transform is disclosed herein. In one embodiment, the method includes, but is not necessarily limited to: (1) receiving multiple data blocks; (2) grouping together one respective element from each of the multiple data blocks to provide full data vectors for single-instruction-multiple-data (SIMD) floating point instructions; and (3) operating on the full data vectors with SIMD instructions to carry out the two dimensional transform on the multiple data blocks. Preferably the two dimensional transform is carried out by performing a linear transform on each row of the grouped elements, and then performing a linear transform on each column of the grouped elements. The method may further include isolating and arranging the two dimensional transform coefficients to form transform coefficient blocks that correspond to the originally received multiple data blocks.

Abstract: A method and apparatus for manipulating work queue elements via a hardware adapter and a software driver. The software driver is configured to cause a plurality of work queue elements to be stored in a queue pair including a plurality of storage locations. Each of the plurality of storage locations includes an indicator indicating whether a corresponding work queue element has been completed. The hardware adapter is configured to select one of the plurality of storage locations and to service a corresponding one of the plurality of work queue elements, and in response to completion of a task associated with the corresponding work queue element, to cause the indicator to indicate that the corresponding work queue element has been completed. Additionally, the software driver is configured to cause a new work queue element to be stored in the selected storage location in response to detecting that the indicator indicates that the corresponding work queue element has been completed.

Abstract: A processor-based system such as a workstation or server, using a system clock provided through a phase-locked loop (PLL) to a clock gate and then to a clock tree, which distributes the core system clock to components in the processor-based system, including a host bridge circuit. The host bridge distributes control signals to a receiving device such as a memory module, which may use a continued clocking signal when the system enters a low-power mode. A feedback clock for the PLL is provided to the receiving devices during low-power mode to ensure continued clocking, when the clock gate output is low and the clock tree is thereby disabled. A skew compensation circuit coordinates clocking in the continued clock and the core system clock.

Abstract: There is provided a cooling fan drive circuit for driving a pair of cooling fans. The circuit comprises a first power supply line for providing a power connection to each of the fans from a first power source. The circuit further comprises a second power supply line for providing a power connection to the first fan; and a third power supply line for providing a power connection to the second fan. The second and third power supply lines are arranged, in use, to provide separate connections between the respective fans and a power source other than the first power source.

Abstract: Methods and systems for storage architectures are provided. Storage resource provider modules interface with storage resources to perform storage operations. A storage management data store maintains storage data associated with a storage environment of the storage resources. The storage resource provider modules retrieve and update the storage management data in response to processing the storage operations. In one embodiment, a storage management application requests a selected storage resource provider module to perform a selected storage operation. The storage management application determines the selected storage resource provider module by acquiring the storage management data in the data store.

Abstract: A microprocessor includes a plurality of execution units each configured to execute instructions and an instruction dispatch circuit configured to dispatch instructions for execution by the plurality of execution units. A power management control unit includes a programmable unit for storing information specifying one or more reduced power modes. In the implementation of a first performance throttling technique, the power management control unit may be configured to cause the instruction dispatcher to limit the dispatch of instructions to a limited number of execution units. In the implementation of a second performance throttling technique, the power management control unit may be configured to limit the dispatch of instructions from the instruction dispatcher on every cycle, upon every other cycle, upon every third cycle, upon every fourth cycle, and so on.

Abstract: A method and device for virtual memory support in a computer system using a mapping structure for address translation. Mapping indicators are associated with each process context and each mapping structure entry. When a context is demapped the mapping indicator associated with the context is changed and the mapping indicator in each mapping structure entry is employed to immediately invalidate further memory accesses for that context.

Abstract: A signal communication device for use within a computer includes a set of optical fibers configured to form an optical computer bus between a set of computer sub-system elements of a computer. A set of input optical connector cards are connected to the set of optical fibers. Each of the input optical connector cards includes a transmitting dynamic bandwidth allocator responsive to an optical bus clock signal operating at a multiple of a computer system clock signal such that a set of bus time slots are available for each computer system clock signal cycle. The transmitting dynamic bandwidth allocator allows a light signal to be applied to the optical computer bus during a dynamically assigned bus time slot. In this way, the optical computer bus bandwidth can be dynamically allocated to different computer sub-system elements during a single computer system clock signal cycle.

Abstract: A system and method for improving the isolation and diagnosis of hardware faults in a computing system wherein means are provided for indicating whether unusable data has previously triggered diagnosis of the hardware fault that caused the data to be unusable. If diagnosis has not been performed, the flag is not set. If diagnosis has already been performed, the flag is set. One embodiment comprises an interface which is used to convey data from one subsystem to another. When the interface receives data from the first subsystem, the data is examined to determine whether it contains an uncorrectable error (including missing data.) If the data contains an uncorrectable error, the interface examines the flag corresponding to the data to determine whether hardware fault diagnosis has already been initiated. If diagnosis has already been initiated, the data is passed to the second subsystem without initiating further diagnosis.

Abstract: Various methods and systems for implementing a sectored least recently used (LRU) cache replacement algorithm are disclosed. Each set in an N-way set-associative cache is partitioned into several sectors that each include two or more of the N ways. Usage status indicators such as pointers show the relative usage status of the sectors in an associated set. For example, an LRU pointer may point to the LRU sector, an MRU pointer may point to the MRU sector, and so on. When a replacement is performed, a way within the LRU sector identified by the LRU pointer is filled.