Abstract: An ejector mechanism (14) for a circuit board (21) and back plane (61), the ejector mechanism being operable to provide resiliently biased engagement between a first part (10) of an electrical connector (8) and a mutually engaging second part (12) of the electrical connector (8), the first and second parts of the electrical connector providing electrical connection for a plurality of electrical channels between the circuit board on which the first part is mounted and the back plane on which the second part is mounted. The ejector mechanism comprises an engaging projection (42) and a lever arm (40) pivotally mounted on one of the circuit board and the back plane and configured to engage the engaging projection (42) forming part of the other of the circuit board and the back plane.

Abstract: An interconnecting apparatus employing a lossy power distribution network to reduce power plane resonances. In one embodiment, a printed circuit board includes a lossy power distribution network formed by a pair of parallel planar conductors separated by a dielectric layer.

Abstract: Several methods are described for building and using a network device database. The network includes multiple enclosures, and each enclosure houses at least one device (e.g., a data storage device). The network may be, for example, a storage area network. One embodiment of a method for deriving the addresses of all devices of the network includes repeating the following steps for each enclosure of the network. A command is issued to the enclosure requesting information comprising device identifications (IDs) of all devices within the enclosure. A portion of an address of the enclosure is concatenated with each device ID to form the addresses of all devices within the enclosure. The network may include one or more Fibre Channel Arbitrated Loops (FC-ALs). In this case, the addresses of the enclosures and the devices coupled FC-ALs are fabric addresses. Each enclosure may include a small computer system interface (SCSI) enclosure services (SES) unit.

Abstract: An efficient method is described for laying out a table for display. The method may be used to display tables on a small footprint device, such as a smart cellular phone, a personal data assistant, a handheld computer, etc. Small footprint devices typically have smaller displays than other computing systems such as desktop computers. In one embodiment the method is employed to lay out HTML tables in a web browser running on a small footprint device.

Abstract: The present invention provides a method and apparatus for packaging high frequency electrical and/or electro-optical components. The present invention provides a package which may be surface mounted on a board with other electrical components. The shielding provided by the package minimizes electromagnetic interference with other electrical components on the board. The package includes a controlled impedance I/O interface for coupling with the electrical and/or electro-optical component(s) in the package. The package interface may also include a differential I/O capability to further control electromagnetic fields generated at the interface. Additionally, the package may include an optical link provided by one or more optical fibers extending from the package.

Abstract: A digital data processing apparatus configured to selectively transfer data between a primary data storage element and an associated data file on a secondary data storage element. The apparatus includes a primary data storage element that stores data for access by one or more processes, as well as a non-volatile secondary data storage element. A directory stores attributes reflecting a state of one or more subsets of data in respective sets. During transfer of data between the primary data storage element and the secondary data storage element, the apparatus stores data corresponding to the attribute in a second file on the second storage element, in response to detecting the transfer and detecting the attribute indicates an atomic state corresponding to the first data.

Abstract: A mechanism for minimizing interrupt context execution in a computer system by providing means for a driver to select the context for its execution. The operating system determines the system processing load and stores this information for use by the driver software. Based on the system processing load information, each driver then selects an execution context which meets its particular service requirements. When the system processing load is low and a lower-priority context will provide adequate service to the application, the lower-priority context is selected in order to reduce the amount of interrupt context execution. When the system processing load is high and a lower-priority context may not provide adequate service to the application, a higher-priority context is selected in order to ensure that execution of the application is within the driver's latency requirements.

Abstract: A heatsink for dissipating thermal energy generated by a microprocessor and neighboring peripheral components. The heatsink is affixed to a printed circuit board within a computer housing. The heatsink includes a thermally conductive base, a plurality of thermally conductive fins, and a heat pipe. The thermally conductive base includes substantially planar upper and lower surfaces displaced from each other by a thickness of the base. The base defines a first channel, proximal to the lower surface, extending from a first end of the base to a second end. The plurality of conductive fins extends substantially perpendicularly from the upper surface of the base. Each of the plurality of fins includes substantially planar proximal and distal major surfaces displaced from each other by a thickness of the fin. The heat pipe is contained within the first channel. The heat pipe includes an elongated casing containing a heat transfer medium and a wick.

Abstract: A fiber optic cable is provided with a thermal shield which consists (proceeding outward from the cable) of a temperature insulating layer of a foam plastic such as polyethylene, a plastic film wrap such as aluminized nylon, a metallic braid such as tinned copper and an outer jacket of plastic as additional temperature insulation and to facilitate pulling the cable. The film wrap and outer jacket are optional. For further shielding a second layer of foam plastic may be positioned outside the first metallic braid followed by a second plastic film wrap, a second metallic braid and an outer plastic jacket. If the shielded cable is near a source of heat, such as a hot water pipe or an air conditioning duct, the fiber optic cable temperature is uniform throughout its cross-section. Without the thermal shield instability of the signals in different fibers may occur because of heat differential.

Abstract: A data block includes a plurality of sub-blocks. Each sub-block includes a sub-block check bit that may be used to detect the presence of a bit error within the sub-block. A composite sub-block is generated, which is the column-wise exclusive-or of the bits of each sub-block. In one embodiment, the composite sub-block is not stored, but rather used for computational purposes only. A plurality of composite check bits is used to detect a bit position of a bit error within the composite sub-block. If a bit error within the data block occurs, the sub-block check bits may be used to detect in which sub-block the error occurred. The composite check bits may be used to determine which bit position of the composite sub-block is erroneous. The erroneous bit position of the composite sub-block also identifies the bit position of the erroneous bit in the sub-block identified by the sub-block check bits.

Abstract: An improved method for generating an NTSC compatible color television video signal having a main carrier signal and a color subcarrier signal 3,579,545 Hz above the main carrier signal. The main carrier signal is modulated by a luminance signal, while the color subcarrier is modulated in quadrature with color difference signals. The luminance and color difference signals provide 525 scan lines of picture frame information at a rate of 29.97 frames per second so that the color subcarrier has 227.5 cycles for each scan line, resulting in 119,437.5 color subcarrier cycles per frame. The additional half cycle causes a subcarrier phase inversion from frame to frame, which produces undesirable dot-crawl. The improvement comprises incrementing the phase of the color subcarrier by a fixed increment at a number of predetermined intervals in each picture frame, to produce a total phase shift which prevents the phase inversion. The total phase shift is an odd-half-multiple of a color subcarrier cycle.

Abstract: A network interface unit which implements a low latency algorithm for buffer credit calculation. In one embodiment, a system network is provided with a remote node coupled to a local node by a serial communications link. The remote node is configured to transmit a data frame to the local node only if the remote node receives a buffer credit which indicates that the local node has available receive buffer space for a data frame. The local node includes a network interface unit for coupling to the serial communications link, and the network interface unit includes a receive buffer, a receive controller, a transmit controller, and a buffer credit manager. The receive controller stores incoming data frames in the receive buffer until they can be forwarded to the i/o bus of the local node. The transmit controller is configured to send buffer credits to the remote node in response to a credit signal from the buffer credit manager.

Abstract: A multiphase power supply that minimizes losses during a low power mode+. In a particular embodiment, a multiphase power supply may include a plurality of switching regulators coupled in parallel with respect to one another. The multiphase power supply further comprises a phase control circuit coupled to each of the switching regulators. The phase control circuit is configured to generate a plurality of control signals for controlling the switching of the switching regulators so that they are out of phase with respect to one another. During the low power mode of operation of the microprocessor, the phase control circuit is configured to selectively suspend operation of a subset of switching regulators by removing or disabling at least one of the plurality of control signals to each of the subset of switching regulators.

Abstract: A frame-rate clock of a plurality of data buses is synchronized to a master clock signal. The master clock signal may be derived from the existing clock signals within the computer system or from data received from an external source. The master clock signal may also be used by an operating system scheduler to schedule tasks that generate or consume blocks of isochronous data. The drift of a device clock signal relative to a master clock signal is measured and used to synchronize the device clock signal. For example, a mechanism may monitor the level of data in a data buffer. The level of data in the data buffer is a measure of the drift between the clock generating the data and the clock consuming the data. Based upon the level of data in the buffer, synchronization information is provided to synchronize the rates of the clock signals that generate and consume the data.

Abstract: An audio decoder architecture makes use of various component sharing techniques to conserve hardware and reduce implementation cost. In one embodiment, the audio decoder comprises a bitstreamer, a synchronization controller, a first and second decode controllers, a memory module, a data path, and an output buffer. The bitstreamer retrieves compressed data and provides token-aligned data to the synchronization controller and decode controllers. The synchronization controller initially controls the bitstreamer to locate and parse audio frame headers to extract decoding parameters. The synchronization controller initiates the decode controller which corresponds to an identified compression format, and turns control of the bitstreamer and data path over to the selected decode controller. The selected decode controller then controls the bitstreamer to parse the variable length code compressed transform coefficients.

Abstract: A power sub-system controls the supply of power to a field replaceable unit. The power sub-system includes a main power controller that supplies main power to at least a first component of the field replaceable unit, and a standby power controller that supplies standby power to at least a second component of the field replaceable unit. The main power controller is operable to switch off the supply of main power to a first component in response to the detection of a fault, whereas the standby power controller maintains the supply of standby power to the second component. By providing separates power controllers for main and standby power, it is possible to maintain power to one or more selected components of the FRU in the event of a fault that requires main power to the FRU to be cut. Standby power is switched off automatically in response to a first change in state of an interlock signal that is indicative of the field replaceable unit being released.

Abstract: A message dispatch system is provided for a multi-computer server having a number of server computers connected via respective server network links. The message dispatch system, which is connectable to an external telecommunications network, includes a message dispatcher configured to receive external client requests for the multi-computer server from the external telecommunications network and to dispatch the client requests to selected server computers via the server network links. The message dispatcher is configured to determine a server to which an external client request is to be dispatched in response to parameters representative of message traffic volume on the server network links. Load balancing is performed based on parameters representative of the server network link loading, rather than, or possibly in addition to measurements on processor loading. Suitable network loading parameters can be derived by monitoring packets passing from and/or to the individual server computers.

Abstract: A modem which enables re-negotiation of the selected modem technology subsequent to the original negotiation which takes place at initiation of the modem connection. The invention includes means for one modem to interrupt data transfer and transmit a signal to the other modem indicating a request that a different modem technology be used. The request may be made as a result of changing line conditions, changing system demands, changing data transfer requirements, or other altered conditions under which the modems are operating. If the modem receiving the request accepts the request, both modems re-enter negotiation to select the best modem technology under the changed conditions. The modems are then re-trained to select the best bit rate within that technology under the existing line conditions. After the new modem technology and bit rate are selected, the modems resume transferring data.

Abstract: A floating point unit is provided which conveys the rounding mode in effect upon dispatch of a particular instruction with that particular instruction into the execution pipeline of the floating point unit. Upon dispatch of a control word update instruction into the execution pipeline, the rounding mode is updated according to the updated control word provided for the control word update instruction. Instructions subsequent to the control word update instruction thereby receive the updated rounding mode as those instructions are dispatched. The updated rounding mode is available to the subsequent instructions prior to retiring the control word update instruction. The rounding mode is therefore updated without serializing the update. If the control word update instruction modifies the value in a field other than the rounding mode, the instructions subsequent to the control word update instruction may be discarded and re-executed subsequent to updating the control word register with the updated control word.

Abstract: The bits of a data block are assigned to a plurality of logical groups such that at most one bit corresponding to a component is assigned to a logical group. This assignment ensures that a component failure may introduce at most one bit error to a logical group. A number of bits in a logical group is selected to reduce the number of check bits for a given number of data bits. Error correction may be performed within each logical group to correct single errors within the logical group. Because each logical group is assigned at most one bit corresponding to a component, component failures may be detected and corrected.