Abstract: A circuit module for a rack-mounted circuit has a motherboard detachably mounted in the module for removal and replacement while the module remains in the rack.

Abstract: A real time clock (RTC) is described several timekeeping dependability and timekeeping security attributes. The RTC may have several registers for storing values, at least one of which stores a value which is safeguarded. For example, a “TrustQualityState” register stores a “TrustQualityState” value which is dependent upon a timekeeping accuracy of the RTC. The “TrustQualityState” value may also be dependent upon timekeeping stability, reliability, and/or security of the RTC (e.g., a tamper resistance of the RTC). The RTC includes an access unit coupled between the “TrustQualityState” register and a bus used to access the “TrustQualityState” register. The access unit controls access to the “TrustQualityState” register in order to safeguard the “TrustQualityState” value. The access unit receives read and write commands directed to “TrustQualityState” register via the bus.

Abstract: A method for identifying stale transactions in a queueing system with transaction processors. The method includes identifying actual processing times of transactions, maintaining a running total of deviations of processing times from a maximum expected processing time and signaling when the running total exceeds a threshold time limit.

Abstract: The present invention relates to a method and circuit for prefetching direct memory access descriptors from memory of a computer system, and storing the prefetched direct memory access descriptors within a unified descriptor memory for subsequent access by direct memory access controllers. The descriptors are generated by a central processing unit of the computer system while executing software applications. The descriptors define data transfer operations between memory of the computer system and input/output devices via direct memory access controllers. The direct memory access controllers generate requests for descriptors. Upon generation of a request, the unified descriptor memory is checked to determine whether the requested descriptor is contained therein. If the requested descriptor is contained within the unified descriptor memory, the request descriptor is provided to the requesting direct memory access controller.

Abstract: The present invention discloses methods and apparatus for installing printed circuit boards within an electronic assembly. One embodiment is a riser card bracket assembly for an electronic system. The riser card bracket comprises an adjustable card retainer disposed within the riser card bracket assembly; the retainer is capable of movement within the riser card bracket assembly to secure cards of various lengths. Another embodiment of the invention is a method for installing cards within a computer housing having a motherboard. The method comprises providing a riser card bracket assembly having an adjustable card retainer. At least one card is inserted within the riser card bracket assembly. The riser card bracket assembly is inserted within the computer housing whereby the at least one card is positioned parallel to the motherboard.

Abstract: A computer system employing redundant cooling fans. A system includes a first and a second array of circuit boards and a first and a second cooling fan. The two arrays of circuit boards are positioned such that the first array of circuit boards is substantially perpendicular to the second array of circuit boards. The first fan is positioned close to the first array of circuit boards and the second fan is positioned close to the second array of circuit boards. The first fan is positioned to force intake air across the first and the second arrays of circuit boards and the second fan is positioned to exhaust the forced intake air after it passes over the second array of circuit boards. Each of the fans may be hot swappable.

Abstract: A virtual network environment to be used by a set of applications for the express purpose of isolating the applications from other applications on the same node or network is disclosed. The virtual network environment encapsulates a set of applications within a virtual network and prevents applications from interfering, either maliciously or unintentionally, with other applications outside of its virtual network environment. This virtual network environment provides security and network isolation between applications, as is required in a hosted application environment.

Abstract: There is described a servicing connection for connecting an electrical device to a supply outlet, wherein live and neutral contacts of the supply outlet are isolated from live and neutral contacts of the device, but a connection is maintained between earth contacts of the supply and the device. The connection may be embodied as an adaptor for interposition between a conventional supply outlet and a conventional power inlet of the device, or may be in the form of a power inlet capable of receiving a supply cord in alternative “servicing” and “operation” positions. There is also described a connection in the form of a power cord for use with a conventional power inlet, and having an additional connector engageable with the power inlet to make an earth connection only.

Abstract: Disclosed herein is a method and associated apparatus for the design and manufacture of VLSI circuit which incorporates therein a method for routing connections between component tiles of the VLSI circuit being designed.

Abstract: An ejector mechanism is provided for a field replaceable module (e.g., a server blade) of modular computer system (e.g., a blade server system). The field replaceable module can be received in a carrier of the modular computer system and can have an elongate face. An ejector mechanism, that can possibly also act as an injection mechanism, can be located at the elongate face and can include an elongate lever extending substantially along the elongate front face. A pivotal mounting for the lever can be located towards a first end thereof and an ejection protrusion can be provided at the first end. The use of a lever that extends substantially along the elongate face of the field replaceable module provides an efficient ejection mechanism with good mechanical advantage.

Abstract: A system and method for monitoring and controlling a power-manageable resource. In one embodiment, a power manageable resource, such as a bus in a computer system, may be shareable among a number of power-manageable devices. A resource monitor may also be coupled to the power-manageable resource. The resource monitor may be configured to monitor the devices coupled to the power manageable resource. More specifically, the functions of the resource monitor may include monitoring the active/inactive state of each of the attached devices. The resource monitor may be configured to cause the sharable resource to be powered down if it is determined that all the attached devices are in an inactive state.

Abstract: A buffer circuit for rotating outstanding transactions. A buffer circuit includes a buffer and a command update circuit. The buffer may be configured to store packet commands that belong to a respective virtual channel of a plurality of virtual channels. The packets may be stored in the buffer to await transmission upon a peripheral bus. Once a given packet is selected for transmission, a peripheral bus cycle corresponding to the given packet command may be generated upon the peripheral bus. The command update circuit may be configured to generate a modified packet command in response to receiving a partial completion indication associated with the peripheral bus cycle. The command update circuit may also be configured to cause the modified packet command to be stored within the buffer.

Abstract: A multiprocessor system is disclosed that employs an apparatus and method for caging a redundant component to allow testing of the redundant component without interfering with normal system operation. In one embodiment the multiprocessor system includes at least two system controllers and a set of processing nodes interconnected by a network. The system controllers allocate and configure system resources, and the processing nodes each include a node interface that couple the nodes to the system controllers. The node interfaces can be individually and separately configured in a caged mode and an uncaged mode. In the uncaged mode, the node interface communicates information from either of the system controllers to other components in the processing node. In the caged mode, the node interface censors information from at least one of the system controllers.

Abstract: A buffer circuit for a peripheral interface circuit in an I/O node of a computer system. A buffer circuit includes a first buffer and a second buffer. The first buffer may be configured to store a plurality of selected packet commands within a plurality of storage locations. The second buffer is coupled to the first buffer and may be configured to store a plurality of index values. Each index value corresponds to one of the storage locations in the first buffer. The buffer circuit further includes a write logic circuit that is coupled between the first buffer and the second buffer. The write logic circuit may be configured to successively read each of the plurality of index values from the second buffer and to cause a selected packet command to be stored in each storage location corresponding to each of the plurality of index values within the first buffer.

Abstract: A system and method for transferring data using an early response signal to indicate subsequent transmission of data after a fixed latency, wherein the signal and data are transferred from a first clock domain to a second clock domain using a clock skipping technique. In one embodiment, an early response signal is transmitted by a first device k clock pulses prior to transmission of the data. The receiving device, which is operating at a higher clock rate, receives the early response signal and delays the signal by the number of skipped pulses which will occur in the second clock domain before the occurrence of the kth valid pulse. The second device employs a skip pattern generator to generate a signal indicative of this number of skipped pulses and provides the number to a delay circuit which delays the early response signal for an this number of clock pulses. The delayed early response signal is then output to the appropriate logic to indicate the latency of the subsequent data transfer.

Abstract: A system and method for distributing power to an integrated circuit. In one embodiment, a power laminate may be mounted to a printed circuit board (PCB). The integrated circuit for which power is to be distributed may be electrically coupled to the PCB. The power laminate may include one or more power planes and one or more reference (i.e. ground) planes, with each pair of power/reference planes separated by a dielectric layer. The power laminate may also include a connector or other means for receiving power from an external power source. The power laminate may be electrically coupled to the integrated circuit, thereby enabling it to provide core power to the integrated circuit. The power laminate may also include a voltage regulator circuit, and a plurality of decoupling capacitors. In one embodiment, the power laminate may include a plurality of apertures which allow for the passing of connections between the integrated circuit and the PCB.

Abstract: A method for initializing a computing system comprising a plurality of devices which communicate on a communication link comprising a plurality of independent point-to-point links is provided, each of the point-to-point links interconnecting a respective pair of the plurality of devices. The method includes a link initialization procedure comprising initially configuring each respective pair of devices to communicate on the respective interconnecting link using common communication parameters, including a common frequency and a common link width. The link initialization procedure also may include an optimization procedure for determining maximum communication parameters for each interconnected pair of devices. If the maximum compatible parameters differ from the common parameters for any pair of devices, then the pair of devices may be reconfigured to communicate on the interconnecting link using the maximum compatible parameters.