Abstract: The invention provides an improved automated system and method for monitoring the states of other systems. In one embodiment, the inventive system and method may be employed by an operations console that is monitoring the state of one or more data processing systems. According to the invention, a set of states is defined to describe events or conditions occurring within the monitored systems. A set, or “family”, of files is defined, wherein the family includes an associated file for each of the defined states. When one or more of the monitored systems are determined to be in a predetermined state, data signals stored within the associated file may be used to generate some type of signal that may be readily perceived by the operator to determined the state. For example, the data signals may be used to generate a visual or audio representation of the state.

Abstract: A program and method enables easy creation and manipulation of timing charts. The preferred embodiment employs off-the-shelf commercial software and uses Visual Basic commands to get timing chart drawing commands into the drawing program and out of the spreadsheet program to order the drawing program to produce a displayable and print/plotable file. The user can easily see changes needed and even if they require ripple-through redrawing, because the user manipulates data in the spreadsheet file instead of directly manipulating drawing commands, the spread sheet will carry through ripple-through calculations to modify all lines related to the recalculated data.

Abstract: A method and apparatus is provided for handling parity errors within a data processing system. Each occurrence of a parity error is attributed to an addressable memory location or a block of memory locations that was being accessed when the error occurred. A memory location or a memory block is marked as unusable after a predetermined number of errors is attributed to that location or block, respectively. The predetermined number of errors that is allowed to occur prior to degradation could be two, or more. In one embodiment, the predetermined number of errors resulting in memory degradation is programmable.

Abstract: Database access operations require a process of first locating a database of data that contains requested data and then retrieving the requested data from within the database table. The database tables are stored within a database file that contains an index structure to assist in the determination of the location of the table within the file. Depending upon the structure of the tables and their location within the database file, different searching methods may be used to determine the location of the table. Each searching method results in a different processing efficiency for the search. However, the most efficient searching methodologies operate only on database files having a preferred structure. The least efficient searching methodologies will operate on all database files. The present invention determines the most efficient searching methodology that is supported by a database file when it is registered with a processing system.

Abstract: The current invention provides a system and method for maintaining memory coherency within a multiprocessor environment that includes multiple requesters such as instruction processors coupled to a shared main memory. Within the system of the current invention, data may be provided from the shared memory to a requester for update purposes before all other read-only copies of this data stored elsewhere within the system have been invalidated. To ensure that this acceleration mechanism does not result in memory incoherency, an instruction is provided for inclusion within the instruction set of the processor. Execution of this instruction causes the executing processor to discontinue execution until all outstanding invalidation activities have completed for any data that has been retrieved and updated by the processor.

Abstract: A synchronous pipeline design is provided that includes a first predetermined number of fetch logic sections, or “stages”, and a second predetermined number of execution stages. Instructions are retrieved from memory and undergo instruction pre-decode and decode operations during the fetch stages of the pipeline. Thereafter, decoded instruction signals are passed to the execution stages of the pipeline, where the signals are dispatched to other execution logic sections to control operand address generation, operand retrieval, any arithmetic processing, and the storing of any generated results. Instructions advance within the various pipeline fetch stages in a manner that may be independent from the way instructions advance within the execution stages. Thus, in certain instances, instruction execution may stall such that the execution stages of the pipeline are not receiving additional instructions to process. This may occur, for example, because an operand required for instruction execution is unavailable.

Abstract: This invention provides to large-scale operating systems supporting multiple classes of tasks a method to allocate processor resources to the classes according to a probability model. It is useful in preventing a class from being denied resources by giving it positive measure in the model. A first stage probability algorithm assigns classes of tasks to an IP resource available to a given scheduler queue. Each class is allocated a probability level in a lottery-type draw in this first stage. In preferred embodiments, a second stage probability algorithm is used to assign tasks within a class to an available processor resource. This second stage algorithm is biased in a feedback manner by task resource usage history. Tasks of extreme high or low priority may avoid the probabilistic mechanisms in preferred embodiments.

Abstract: The current invention provides a system and method for managing requests from one or more requesters to one or more resources. These requests, which may be any of multiple request types, are prioritized using one or more threshold values. Each threshold value is associated with one or more of the request types, and defines the maximum number of requests of the associated types that may be pending to the resources before the threshold is reached. When all associated thresholds have been reached for requests of one or more predetermined request types, an indication is provided to re-issue requests of those types at a later time. A priority scheme is used to allow re-issued requests to systematically gain access to the shared resource to prevent the starvation of any given requester.

Abstract: A system and method for managing memory data within a data processing system is disclosed. A main memory is provided to store data signals. When the main memory receives a request to read data signals, the main memory determines whether an updated copy of the requested data signals may be stored within some other storage device within the system. If so, the main memory issues a snoop request to this other storage device to cause any updated copy of the requested data to be returned to the main memory. In addition, the main memory reads the requested data signals from its data store. This data will be used to satisfy the read request if an updated copy of the data signals is not returned to the main memory in response to the snoop request. Otherwise, the updated copy is provided to fulfill the request.

Abstract: A system and method for pre-fetching data signals is disclosed. According to one aspect of the invention, an Instruction Processor (IP) generates requests to access data signals within the cache. Predetermined ones of the requests are provided to pre-fetch control logic, which determines whether the data signals are available within the cache. If not, the data signals are retrieved from another memory within the data processing system, and are stored to the cache. According to one aspect, the rate at which pre-fetch requests are generated may be programmably selected to match the rate at which the associated requests to access the data signals are provided to the cache. In another embodiment, pre-fetch control logic receives information to generate pre-fetch requests using a dedicated interface coupling the pre-fetch control logic to the IP.

Abstract: The current invention provides a system and method for managing data stored within a main storage device such as a main memory. In one embodiment, multiple requesters are coupled to the main storage device to store copies of ones of the data signals. A directory is coupled to the main storage device to store directory signals that describe the most recent copy of each the data signals. Another storage device is coupled to the directory to store a subset of the directory signals that describes a predetermined subset of the data signals. This subset of directory signals can be used to access any of the predetermined subset of the data signals in an accelerated manner.

Abstract: A system and method is provided to selectively flush data from cache memory to a main memory irrespective of the replacement algorithm that is used to manage the cache data. According to one aspect of the invention, novel “page flush” and “cache line flush” instructions are provided to flush a page and a cache line of memory data, respectively, from a cache to a main memory. In one embodiment, these instructions are included within the hardware instruction set of an Instruction Processor (IP). According to another aspect of the invention, flush operations are initiated using a background interface that interconnects the IP with its associated cache memory. A primary interface that also interconnects the IP to the cache memory is used to simultaneously issue higher-priority requests so that processor throughput is increased.

Abstract: A dual-channel memory system and accompanying coherency mechanism is disclosed. The memory includes both a request and a response channel. The memory provides data to a requester such as an instruction processor via the response channel. If this data is provided for update purposes, other read-only copies of the data must be invalidated. This invalidation may occur after the data is provided for update purposes, and is accomplished by issuing one or more invalidation requests via one of the memory request or the response channel. Memory coherency is maintained by preventing a requester from storing any data back to memory until all invalidation activities that may be directly or indirectly associated with that data have been completed.

Abstract: An improved system and method are provided for initializing memory in a data processing system. According to one aspect of the invention, a “page zero” instruction is provided that may be executed by an Instruction Processor to initiate memory initialization. Upon instruction execution, the IP issues one or more page zero requests using a background interface of the IP. In one embodiment, each request results in the initialization of a page of memory. While page zero requests are issued over the background interface, the IP may continue issuing other read and write requests to memory over a primary interface of the IP.

Abstract: A mechanism to selectively leak data signals from a cache memory is provided. According to one aspect of the invention, an Instruction Processor (IP) is coupled to generate requests to access data signals within the cache. Some requests include a leaky designator, which is activated if the associated data signals are considered “leaky”. These data signals are flushed from the cache memory after a predetermined delay has occurred. The delay is provided to allow the IP to complete any subsequent requests for the same data before the flush operation is performed, thereby preventing memory thrashing. Pre-fetch logic may also be provided to pre-fetch the data signals associated with the requests. In one embodiment, the rate at which data signals are flushed from cache memory is programmable, and is based on the rate at which requests are processing for pre-fetch purposes.

Abstract: Methods are executed upon data objects distributed across a plurality of nodes of a system from a user-held “special” device (such as a cell phone, palm top, set top, car GPS system, . . . ). Heterogeneous data at a plurality of remote nodes is accessed automatically in parallel at high speed using a simple script request containing a data source object name wherein the heterogeneous data is treated as a single data source object, the script further containing code representing a user-defined program to be executed on the data source object. An agent breaks the user-generated script into new scripts appropriate for execution at the remote nodes. A messenger process transmits the new scripts to the appropriate remote nodes where respective agent processes respond to automatically access the appropriate data and to automatically execute the specified program. If the program is a user-defined script or executable, the respective agent processes access a metadata repository to obtain the specified program.

Abstract: A system and method is provided for locating, within a set of ordered items, N contiguous items having a desired attribute. The system utilizes a hierarchical bitmap structure. At the lowest level, a bitmap is provided, wherein each bit in the bitmap corresponds to a respective search item. The bit has a state indicative of a state of the search item. This lowest level bitmap is divided into segments. A higher-level bitmap is created, with each bit in this higher-level bitmap being associated with one of the segments and being assigned a state that describes a collective state of the search items associated with the segment. The higher-level bitmap may be sub-divided and the process repeated to create a hierarchical bitmap structure having any number of levels. The bitmap structure may be recursively searched to locate N contiguous ordered search items having a desired attribute.

Abstract: The current invention provides an improved system and method for locking shared resources. The invention may operate in a data processing environment including a main memory system coupled to multiple instruction processors (IPs). Lock-type instructions are included within the hardware instruction set of ones of the IPs. These lock-type instructions are executed to gain access to a software-lock stored at a predetermined location within the main memory. After activating the software-lock, further, indivisible execution of the lock-type instruction causes one or more addresses associated with the software-lock to be retrieved. These addresses are used as pointers to, in turn, retrieve the data signals protected by the software-lock. Requests for the protected data signals are issued automatically by the hardware on behalf of the requesting IP, and the IP is allowed to continue instruction execution.

Abstract: A modular, expandable, multi-port main memory system that includes multiple point-to-point switch interconnections and a highly-parallel data path structure that allows multiple memory operations to occur simultaneously. The main memory system includes an expandable number of modular Memory Storage Units, each of which are mapped to a portion of the total address space of the main memory system, and may be accessed simultaneously. Each of the Memory Storage Units includes a predetermined number of memory ports, and an expandable number of memory banks, wherein each of the memory banks may be accessed simultaneously. Each of the memory banks is also modular, and includes an expandable number of memory devices each having a selectable memory capacity. All of the memory devices in the system may be performing different memory read or write operations substantially simultaneously and in parallel.

Abstract: A tool management system and interface for a disparate set of data processing tools is disclosed. A main tool menu allows selected tools to be launched so that each tool populates a respective window. A tool is selected by choosing an associated window as the currently-active window. Next, a list of all data items that are available for processing by the tool set may be obtained. A data item that is to undergo processing may be selected. A user interface provides a list of all operations that may be used to process the selected data item, including those operations that are supported by the currently-selected tool, and those operations that are not supported by the selected tool. Following selection of the operation, processing of the selected data item is completed by automatically invoking the appropriate tool.