Abstract: A cache architecture for a multiprocessor data processing system. The cache architecture includes multiple first-level caches, two second-level caches, and main storage that is addressable by each of the processors. Each first-level cache is dedicated to a respective one of the processors. Each of the second-level caches is coupled to the other second-level cache, coupled to the main storage, and coupled to predetermined ones of the first-level caches. The range of cacheable addresses for both of the second-level caches encompasses the entire address space of the main storage. Each of the second-level caches may be viewed as dedicated for write access to the set of processors associated with the predetermined set of first-level caches, and shared for read access to the other set of processors. The dedicated and shared nature enhances system efficiency. The cache architecture includes coherency control that filters invalidation traffic between the second-level caches.

Abstract: An improved conflict detection system for use in maintaining memory coherency in a multiprocessor, shared-cache memory system. The system includes a queue for storing pointers to request addresses that resulted in cache misses. The addresses associated with the queued pointers will generally be presented to a main memory for processing based on a predetermined priority scheme. The system further includes conflict detection logic which uses the queue pointers and the request addresses provided by associated ones of the processors to determine if any two of the queued requests are associated with the same request address. If so, a conflict exists, and the request queue later in time must be re-directed to cache instead of being presented to main memory to maintain cache coherency. The system further includes a mechanism for using pointers to detect conflict situations associated with flush and replacement cache operations.

Abstract: A system and method for selectively injecting parity errors into instructions after the instructions are fetched from a storage device and are resident within the instruction processor in a data processing system. The parity errors are selectively injected according to programmable indicators, each programmable indicator being associated with one or more instructions stored in the storage device. The error-injection system also includes programmable operating modes whereby error injection will occur after every fetch of an associated instruction, or alternatively, after alternate fetches of an associated instruction. The system allows for comprehensive testing of error detection and recovery logic in an instruction processor, and further allows for comprehensive testing of the logic associated with performing a data re-fetch from the storage device.

Abstract: A control store apparatus having flexibility for reprogramming of microcode. A ROM with predetermined microcode is embedded in a microprocessor. A RAM, into which predetermined microcode may be scanned, is also embedded in the microprocessor. An Address RAM stores addresses of the ROM and RAM which are entry points into the microcode. Selection bits are respectively associated with the addresses stored in the Address RAM for selecting between microcode in the ROM and microcode in the RAM. A remapping circuit provides further flexibility. The remapping circuit includes a storage array into which predetermined ROM addresses and respectively associated RAM address may be scanned. The remapping logic circuit is directly coupled to address generation circuitry in the microprocessor for receiving a first part of the ROM address, and is directly coupled to the storage array. The remapping logic circuit is thereby capable of remapping a ROM address to a RAM address efficiently.

Abstract: A stackable modular cabinet having modular, interlocking side units which allow cabinet dimensions to be tailored both vertically and laterally to user needs while also providing the strength and stability to support heavy equipment such as electronic subassemblies. Each side unit has a pair of mating flanges with apertures for receiving and retaining fastening pins that interlock to the fastening pins of a different side unit when the respective flanges of the two side units mate. The interlocked fastening pin structure forms unified rods which extend the full height of the cabinet and which cooperates with the intervening side unit flanges. Each side unit further has re-enforced, double-sided bracket structures at opposing ends which, in combination with the pin structure, provides an unusual amount of strength to the modular cabinet.