Abstract: A non-volatile memory system including an array of cells, each having an access transistor and a capacitor sharing a floating gate. The access transistors in each row are fabricated in separate well regions, which are independently biased. Within each row, the source of each access transistor is coupled to a corresponding virtual ground line, and each capacitor structure is coupled to a corresponding word line. Alternately, the source of each access transistor in a column is coupled to a corresponding virtual ground line. Within each column, the drain of each access transistor is coupled to a corresponding bit line. Select memory cells in each row are programmed by band-to-band tunneling. Bit line biasing prevents programming of non-selected cells of the row. Programming is prevented in non-selected rows by controlling the well region voltages of these rows. Sector erase operations are implemented by Fowler-Nordheim tunneling.

Abstract: A multiple beam scanning system for scanning light beams onto a photoreceptor of an image forming apparatus. A pre-polygon input and output telecentric optical subsystem includes a beam conditioning system that focuses the light beams in a cross-scan direction, collimates the beams in the scan direction, and individually focuses the beams on a polygonal mirror deflector, which reflects the beams along a first scan path. A post-polygon input and output telecentric optical subsystem redirects the scanned beams along a second scan path and through an output window onto the photoreceptor, wherein the post-polygon subsystem includes a positive cross-scan cylindrical first optical element, a negative cross-scan cylindrical second optical element, and a positive cross-scan cylindrical third optical element. In one embodiment, the three cylindrical optical elements are cylinder mirrors. In another embodiment, one or more of the optical elements are cylinder lenses.

Abstract: A low-profile Universal-Serial-Bus (USB) assembly includes a modular USB core component that is mounted into a swivel casing. The modular USB core component includes a PCBA in which all passive components and unpackaged IC chips are attached to a single side of a PCB opposite to the metal contacts. The IC chips (e.g., USB controller, flash memory) are attached to the PCB by wire bonding or other chip-on-board (COB) technique. The passive components are attached by conventional surface mount technology (SMT) techniques. The swivel casing includes a holder that is pivotably mounted into an external housing by way of a pivot pin. The pivot pin is either a separate structure that is inserted into holes formed in the holder and housing, or is integrally formed on the holder.

Abstract: An electrophoretic-type display device including an array of microcells, where each microcell is formed by a microwell containing a quantity of ink and a polymer-based membrane connected to upper edges of the microwell. The membrane is formed by curing an aqueous or hydroalcoholic sealing solution that is overcoated on the ink-filled microwells. The ink includes an isoparaffinic-based or oil-based suspension fluid, and the peripheral side walls of the microwell have a surface energy in the range of 20 to 30 mN/m. The microwell material serves two purposes: to prevent displacement (floating) of the relatively light ink solution above the relatively heavy sealing solution, and to facilitate reliable attachment between the polymer membrane and microwell walls during subsequent curing.

Abstract: To efficiently transmit data on a wireless network, small packets that might otherwise be sent individually are aggregated into a “superframe”. This superframe can then be transmitted as a single, larger packet. To form this superframe, a plurality of tagged data packets can be aggregated into a packed aggregation block (PAB). Encapsulation data, e.g. protocol information, can be appended to the PAB. Wireless transmission information can bound the PAB and encapsulation data. Forming the superframe can be performed using an efficient combination of hardware and software. In one embodiment, aggregation of the tagged data packets can be performed by hardware without regard to the underlying protocol(s). Software can then provide protocol-handling support.

Abstract: A wireless local area network (WLAN) system can have multiple antennas to improve signal detection and decoding. A WLAN receiver in such a system includes multiple amplifiers that can appropriately size an incoming signal and an automatic gain control unit to process the received incoming signals. The amplifiers of a chain of the WLAN receiver, i.e. an antenna and associated receiver components, can be adjusted with computed gains. To optimize the wireless system detection and decoding, the automatic gain control unit can advantageously compute these gains for each amplifier in the WLAN receiver.

Abstract: A system architecture optimized for pattern match applications is provided. This system architecture includes a host computer and a pattern match accelerator (PMA), which in turn includes one or more pattern match units (PMUs) and PMU control logic. The PMU control logic can divide a database, transmitted by the host computer, such that each of the PMUs receives a database portion. Each PMU includes a main memory for storing the database portion and a programmable logic device (PLD). The PLD can perform a search and score operation on its database portion. Advantageously, the PLD can be configured to generate an index of the database portion, and then configured to perform the search and score operation using that index. The PMU control logic can assemble the results of the pattern match application from each of the PMUs.

Abstract: A bandgap reference circuit utilizes differential transistors to generate a temperature-independent bandgap voltage. In place of conventional trim elements that are connected in parallel to and adjust the resistance values of the bandgap reference circuit, current control circuits are placed in the current paths passing through the differential transistors (i.e., connected to the critical nodes located at the terminals of the differential transistors). Each current control circuit includes a resistive “trim” element (e.g., a zener diode) and associated trim pads that are separated from the critical nodes (i.e., the terminals of the differential transistors) by isolation transistors such that, during a trim/test procedure, the stray capacitances introduced by trim/test equipment probes are prevented from altering the performance of the bandgap reference circuit. In one embodiment, a current control circuit is connected to the critical node connected to the base of at least one of the differential transistors.

Abstract: A patterned integrated circuit structure defining a gap or via is fabricated solely by digital printing and bulk processing. A sacrificial lift-off pattern is printed or otherwise formed over a substrate, and then covered by a blanket layer. A mask is then formed, e.g., by printing a wax pattern that covers a region of the blanket layer corresponding to the desired patterned structure, and overlaps the lift-off pattern. Exposed portions of the blanket layer are then removed, e.g., by wet etching. The printed mask and the lift-off pattern are then removed using a lift-off process that also removes any remaining portions of the blanket layer formed over the lift-off pattern. A thin-film transistor includes patterned source/drain structures that are self-aligned to an underlying gate structure by forming a photoresist lift-off pattern that is exposed and developed by a back-exposure process using the gate structure as a mask.

Abstract: A method and apparatus for routing data in a device having a plurality of parts. A signal is received at a first port. A detection is made that the first port received the signal. Information contained in the signal is selectively routed from the first port to a data recovery circuit.

Abstract: A PCI Express-compatible flash device can include one or more flash memory modules, a controller, and an ExpressCard interface. The controller can advantageously provide PCI Express functionality as well as flash memory operations, e.g. writing, reading, or erasing, using the ExpressCard interface. A PIO interface includes sending first and second memory request packets to the flash device. The first memory request packet includes a command word setting that prepares the flash device for the desired operation. The second memory request packet triggers the operation and includes a data payload, if needed. A DMA interface includes sending the second memory request from the flash device to the host, thereby triggering the host to release the system bus for the DMA operation.

Abstract: A memory cell includes a storage capacitor and a negative differential resistance (NDR) field effect transistor (FET), wherein the NDR FET is connected between a high voltage source and the storage capacitor. A junction between the NDR FET and the storage capacitor forms a storage node of the memory cell. when a logic HIGH value is stored at the storage node, a pulsed gate bias signal turns on the NDR FET. In contrast, when a logic LOW value is stored at the storage node, the pulsed gate bias signal does not turn on the NDR FET. Thus, using the NDR FET as a pull-up element, the memory cell can exhibit a refresh behavior that is dependent on the data value stored in the memory cell. Moreover, this memory cell can be operated without a separate refresh cycle.

Abstract: A method and system for enforcing ordering rules for transactions are presented. The method and system generates transaction clump tags for each transaction before the transactions are stored in various type specific transaction queues. A transaction clump tag decoding unit decodes the transaction clump tag to recover temporal information regarding the transaction to avoid violations of the ordering rules.

Abstract: A BiCMOS integrated circuit (IC) includes a floating gate-type non-volatile memory (NVM) device that uses the polycrystalline silicon gate of a CMOS FET and the P-base and N-emitter diffusions of a bipolar transistor to provide an isolated P-type body and N-type source/drain diffusions. The P-body diffusion of the NVM device is isolated from a P-substrate by an N-well, thus facilitating the use of reduced positive and negative voltage levels to produce the onset of Fowler-Nordheim tunneling without the need for a triple-well structure. The polysilicon gate structure is formed on a suitable gate oxide over the P-body. The source/drain diffusions, which like the N-emitter diffusions of the bipolar transistor have no LDD, produce a reduced field drop across the gate oxide to allow Fowler-Nordheim tunneling from the source side.

Abstract: A word line driver is provided for accessing a DRAM cell embedded in a conventional logic process. The DRAM cell includes a p-channel access transistor coupled to a cell capacitor. The word line driver includes an n-channel transistor located in a p-well, wherein the p-well is located in a deep n-well. The deep n-well is located in a p-type substrate. A word line couples the drain of the n-channel transistor to the gate of the p-channel access transistor. A negative boosted voltage supply applies a negative boosted voltage to the p-well and the source of the n-channel transistor. The negative boosted voltage is less than ground by an amount equal to or greater than the threshold voltage of the p-channel access transistor. The deep n-well and the p-type substrate are coupled to ground. The various polarities can be reversed in another embodiment.

Abstract: A low-profile Universal-Serial-Bus (USB) assembly includes a modular USB core component and an external case. The modular USB core component includes a PCBA in which all passive components and unpackaged IC chips are attached to a single side of a PCB opposite to the metal contacts. The IC chips (e.g., USB controller, flash memory) are attached to the PCB by wire bonding or other chip-on-board (COB) technique. The passive components are attached by conventional surface mount technology (SMT) techniques. A molded housing is then formed over the IC chips and passive components such that the device has a uniform thickness. The modular USB core component is then inserted or otherwise combined with an external plastic case to provide a USB assembly. An optional carrying case is disclosed.

Abstract: An enhanced library accessible by an EDA tool can include a base curve database and a plurality of curve data sets. Each curve data set refers to a standard cell having certain timing characteristics. To determine those timing characteristics, each curve data set identifies at least one base curve (in the base curve database) as well as a starting current, a peak current, a peak voltage, and a peak time. In one embodiment, each base curve can be normalized. The base curve(s), the starting current, peak current, peak voltage, and peak time can accurately model the functioning of the IC device, e.g. represented by an I(V) curve.

Abstract: Capacitive coupling correction circuits are coupled between adjacent parallel dynamic (pre-charged) or static conductors. The capacitive coupling correction circuits effectively isolate a low voltage applied to a first conductor from a high pre-charged voltage stored on an adjacent second conductor (or vice versa). The adjacent parallel conductors can be bit lines of a memory cell. Each capacitive coupling correction circuit can include an inverter having an input terminal coupled to the first conductor, and an output terminal coupled to a first plate of a capacitor. A second plate of the capacitor is coupled to the second conductor. The capacitance of the capacitor is selected to be identical to a parasitic capacitance between the first and second conductors. As a result, there is a zero net voltage effect between the first and second conductors. The capacitive coupling correction circuits may be distributed along the length of the first and second conductors.

Abstract: A peak detector can advantageously increase its bandwidth, i.e. its charging and discharging speed, while minimizing the ripple of its output signal by sensing the charging current of a storage device. In response to that charging current, the peak detector can control a discharge current, thereby accelerating its response. For example, the peak detector can reduce a discharge current in response to an increased charging current (which indicates a charging phase) and increase the discharge current in response to a decreased charging current (which indicates a discharge phase).

Abstract: A Light-Emitting Diode (LED) driver circuit is disclosed that controls the brightness of light generated by a LED that is coupled between a first terminal and a second terminal in response to a user supplied brightness control signal. A constant current source generates a constant current that is supplied to the LED and to a shunt circuit, which his connected in parallel with the LED. A brightness control circuit generates a pulse signal having a duty cycle that is proportional to the brightness control signal, and controls the shunt circuit such that, when said pulse signal is high, the constant current is passed through the shunt circuit and the LED is turned off, and when the pulse signal is low, the constant current is passed through the LED. The duty cycle of the brightness control signal is adjusted to adjust the LED's brightness, while the LED color remains constant.