Abstract: A method for generating a linear piecewise representation of a driver output current signal includes segmenting the driver output current signal such that an integral of each segment matches an actual voltage change in corresponding portion of an associated output voltage signal (within a desired tolerance). The beginning and ending current/time values for each segment can then be compiled into the piecewise linear representation of the driver output current signal. A method for generating a model driver output current signal includes conformally mapping first and second sets of precharacterization output current data based on a weighted average of the indexing parameter (e.g., input slew or output capacitance) values for the model driver output signal and the first and second sets of precharacterization data.

Abstract: A method for determining a gain compensation value for multiple ADCs sums an absolute value of a number of ADC output samples from each of the ADCs that may be collected while the ADCs are in normal operation. In one embodiment, the ratio of the sums of the absolute values of ADC output samples may reflect the difference in gains between the ADCs, and may be used to determine the ADC gain compensation value. A method for determining an offset compensation value between for multiple ADCs averages of a number of ADC output samples from each ADC collected while the ADCs are in normal operation. In one embodiment, a difference between the ADC sample averages may reflect the difference in magnitudes of the ADC offsets for each ADC, and may be used to determine the ADC offset compensation value.

Abstract: A voltage regulator output stage can include a power device whose body to source junction is forward biased using a MOSFET trigger. The forward biasing can advantageously reduce the threshold voltage of the power device, thereby effectively increasing its gate drive as well as its output current capability. Controlling the forward biasing using the MOSFET trigger provides minimal leakage, thereby ensuring that the output stage is commercially viable as well as performance enhanced.

Abstract: A multiple mask and a multiple masking layer technique can be used to pattern a single IC layer. A resolution enhancement technique can be used to define one or more fine-line patterns in a first masking layer, wherein each fine-line feature is sub-wavelength. Moreover, the pitch of each fine-line pattern is less than or equal to that wavelength. The portions of the fine-line features not needed to implement the circuit design are then removed or designated for removal using a mask. After patterning of the first masking layer, another mask can then be used to define coarse features in a second masking layer formed over the patterned first masking layer. At least one coarse feature is defined to connect two fine-line features. The IC layer can be patterned using the composite mask formed by the patterned first and second masking layers.

Abstract: Embodiments of a digital potentiometer are disclosed that require lesser numbers of components than conventional digital potentiometers. A first string of elemental impedance devices, and at least one bulk impedance device, are provided between first and second reference terminals. The first string of elemental impedance devices is tapped by wiper switches. The at least one bulk impedance device has an impedance greater than an impedance of the first string. If desired, second and third bypassable impedance device strings also may be provided between the first and second reference terminals, with the impedance of the respective second and third strings being between the impedance of the first string and the impedance of one bulk impedance device. One or more dummy structures each including an impedance device in parallel with a permanently-on switch also may be between the first and second reference terminals to improve linearity.

Abstract: A low-profile Universal-Serial-Bus (USB) assembly includes a modular USB core component that is retractably mounted into an external housing. The modular USB core component includes a PCBA in which all passive components and unpackaged IC chips are attached to a single side of a PCB opposite to the metal contacts. The IC chips (e.g., USB controller, flash memory) are attached to the PCB by wire bonding or other chip-on-board (COB) technique. The passive components are attached by conventional surface mount technology (SMT) techniques. The housing includes a retractable mechanism that facilitates selective exposure of metal contacts, either by sliding a front portion of the modular USB core component into and out of a front opening of the housing, or by providing a cover plate that slidably covers the front portion of the modular USB core component.

Abstract: A full phase shifting mask (FPSM) can be advantageously used in a damascene process for hard-to-etch metal layers. Because the FPSM can be used with a positive photoresist, features on an original layout can be replaced with shifters on a FPSM layout. Adjacent shifters should be of opposite phase, e.g. 0 and 180 degrees. In one embodiment, a dark field trim mask can be used with the FPSM. The trim mask can include cuts that correspond to cuts on the FPSM. Cuts on the FPSM can be made to resolve phase conflicts between proximate shifters. In one case, exposing two proximate shifters on the FPSM and a corresponding cut on the trim mask can form a feature in the metal layer. The FPSM and/or the trim mask can include proximity corrections to further improve printing resolution.

Abstract: A dual-port memory system is implemented using single-port memory cells. An access arbiter having a synchronization circuit is used to prioritize and synchronize the access requests associated with the two ports. The access arbiter can also prioritize and synchronize refresh requests, in the case where the single-port memory cells require refresh. Access requests on the two ports and the refresh requests can be asynchronous. The access arbiter synchronizes the various requests by latching the requests into first-stage registers when a row access signal (RAS) is activated, and subsequently latching the contents of the first-stage registers into second-stage registers after a selected delay.

Abstract: A non-volatile memory including one or more EEPROM cell pairs. Each EEPROM cell pair includes three transistors and stores two data bits, effectively providing a 1.5 transistor EEPROM cell. An EEPROM cell pair includes a first non-volatile memory transistor, a second non-volatile memory transistor and a source access transistor. The source access transistor includes: a first source region continuous with a source region of the first non-volatile memory transistor; a second source region continuous with a source region of the second non-volatile memory transistor, and a drain region that extends downward through a first well region to contact a second well region. The first, second and third semiconductor regions and the second well region have a first conductivity type, and the first well region has a second conductivity type, opposite the first conductivity type.

Abstract: By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repeatably produced. Forming a corrugated substrate prior to actual device formation allows the ridges on the corrugated substrate to be created using high precision techniques that are not ordinarily suitable for device production. MOSFETs that subsequently incorporate the high-precision ridges into their channel regions will typically exhibit much more precise and less variable performance than similar MOSFETs formed using optical lithography-based techniques that cannot provide the same degree of patterning accuracy. Additional performance enhancement techniques such as pulse-shaped doping and “wrapped” gates can be used in conjunction with the segmented channel regions to further enhance device performance.

Abstract: A system and method for wirelessly transmitting both real-time data streams and remote control signals is described. A first transceiver can be used for detecting remote control signals associated with an end device (e.g. a television), transforming these remote control signals into wireless signals, and transmitting the wireless signals. A second transceiver can be used for receiving the wireless signals and transforming the wireless signals into the recreated remote control signals. The recreated remote control signals can then be sent to a source device (e.g. a DVD player). Because wireless signals are used (instead of infrared (IR) signals, for example), the source device can be outside the line of sight of the end device and still respond to the remote control signals.

Abstract: A multi-carrier communication system such as an OFDM or DMT system has nodes which are allowed to dynamically change their receive and transmit symbol rates, and the number of carriers within their signals. Changing of the symbol rate is done by changing the clocking frequency of the nodes' iFFT and FFT processors, as well as their serializers and deserializers. The nodes have several ways of dynamically changing the number of earners used. The selection of symbol rate and number of earners can be optimized for a given channel based on explicit channel measurements, a priori knowledge of the channel, or past experience. Provision is made for accommodating legacy nodes that may have constraints in symbol rate or the number of carriers they can support.

Abstract: A method and apparatus for wirelessly transmitting real-time data streams is described. To ensure continuous data flow, fast diversity and slow diversity can be used. Fast diversity chooses a receive antenna based on received signal parameters, such as signal strength, during the transmission header and prior to information transfer. Slow diversity stores received signal parameters from previous packets, associates the parameters with a selected antenna, and uses the parameter history to denote a “default” antenna. Additionally, receive and/or transmit beam forming can be used to maintain continuous communication between stations. Beam forming, which combines antenna signals to maximize performance, is possible when at least two transmit/receive signal processing chains are available.

Abstract: A method of providing a protocol for rekeying between two stations is disclosed. The method can include providing a first set of messages for computing a new key and reserving an auxiliary storage area for the new key. The first set of messages comprises an enable exchange. The method also includes providing a second set of messages to obsolete an old key and switch to the new key. The second set of messages comprises a transition exchange. In one embodiment, the protocol includes rekeying between multiple stations, and the rekey coordinator sends the first set of messages to a plurality of rekey participants. The auxiliary storage area allows multiplexing in both the enable and transition exchanges, thereby facilitating an efficient and safe rekey operation.

Abstract: A non-volatile memory system including an array of cells, each having an access transistor and a capacitor sharing a floating gate. The access transistors in each row are fabricated in separate well regions, which are independently biased. Within each row, the source of each access transistor is coupled to a corresponding virtual ground line, and each capacitor structure is coupled to a corresponding word line. Alternately, the source of each access transistor in a column is coupled to a corresponding virtual ground line. Within each column, the drain of each access transistor is coupled to a corresponding bit line. Select memory cells in each row are programmed by band-to-band tunneling. Bit line biasing prevents programming of non-selected cells of the row. Programming is prevented in non-selected rows by controlling the well region voltages of these rows. Sector erase operations are implemented by Fowler-Nordheim tunneling.

Abstract: A Universal Serial Bus (USB) 2.0 transceiver includes a legacy full speed and low speed (FS/LS) USB driver that includes multiple output stages. The multiple output stages are connected in parallel to an output terminal. By sequentially providing the USB data to the multiple output stages, the USB signal at the output terminal will transition between logic states in an incremental fashion as the multiple output stages sequentially switch their individual output states. Consequently, the rise/fall time for the legacy FS/LS USB driver is controlled not by the strength of the inverter transistors in the output stages, but rather by the number of stages and the time interval between application of the USB data to each stage. Therefore, by selecting an appropriate number of output stages and an appropriate timing interval, accurate control over full speed and low speed USB signal rise/fall times can be provided.

Abstract: A method and apparatus to selectively disregard co-channel transmissions on a medium uses an automatic gain control/clear channel assessment (AGC/CCA) circuit to gather signal power information, which is used to establish receiver sensitivity thresholds. Raw and cyclical power measurements of a received signal are processed by the AGC/CCA circuit to determine whether a current received signal process should be halted, and a new signal acquisition sequence begun.

Abstract: A USB transmitter 3.3V output stage includes a PMOS cascode transistor connected between a PMOS pullup transistor and a USB port data pin, an NMOS cascode transistor connected between an NMOS pulldown transistor and the data pin, and an output driver circuit that generates a pullup signal range of 0.8V to 3.3V, and a pulldown signal range of 0V to 2.5V, whereby the pullup and pulldown transistors are subjected to 2.5V gate-to-source potentials. A protection/bias circuit biases the PMOS cascode transistor during normal operation such that the pullup resistance matches the pulldown resistance, and turns off the PMOS cascode transistor to shut off the pullup path during a 5V short condition. N-wells of the PMOS pullup and cascode transistors are connected to the 3.3V supply via a resistor.

Abstract: Performing signal integrity (SI) analysis on integrated circuit designs is becoming increasingly important as these designs increase in size and complexity. Dividing a design into blocks can simplify the resulting analysis. Additionally, such blocks can be replaced with timing models, which provide a compact means of exchanging interface timing information for the blocks. To further increase the speed and accuracy of SI analysis, enhanced interface logic models (SI-ILMs) can be used. An SI-ILM can include cells in timing paths that serve as the interface between the block and other parts of the design. The SI-ILM can also include internal nets that have cross-coupling effects on interface nets and nets outside the block. By including these internal nets, SI analysis at the top-level can be both fast and accurate.

Abstract: A corona-microwave system can generate accurate capacitance-voltage (C-V) and resistance-voltage (R-V) curves, thereby allowing the accurate determination of gate film capacitance, sheet resistance of implanted regions, and mobility of a substrate under a gate. The corona-microwave system can combine a corona deposition system, a Kelvin probe, and a microwave probe. The corona deposition system can deposit a corona charge on a surface of the semiconductor. The Kelvin and microwave probes can be used to make first and second electrical measurements of a layer/region of the semiconductor. The steps of charge deposition and probe measurements can be repeated to generate a curve plotting the first and second electrical measurements. Because the first and second electrical measurements can be accurately made, the extracted information from the curve is also accurate.