Abstract: A reference output circuit for generating an output clock signal for driving signals off of an integrated circuit chip uses a switched terminated load in combination with an output buffer to generate a feedback clock signal, which is used, in combination with a reference input clock signal, to generate the output clock signal. The switched terminated load uses transistors having the same size as transistors in the output buffer. The switched terminated load draws the same DC current as the output buffer. As a result, the switched terminated load and the output buffer have the same electro-migration performance. Pull-up and pull-down MOS impedances of the switched terminated load are easily adjusted during switching periods of the switched terminated load. The design of the switched terminated load minimizes variations in the terminated load impedance due to MOS impedance variations.

Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.

Abstract: Accurate position capability can be quickly provided using a Wireless Local Area Network (WLAN). When associated with a WLAN, a wireless device can quickly determine its relative and/or coordinate position based on information provided by an access point in the WLAN. Before a wireless device disassociates with the access point, the WLAN can periodically provide time, location, and decoded GPS data to the wireless device. In this manner, the wireless device can significantly reduce the time to acquire the necessary GPS satellite data (i.e. on the order of seconds instead of minutes) to determine its coordinate position.

Abstract: A method for functional verification includes transforming an original multiphase circuit design into a phase-abstracted circuit design by identifying cyclical (repetitive) signals in the multiphase circuit design, determining a number of simulation phases for the multiphase circuit design, unwinding the multiphase circuit design by the number of phases to create an unwound design, and then applying logic reduction techniques to the unwound design using the clock-like signals to reduce (simplify) the logic in the unwound design by eliminating unused/unnecessary registers, inputs, outputs, and logic. The resulting phase-abstracted design can then be processed much more efficiently by functional verification engines than the original multiphase circuit design due to the reduced number of registers/inputs.

Abstract: A non-atmospheric pressure vapor oven system that utilizes a controllable pressure zone to facilitate fast phase change heat transfer at any desired temperature to heat or cool flat substrates, and to level temperatures across different locations of the substrates. The system enables the use of a heat transfer fluid, such as water, without being limited to a particular temperature, such as the fluid's natural boiling point at atmospheric pressure. The system includes a vapor oven (hermetic enclosure) defining a pressure chamber having sealed entry and exit ports for transferring an object (e.g., a sheet of paper) with added material (e.g., toner) through the pressure chamber, and a pressure regulation apparatus for setting the saturation temperature (boiling point) of heat transfer fluid inside the vapor oven to an optimal heating/cooling temperature by selectively controlling the pressure inside the hermetic enclosure.

Abstract: A differential amplifier includes a first pair of differential amplifiers and a second pair of differential amplifiers. These first and second pairs of differential amplifiers are connected between first power rails and are arranged to receive a differential input signal. Third and fourth pairs of differential amplifiers are connected between second rails and also connected to the differential input signal. A current summer sums a first output current of the first pair of differential amplifiers, a second output current of the second pair of differential amplifiers, a third output current of the third pair of differential amplifiers and a fourth output current of a fourth pair of differential amplifiers to produce an output signal.

Abstract: Black matrix (BM) material is deposited on glass and patterned to form walls that define an array of wells. Various surface treatments and masking schemes are utilized to achieve surface energy control of the BM glass. The surface treatments include one or more of chemically treating the BM walls by depositing hydrophobic self-assembled monolayers on the uppermost wall surfaces, and plasma treatments to control the surface energy of the various BM glass surfaces. Masking processes include backside exposure and development of photoresist, and maskless, self-aligned photo-patterning of the monolayers. Color filter ink is then injected into each well from an ink jet print head. The high surface energy of the lower and side wall surfaces facilitates wetting of the ink, and the low surface energy of the monolayers prevents intermixing of ink between adjacent wells. The ink then dries to form a color filter in each well.

Abstract: The present invention discloses an automatic gain controller with an amplifier (10) having an amplifier output connected to a mixer (20) and a receiver signal strength indicator (100) connected to the amplifier output and to a first counter (60). The first counter (60) is adapted to produce a signal to control gain of the amplifier (10) and receives its input from the receiver signal strength indicator (100) which causes the first counter (60) to count up or down depending on the strength of the signal output from the amplifier (10). The automatic gain controller also includes a second counter (70) which is connected to an applications circuit and is adapted to produce a signal to control gain of the mixer (20). The second counter (70) receives its input from a gain control signal from the applications circuit (50) and also from the first counter (60).

Abstract: An electronic data flash card includes a random number generator that generates a random number stored in the card and a host system each time the card is accessed by the host system. The random number is used by the host system to encrypt a logical branch address, a user password, and user data that is written to and stored in a secure area of the card. The random number is encrypted using a key associated with the card, and the encrypted random number is stored by the card with the associated encrypted data. The random number is not stored in the host system. A new random number is generated each time the card is queried. In a read process the host system decrypts the encrypted random number using the key, then uses the random number to decrypt the associated encrypted data. Access to read/write processes are password protected.

Abstract: A dual-personality extended USB (EUSB) system supports both USB and EUSB memory cards using an extended 9-pin EUSB socket. Each EUSB memory card includes a PCBA having four standard USB metal contact pads disposed on an upper side of a PCB, and several extended purpose contact springs that extend through openings defined in the PCB. Passive components are mounted on a lower surface of the PCB using SMT methods, and IC dies are mounted using COB methods, and then the components and IC dies are covered by a plastic molded housing. The extended 9-pin EUSB socket includes standard USB contacts and extended use contacts that communicate with the PCBA through the standard USB metal contacts and the contact springs. The PCBA includes dual-personality electronics for USB and EUSB communications.

Abstract: A low-profile Universal-Serial-Bus (USB) device includes a PCBA in which all passive components and unpackaged IC chips are attached to a single side of a PCB opposite to the metal contacts. The IC chips include, for example, a USB controller chip and a flash memory chip, or a single-chip (combined USB controller/flash memory) chip. Multiple flash IC chips are optionally stacked to increase storage capacity. The IC chip(s) are attached to the PCB by wire bonding or other chip-on-board (COB) technique. The passive components are attached by conventional surface mount technology (SMT) techniques. A molded housing is then formed over the IC chips and passive components such that the device has a uniform thickness. The low-profile USB device is optionally used as a modular insert that is mounted onto a metal case to provide a USB assembly having a plug shell similar to a standard USB male connector.

Abstract: A Solid State Drive (SSD) device includes a printed circuit board assembly (PCBA) defining rivet holes, and a support structure including parallel side frame rails defining rivet openings and support platforms for receiving and supporting the PCBA. Compression-mated rivet sets are used to connect the PCBA to the support structure, each rivet set including a female rivet portion and an associated male rivet portion. The PCBA is mounted onto the support structure such that the rivet holes are aligned with the rivet openings of the plurality of rivet openings, and then the rivet sets are mounted and secured using an automatic rivet tool such that each rivet set extends through an associated rivet hole/opening and fixedly engaged such that the PCBA and the support structure are held between end caps of the respective male and female rivet portions.

Abstract: A pen-type computer peripheral device includes an elongated housing containing a PCBA having a plug connector. The PCBA is secured to a positioning member that is actuated by way of a press-push button that is exposed through a slot defined in a wall of the housing. A spring-loaded mechanism includes a spring and a locking mechanism that locks the connector in a retracted position and a deployed position, and the spring biases the connector from the retracted position to the deployed position, or vice versa.

Abstract: A method of operating a multi-queue device, including: (1) storing a plurality of read (write) count pointers, wherein each of the read (write) count pointers is associated with a corresponding queue of the multi-queue device, (2) providing a read (write) count pointer associated with a present queue to read (write) flag logic, (3) adjusting the read (write) count pointer associated with the present queue in response to each read (write) operation performed by the present queue, (4) indicating a read (write) queue switch from the present queue to a next queue, (5) retrieving a read (write) count pointer associated with the next queue; and then (6) simultaneously providing the read (write) count pointer associated with the present queue and the read (write) count pointer associated with the next queue to the read (write) flag logic.

Abstract: A modified coffee-stain method for producing self-organized line structures and other very fine features that involves disposing a solution puddle on a target substrate, and then controlling the peripheral boundary shape of the puddle using a control structure that contacts the puddle's upper surface. The solution is made up of a fine particle solute dispersed in a liquid solvent wets and becomes pinned to both the target substrate and the control structure. The solvent is then caused to evaporate at a predetermined rate such that a portion of the solute forms a self-organized “coffee-stain” line structure on the target substrate surface that is contacted by the peripheral puddle boundary. The target structure is optionally periodically raised to generate parallel lines that are subsequently processed to form, e.g., TFTs for large-area electronic devices.

Abstract: On-chip resources of a serial buffer are accessed using priority packets of a Lite-weight protocol. A priority packet path is provided on the serial buffer to support priority packets. Normal data packets are processed on a normal data packet path, which operates in parallel with the priority packet path. The system resources of the serial buffer can be accessed in response to the priority packets, without blocking the flow of normal data packets. Thus, normal data packets may flow through the serial buffer with the maximum bandwidth supported by the serial interface. The Lite-weight protocol also supports read accesses to queues of the serial buffer (which reside on the normal data packet path). The Lite-weight protocol also supports doorbell commands for status/error reporting.

Abstract: A dual band radio is constructed using a primary and secondary transceiver. The primary transceiver is a complete radio that is operational in a stand alone configuration. The secondary transceiver is a not a complete radio and is configured to re-use components such as fine gain control and fine frequency stepping of the primary transceiver to produce operational frequencies of the secondary transceiver. The primary transceiver acts like an intermediate frequency device for the secondary transceiver. Switches are utilized to divert signals to/from the primary transceiver from/to the secondary transceiver. The switches are also configured to act as gain control devices. Antennas are selected using either wideband or narrowband antenna switches that are configured as a diode bridge having high impedance at operational frequencies on control lines that bias the diodes.

Abstract: A three terminal non-volatile memory (NVM) cell for a CMOS IC is formed by a standard CMOS process flow. The NVM cell includes two transistors that share a common floating gate. The floating gate includes a first portion disposed over the channel region of the first (NMOS) transistor, a second portion disposed over the channel region of the second (NMOS or PMOS) transistor, and a third portion extending into an enlarged drain diffusion area away from the channel regions, whereby the gate-to-drain capacitance is higher than the gate-to-source capacitances. A pocket implant or CMOS standard LV N-LDD is formed under the second transistor to enhance CHE programming. Both HV LDD and LV LDD implants are introduced together enabling LDD implant merging under the floating gate extension. The floating gate is formed using substantially T-shaped, C-shaped, U-shaped, Y-shaped or O-shaped polysilicon structures. Various array addressing schemes are disclosed.

Abstract: A concentrating solar collector that utilizes a solar collector optical system to concentrate solar light onto a PV cell (image plane), wherein the solar collector optical system includes an array of first optical elements that divide the solar light into separate beams, and a secondary optical system that integrates (superimposes) the separate beams in a defocused state at the image plane, thereby forming a uniform light distribution pattern on the PV cell. The secondary optical system is positioned at a distance from the aperture plane, whereby the rays of each separate beam leaving the secondary optical element are parallel. The image plane (PV cell) is located at the back focal point of the second image element, whereby all of the separate beams are superimposed on the PV cell in a defocused state. Optional intervening third optical elements are used to increase the acceptance angle.

Abstract: A fast settling AGC system includes a “fast settle” comparator that facilitates fast settling of strong radio receiver output signals from a maximum to an intermediate voltage level at the start of each transmission burst, and a “normal” AGC comparator that further settles the output signal from the intermediate voltage level to a desired target output voltage level at a slower “normal” rate. The gain control signal components generated by both the “fast settle” comparator and the “normal” AGC comparator are summed and applied to the gain control terminal of a variable gain amplifier. The gain control signal component generated by the “fast settle” comparator has a higher current level than the gain control signal component generated by the “normal” comparator, but is terminated when receiver output signal drops to the intermediate voltage level.