Abstract: A Cassegrain-type concentrating solar collector cell includes primary and secondary mirrors disposed on opposing convex and concave surfaces of a light-transparent (e.g., glass) optical element. Light enters an aperture surface surrounding the secondary mirror, and is reflected by the primary mirror toward the secondary mirror, which re-reflects the light onto a photovoltaic cell. The photovoltaic cell is mounted on a central portion of heat spreader that extends over the primary mirror. The heat spreader transmits waste heat from the photovoltaic cell in a manner that evenly distributes the heat over the optical element, thereby maximizing the radiation of heat from the aperture surface into space. The heat spreader includes a thick copper layer formed on a flexible substrate (e.g., polyimide film) that is patterned with radial arms that facilitate mounting onto the convex surface of the optical element.

Abstract: A persistence-driven optimization technique is provided in which nets can be ranked based on unpredictability and likely quality of result impact. The top nets in that ranking can be routed and their parasitics extracted. A timing graph can be back-annotated with route-based delays and parasitics for the selected nets. At this point, synthesis can be run using actual route-based delays and parasitics for the selected nets, with their routes being updated incrementally as needed. In one embodiment, the nets can be re-ranked after synthesis. Finally, these routes can be preserved across the subsequent global routing of the remaining nets.

Abstract: A method and system of optimizing transmit beam forming in a multiple radio wireless system is provided. A stimulus signal can be provided to an analog receive input of a device under test (DUT), wherein the DUT includes multiple radios. A receive phase and amplitude can be measured at baseband using the stimulus signal for each radio. At this point, a receive weight and its conjugate can be determined using the receive phases and amplitudes. A calibration vector and its conjugate can also be determined, wherein a product of the receive weight conjugate and the calibration vector conjugate generate a transmit weight. This transmit weight can be applied to transmit signals during the transmit beam forming using the multiple radios.

Abstract: A USB device including a housing and a rear cap that is rotatably connected to the housing to facilitate deploying and retracting a plug connector through a front opening of the housing. The plug connector is fixedly connected onto the front end of a sliding rack assembly that is disposed in housing such that the sliding rack assembly is slidable along a longitudinal axis. The sliding rack assembly includes a carrier including a carrier tray for supporting electronic devices and an elongated positioning rod extending from a rear portion of the carrier tray. The positioning rod is operably engaged with an actuator portion such that manual rotation of the rear cap relative to the housing around the longitudinal axis causes the sliding rack assembly to slide inside the housing between retracted and deployed positions.

Abstract: A PCI Express-compatible flash device can include one or more flash memory modules, a controller, and an ExpressCard interface. The controller can advantageously provide PCI Express functionality as well as flash memory operations, e.g. writing, reading, or erasing, using the ExpressCard interface. A PIO interface includes sending first and second memory request packets to the flash device. The first memory request packet includes a command word setting that prepares the flash device for the desired operation. The second memory request packet triggers the operation and includes a data payload, if needed. A DMA interface includes sending the second memory request from the flash device to the host, thereby triggering the host to release the system bus for the DMA operation.

Abstract: A method and apparatus for detecting radar signals in single and multiple (extension) channel wireless network frequencies uses spectral and DC analysis. Spectral images produced through a Fast Fourier transform may be captured and analyzed to determine if any radar signals may be present within the selected wireless network frequencies. A plurality of spectral images may also be analyzed to determine if frequency shifting radar signals are present as well. DC analysis of the power contained at the wireless carrier frequencies may detect radar signals that may be centered near those frequencies.

Abstract: A flash memory card includes a differential datapath that enables communications between the flash memory card and a host device to be performed using differential signals. The differential datapath can translate between the differential signals and card-specific signals that control read/write operations to the memory array of the flash memory card. The card-specific signals can be standard MultimediaCard, Secure-Digital card, Memory Stick, or CompactFlash card signals, among others. A host device that provides differential data transfer capability can include a similar differential datapath. By using differential data transfer rather than conventional clocked data transfer, overall data bandwidth between a flash memory card and a host device can be significantly increased, while simultaneously decreasing power consumption and pin requirements.

Abstract: A differential signal driver includes a pre-driver configured to generate a constant charging current and a constant discharging current. A first capacitor of the pre-driver is charged with the charging current when a differential input signal has a first state, and discharged with the discharging current when the differential input signal has a second state, thereby developing a first output control voltage on the first capacitor. A second capacitor of the pre-driver is discharged with the discharging charging current when the differential input signal has the first state, and charged with the charging current when the differential input signal has the second state, thereby developing a second output control voltage on the second capacitor. An output driver circuit generates a differential output signal in response to the first and second output control voltages. The slew rate of the differential output signal is controlled by the charging and discharging currents.

Abstract: A slice level reference generator and method for performing improved data slicing operations when gaps are present in a data stream is disclosed that involves applying a nominal reference signal to the comparator the during signal gaps. In one embodiment, a receiver circuit includes a slice level detector and a comparator that operate in a conventional manner, and control circuitry that utilizes a signal detector and a switch to store a slice level reference signal generated by the slice level detector during a first signal burst, and to apply the stored reference signal to the comparator during signal gaps. In one embodiment a timer circuit is used to detect signal gaps. In another embodiment a predetermined fixed reference signal is applied to the comparator during signal gaps.

Abstract: Spurs cause significant problems with signal detecting, amplifier gain adjustment, and signal decoding. Various techniques can be used to mitigate the effects of spurs on a received signal. Generally, these techniques work by either canceling or ignoring the spurs. For example, a pilot mask can be used to ignore pilot information in one or more sub-channels. A Viterbi mask can determine the weighting given to bits in a sub-channel based on spur and data rate information. Channel interpolation can compute a pseudo channel estimate for a sub-channel known to have a spur location can be computed by interpolating the channel estimates of adjacent good sub-channels. Filtering of the received signal using a low-pass filter, a growing box filter, or a low-pass filter with self-correlation can be used to cancel a spur.

Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.

Abstract: Systems and methods for communicating using various protocols through the Secured Digital (SD) physical interface are disclosed. The invention covers, among others, single-mode and multi-mode hosts, single-mode and multi-mode devices, as well as techniques for initializing these hosts and devices in order to facilitate the aforementioned communication.

Abstract: A simulated wafer image of a physical mask and a defect-free reference image are used to generate a severity score for each defect, thereby giving a customer meaningful information to accurately assess the consequences of using a mask or repairing that mask. The defect severity score is calculated based on a number of factors relating to the changes in critical dimensions of the neighbor features to the defect. A common process window can also be used to provide objective information regarding defect printability. Certain other aspects of the mask relating to mask quality, such as line edge roughness and contact corner rounding, can also be quantified by using the simulated wafer image of the physical mask.

Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.

Abstract: Method and apparatus to dynamically configure the signal reception selectivity of a plurality of transceivers is described. In one embodiment, a transceiver includes a receiver circuit having two or more filter circuits. Each of the filter circuits is configured to pass RF signals from a different portion of an overall receiver bandwidth. When two or more receivers in proximity to one another are simultaneously operating, the filter circuits of the respective receiver are dynamically configured to different RF frequency passbands to minimize interference and cross talk between receivers and transmitters.

Abstract: A non-volatile memory (NVM) system includes a set of NVM cells, each including: a NVM transistor; an access transistor coupling the NVM transistor to a corresponding bit line; and a source select transistor coupling the NVM transistor to a common source. The NVM cells are written by a two-phase operation that includes an erase phase and a program phase. A common set of bit line voltages are applied to the bit lines during both the erase and programming phases. The access transistors are turned on and the source select transistors are turned off during the erase and programming phases. A first control voltage is applied to the control gates of the NVM transistors during the erase phase, and a second control voltage is applied to the control gates of the NVM transistors during the program phase. Under these conditions, the average required number of Fowler-Nordheim tunneling operations is reduced.

Abstract: An MMC/SD core unit includes a PCBA in which all passive components and unpackaged IC chips are attached to a single side of a PCB opposite to the metal contacts. The IC chips include, for example, a controller chip and a flash memory chip, or a single-chip (combined controller/flash memory) chip. Multiple flash IC chips are optionally stacked to increase storage capacity. The IC chip(s) are attached to the PCB by wire bonding or other chip-on-board (COB) technique. The passive components are attached by conventional surface mount technology (SMT) techniques. A molded housing is then formed over the IC chips and passive components such that the device has a uniform thickness. The MMC/SD core unit is then inserted or otherwise mounted in an eternal casing to provide a finished MMC/SD device.

Abstract: Phase shifting allows generating very narrow features in a printed features layer. Thus, forming a fabrication layout for a physical design layout having critical features typically includes providing a layout for shifters. Specifically, pairs of shifters can be placed to define critical features, wherein the pairs of shifters conform to predetermined design rules. After placement, phase information for the shifters associated with the set of critical features can be assigned. Complex designs can lead to phase-shift conflicts among shifters in the fabrication layout. An irresolvable conflict can be passed to the design process earlier than in a conventional processes, thereby saving valuable time in the fabrication process for printed circuits.

Abstract: Rate adaptation is accurately provided by using an average SNR technique, a predicted PER technique, or an EVM to PER mapping technique. An average SNR is computed by averaging EVM values in a particular domain. Using the computed average SNR, an optimized rate is determined. The predicted PER technique includes computing EVM values for a current packet, determining an average BER using these EVM values for each data rate, determining an average SNR from this average BER, using the average SNR and a PER versus SNR curve to determine the predicted PER for each data rate, and using a data rate and the predicted PER to compute the predicted throughput for that data rate. In the last technique, an EVM is mapped to a packet error rate (PER) for each data rate. A throughput is computed for each data rate and PER. A data rate with a high throughput is selected.

Abstract: An electronic device includes a scan-based circuit that includes a combinational decompressor, a combinational compressor, scan chains, and logic which typically includes a number of storage elements. Cycle time normally needed to shift data into or out of a scan cell to/from an external interface of the electronic device is reduced by use of one or more additional storage element(s) located between the external interface and one of the combinational elements (decompressor/compressor). The one or more additional storage element(s) form a pipeline that shifts compressed data in stages, across small portions of an otherwise long path between the external interface and one of the combinational elements. Staged shifting causes the limit on cycle time to drop to the longest time required to traverse a stage of the pipeline. The reduced cycle time in turn enables a corresponding increase in shift frequency.