Abstract: The present invention provides a method for determining timing delays associated with the placement and routing delays of an integrated circuit. In particular, the present invention determines the area of each region wherein a region includes a group or subgroup of circuit elements for use in designing an integrated circuit. Once the area for each region is obtained, substantially more accurate and more design specific wireload model and net parasitics can be obtained. The wireload models or net parasitics can then be supplied to other CAE tools to create a modified netlist. Moreover, the present invention provides a process which allows the user to account for the RC time constant effects of wire delay on a hierarchical block basis thereby improving the accuracy of the wire placement and routing delay estimate while preserving the performance benefits of a traditional simplified equation.

Abstract: A receiver performs rapid adaptive interference canceling for use in despreading multiple CDMA channels sharing the same RF front end. The receiver includes a buffer (22) for providing for overlapping time samples and rate adaptation, a windowing function (24) for improving interference rejection capability and a FFT (26) for calculating the input power spectrum. The receiver further includes a circuit (28, 30) to whiten the input power spectrum. The whitened power spectrum is multiplied (32) against the frequency domain version of different spreading sequences and the inverse FFT (40) of the product is performed. The output of this inverse FFT is buffered (44) to provide multiple despread output channels, with a plurality of code phases for further processing.

Abstract: A cellular communication network (10) and method operates at frequencies above 2 GHz and achieves widespread coverage within a cell (14) by adapting routing channels, symbol rates, and FEC coding processes (78) to current RF broadcast conditions. A portion of subscriber nodes (16) act as repeaters for a base node (12). If subscriber nodes (16) cannot directly communicate with the base node (12), their communications may be indirectly routed to the base node (12) through one or more repeating subscriber nodes (16'). If current conditions do not support a high data rate, then lower data rates are supported by selection of FEC coding processes (78). If increasingly inclusive FEC coding does not achieve a data rate supportable by current conditions, slower symbol rates may be used. Communications at slower symbol rates may utilize narrower frequency bands thus keeping wider frequency bands available for higher speed usage.

Abstract: An integrated radiating and coupling device (30) for a duplex communication radio (26) is formed using a ferrite body (36) having first and second surfaces. A multi-port circulator (40) is mounted on the first surface. The circulator (40) has at least three ports; a transmitter port (42), a receiver port (44), and an antenna port (38). A patch antenna (32) is mounted on the second surface and connected to the antenna port (38) by, for example, a wire passing through a via hole in the ferrite body (36). The device (30) provides transmitter and receiver isolation, antenna coupling, and filtering in a single integrated structure.

Abstract: A method and apparatus for hardening current steering logic (CSL) to soft errors (charged particles passing through and upsetting the logic state of an integrated circuit) includes a hardened CSL circuit or cell (20), including three or more circuit cell elements (21) in parallel. The circuit cell elements (21) redundantly perform a single cell function. Each of the circuit cell elements (21) is coupled to soft error immune resistive elements (24 and 25) within a summing element (22). Current (23) is steered through the resistive elements (24 and 25) depending upon input signals (26) to each of the circuit cell elements (21). The logical output signal (27) is unaffected by a single soft error event since the majority of the total current (23) remains steered through the correct resistive element (24 or 25).

Abstract: A computer system includes a Key Certification Agency (KCA) (12), a host computer (16), and a number of remote terminals (14). The KCA (12) uses incompatible encryption processes (96, 98) to encrypt session control data and to store the data as various messages (44, 46, 48) in a user token (26). The token (26) may be removably installed in any remote terminal (14). To set up a communication session, the token uncovers one of the messages (48) using a crypto-uncovering agent which is known to the user. This message includes a remote traffic key after deciphering, but the key is never transmitted to the host. The host (16) deciphers the other messages (44, 46) and constructs a host traffic key in response to data contained therein. No plain text is transmitted during the setup or the session.

Abstract: A dual traveling wave resonator filter includes a microstrip line to receive an input signal at a first end and first and second traveling wave resonator rings. Each traveling wave resonator ring is in close proximity to the microstrip line such that first and second resonant first combined signals are induced, respectively, in each of the first and second traveling wave resonator rings in response to the input signal on the microstrip line. A band-reject signal is rejected from the microstrip line and a pass-band signal is produced from the microstrip line at a second end.

Abstract: A microwave monolithic integrated circuit (MMIC) RF-generated bias circuit and method includes an input for receiving an RF signal. A rectifier coupled to the input and to electrical ground produces a rectified RF signal in response. A voltage divider coupled to the rectifier and to the electrical ground receives the rectified RF signal and produces a DC voltage therefrom. An output is coupled to the voltage divider for applying the DC voltage to a MMIC field effect transistor (FET) for biasing. No separate bias battery is required, and efficiency is optimized because the generated bias voltage increases to the point where the amplifier voltage begins to decrease, which in turn reduces the generated bias voltage. The derived bias voltage may be used to control other circuits (e.g., other amplifiers, oscillators, mixers, etc.) which require detection of RF presence.

Abstract: A method and apparatus for power combining or dividing handles high impedance line requirements in n-way combiners (15) and dividers (10) using phase delay networks (12, 14) to transform impedances to a lower, intermediate impedance. Each impedance transformation is accomplished using a stepped impedance or tapered impedance transmission line (26). The method and apparatus provides isolation between input or output ports (11, 22 and 24, 13) in power combining or dividing circuits using an incremental phase delay network (12) of prescribed electrical phase lengths (22, 24) to provide phase cancellation. The power divider (10) and combiner (15) can be used in power amplifiers and in communication devices.

Abstract: A low profile hermetic electrical connector includes a conductive layer with opposite first and second conductive layer surfaces. An inner electrical isolation layer is coupled between the first conductive layer surface and a first contact and an outer electrical isolation layer is coupled between the second conductive layer surface and a second contact. A contact interconnector electrically couples the first contact and the second contact through the inner electrical isolation layer, the conductive layer, and the outer electrical isolation layer without electrically contacting the conductive layer, creating a serpentine, low flow path for vapor through the adhesive layers. In a hermetic electrical cable end connector, the first contact is electrically coupled to a first conductor through a first interconnector and a second contact is electrically coupled to a second conductor through a second interconnector. Two additional electrical isolation layers are required.

Abstract: A method for designing and making an RF transformer has been provided. The method utilizes a model for an RF transformer wherein the model has parameters that directly relate to a physical construction of the components of the transformer, namely, a core and a twisted wire. The method separates the core from the twisted wire so that characteristics of each can be separately determined. These determined characteristics are then optimized and used to design and make a transformer.

Abstract: A 3 state BiCMOS output buffer (100) with power down capability has been provided. The buffer includes an input stage (102), responsive to an input signal, an output coupled to both a pull-up driver (114), and an output pull-down driver (116) wherein the drivers provide an output signal at an output of the buffer in response to the input signal. Additionally, the buffer includes a power down sense circuit (108), coupled to a power supply node (118), for turning off an output pull-up transistor (214) when the power supply node is powered down and thus eliminating leakage paths within the buffer. The buffer also includes a noise limiting circuit (112) for slowing down a high to low transition at the output of the buffer thereby reducing the switching noise of the buffer while not affecting the overall speed of the buffer.

Abstract: An impedance transforming power divider/combiner includes a first transmission line (60) with a first terminal (65) and N transmission line fingers (65, 66, 68, 70) terminating in N transmission line finger ends. N transmission lines (28, 38, 48, 58) having N first and second ends are positioned in close proximity to the N transmission line fingers (65, 66, 68, 70) in one-to-one correspondences. The N second ends of the N transmission lines (28, 38, 48, 58) are coupled through N individual impedances (20, 30, 40, 50) to N terminals (25, 35, 45, 55). If signal power is provided to the first terminal (64), the signal power is divided into N signal power outputs at the N terminals (25, 35, 45, 55). If signal power is provided to the N terminals (25, 35, 45, 55), a combined signal power results at the first terminal (65).

Abstract: A multilateration location system (12) includes a locatable unit (16) and any number of known-position locators (14). A time of arrival detector (22) determines instants in time when a location signal (20) transmitted by the locatable unit (16) arrives at various known-position locators (14). For each combination of two known-position locators (14) that receive the location signal (20), a pre-estimation process (32) determines whether the difference in arrival times is less than or equal to a maximum propagation duration for the locator pair. The maximum propagation duration is based upon the distance between the locators (14) in the locator pair. If the difference is greater than the maximum propagation duration, the difference is omitted from the data set processed by a multilateration calculation process (34). A post estimation filtering process (36) screens out location estimates that are too distant from a predicted position.

Abstract: A technique for achieving impedance transformations utilizing transmission lines has been provided. This technique involves placing additional distributed capacitance along the length of a transmission line thereby reducing the effective characteristic impedance of the transmission line. The effective wavelength for the transmission line is also reduced thereby substantially reducing the electrical length of a quarter wavelength matching network and making the transmission line practical and effective even at low frequencies.

Abstract: An arithmetic engine includes a first dual multiplier accumulator (MAC) for receiving input data and for producing first dual MAC output data. A second dual MAC is coupled in parallel to the first dual MAC. The second dual MAC receives the input data and produces second dual MAC output data. An adder array is coupled to both the first dual MAC and to the second dual MAC. The adder array receives the input data, the first dual MAC output data, and the second dual MAC output data and produces arithmetic engine output data. Each dual MAC comprises a multiplier cross point switch, multiplier registers, a register selector, and parallel multipliers. Each adder array comprises a cross point switch, adder registers, a register selector, adder, and condition code determiner.

Abstract: A MMIC FET mixer and method includes a RF input port for receiving a RF signal, a feedback control input for receiving a feedback signal, and a LO input port for receiving a LO signal. A feedback controller is coupled to the RF amplifier, the feedback controller for producing a controlled RF signal in response to the feedback signal. A constant current source is coupled to the feedback controller, to the RF amplifier and to the LO input port. The constant current source receives a DC offset voltage, the controlled RF signal, and the LO signal and produces an IF output signal at an IF output port. The IF output signal is proportional to the DC offset voltage, to the RF signal, and to the LO signal.

Abstract: A differential track and hold amplifier circuit (200) is provided. The track and hold amplifier includes an input transconductance amplifier (212), an output amplifier (111), and a second transconductance amplifier (214). The track and hold circuit further includes a switching circuit (108) for coupling the output of the input transconductance amplifier to a capacitor (110) in the output stage of the track and hold circuit during track mode, and for decoupling the capacitor from the input amplifier during hold mode. The track and hold circuit further includes a subtractor circuit (103) for reducing a common mode voltage of the output of the input transconductance amplifier, thereby maintaining a stable voltage across the capacitor during hold mode. Further, during hold mode, the second transconductance amplifier acts in a negative feedback configuration to reduce the gain of the input amplifier to attenuate its output signal.

Abstract: A circuit (10) for enhancing logic transitions appearing on a line (34) has been provided. The circuit includes a first comparator (14) for sensing when a voltage on the line exceeds a first level and subsequently pulling the voltage on the line to a first predetermined voltage. The circuit also includes a second comparator (12) for sensing when the voltage on the line falls below a second level and subsequently pulling the voltage on the line to a second predetermined voltage.

Abstract: A non-intrusive mounting system and method for coupling microwave instruments to a container flange having an opening into a container. The mounting system includes a microwave transparent window and a mounting flange having a window recess for accommodating the microwave transparent window. The microwave transparent window is compressively fastened over the container opening between the mounting flange and the container flange. Microwave instruments such as radar level sensing apparatus can be mounted on and removed from the mounting flange without breaking the seal to the container.